Searched refs:AlignedAddr (Results 1 - 4 of 4) sorted by relevance
/external/clang/test/CodeGen/ |
H A D | arm-vector-align.c | 14 typedef float AlignedAddr __attribute__ ((aligned (16))); typedef 15 void t1(AlignedAddr *addr1, AlignedAddr *addr2) {
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/external/llvm/include/llvm/Support/ |
H A D | Allocator.h | 239 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); local 240 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); 241 char *AlignedPtr = (char*)AlignedAddr; 249 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); local 250 assert(AlignedAddr + Size <= (uintptr_t)End && 252 char *AlignedPtr = (char*)AlignedAddr;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1189 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); local 1240 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1279 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1304 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1427 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); local 1485 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1516 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1534 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3084 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, 3113 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, 3188 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, 3204 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
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