Searched refs:BankSwizzle (Results 1 - 4 of 4) sorted by relevance
/external/llvm/lib/Target/AMDGPU/ |
H A D | R600InstrInfo.h | 52 enum BankSwizzle { enum in class:llvm::R600InstrInfo 120 const std::vector<R600InstrInfo::BankSwizzle> &Swz, 122 R600InstrInfo::BankSwizzle TransSwz) const; 126 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 128 R600InstrInfo::BankSwizzle TransSwz) const; 131 /// returns true and the first (in lexical order) BankSwizzle affectation 136 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to 141 std::vector<BankSwizzle> &BS,
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H A D | R600InstrInfo.cpp | 387 R600InstrInfo::BankSwizzle Swz) { 415 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { 444 const std::vector<R600InstrInfo::BankSwizzle> &Swz, 446 R600InstrInfo::BankSwizzle TransSwz) const { 493 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 505 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; 513 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, 515 R600InstrInfo::BankSwizzle TransSwz) const { 528 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, 550 std::vector<BankSwizzle> [all...] |
H A D | R600Packetizer.cpp | 236 std::vector<R600InstrInfo::BankSwizzle> &BS, 271 // Is there a BankSwizzle set that meet Read Port limitations ? 301 std::vector<R600InstrInfo::BankSwizzle> BS;
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 505 int BankSwizzle = MI->getOperand(OpNo).getImm(); local 506 switch (BankSwizzle) {
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