| /external/llvm/lib/Transforms/Scalar/ |
| H A D | LoopLoadElimination.cpp | 93 const StoreToLoadForwardingCandidate &Cand) {
94 OS << *Cand.Store << " -->\n";
95 OS.indent(2) << *Cand.Load << "\n";
210 for (const auto &Cand : Candidates) {
215 LoadToSingleCand.insert(std::make_pair(Cand.Load, &Cand));
225 if (Cand.Store->getParent() == OtherCand->Store->getParent() &&
226 Cand.isDependenceDistanceOfOne(PSE) &&
229 if (getInstrIndex(OtherCand->Store) < getInstrIndex(Cand.Store))
230 OtherCand = &Cand;
92 operator <<(raw_ostream &OS, const StoreToLoadForwardingCandidate &Cand) argument
356 propagateStoredValueToLoadUsers(const StoreToLoadForwardingCandidate &Cand, SCEVExpander &SEE) argument
[all...] |
| /external/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 2317 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) { argument
2321 switch (Cand.Reason) {
2325 P = Cand.RPDelta.Excess;
2328 P = Cand.RPDelta.CriticalMax;
2331 P = Cand.RPDelta.CurrentMax;
2334 ResIdx = Cand.Policy.ReduceResIdx;
2337 ResIdx = Cand.Policy.DemandResIdx;
2340 Latency = Cand.SU->getDepth();
2343 Latency = Cand.SU->getHeight();
2346 Latency = Cand
2371 tryLess(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) argument
2388 tryGreater(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason) argument
2405 tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone) argument
2431 tracePick(const GenericSchedulerBase::SchedCandidate &Cand, bool IsTop) argument
2578 tryPressure(const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF) argument
2654 tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary &Zone, const RegPressureTracker &RPTracker, RegPressureTracker &TempTracker) argument
2791 pickNodeFromQueue(SchedBoundary &Zone, const RegPressureTracker &RPTracker, SchedCandidate &Cand) argument
3033 tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) argument
3066 pickNodeFromQueue(SchedCandidate &Cand) argument
[all...] |
| H A D | RegAllocGreedy.cpp | 350 void growRegion(GlobalSplitCandidate &Cand);
1036 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) { argument
1039 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
1072 if (Cand.PhysReg)
1073 addThroughConstraints(Cand.Intf, NewBlocks);
1093 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) { argument
1099 Cand.reset(IntfCache, 0);
1105 SpillPlacer->prepare(Cand.LiveBundles);
1107 // The static split cost will be zero since Cand.Intf reports no interference.
1109 if (!addSplitConstraints(Cand
1153 calcGlobalSplitCost(GlobalSplitCandidate &Cand) argument
1229 GlobalSplitCandidate &Cand = GlobalCand[CandIn]; local
1238 GlobalSplitCandidate &Cand = GlobalCand[CandOut]; local
1278 GlobalSplitCandidate &Cand = GlobalCand[CandIn]; local
1286 GlobalSplitCandidate &Cand = GlobalCand[CandOut]; local
1406 GlobalSplitCandidate &Cand = GlobalCand[NumCands]; local
1468 GlobalSplitCandidate &Cand = GlobalCand[BestCand]; local
1480 GlobalSplitCandidate &Cand = GlobalCand.front(); local
[all...] |
| /external/clang/lib/Sema/ |
| H A D | SemaOverload.cpp | 1186 for (OverloadCandidateSet::iterator Cand = Conversions.begin();
1187 Cand != Conversions.end(); ++Cand)
1188 if (Cand->Viable)
1189 ICS.Ambiguous.addConversion(Cand->Function);
4210 for (OverloadCandidateSet::iterator Cand = CandidateSet.begin();
4211 Cand != CandidateSet.end(); ++Cand)
4212 if (Cand->Viable)
4213 ICS.Ambiguous.addConversion(Cand
[all...] |
| H A D | SemaLookup.cpp | 2857 for (auto *Cand : Candidates) {
2858 if (Cand->isInvalidDecl())
2861 if (UsingShadowDecl *U = dyn_cast<UsingShadowDecl>(Cand)) {
2866 Cand = U->getTargetDecl();
2868 if (Cand->isInvalidDecl())
2872 if (CXXMethodDecl *M = dyn_cast<CXXMethodDecl>(Cand)) {
2881 dyn_cast<FunctionTemplateDecl>(Cand)) {
2892 assert(isa<UsingDecl>(Cand) && "illegal Kind of operator = Decl");
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineScheduler.h | 848 void traceCandidate(const SchedCandidate &Cand);
896 void tryCandidate(SchedCandidate &Cand,
957 void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
959 void pickNodeFromQueue(SchedCandidate &Cand);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 146 MachineInstr *MergeOpsUpdate(const MergeCandidate &Cand);
796 MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) { argument
797 const MachineInstr *First = Cand.Instrs.front();
805 for (const MachineInstr *MI : Cand.Instrs) {
836 MachineInstr *LatestMI = Cand.Instrs[Cand.LatestMIIdx];
846 if (Cand.CanMergeToLSDouble)
849 if (!Merged && Cand.CanMergeToLSMulti)
857 iterator EarliestI(Cand.Instrs[Cand
[all...] |
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 421 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]); local
423 if (Cand == this || getSubRegIndex(Cand))
425 // Check if each component of Cand is already a sub-register.
429 assert(!Cand->ExplicitSubRegs.empty() &&
431 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) {
432 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j]))
440 // If some Cand sub-register is not part of this register, or if Cand only
445 // Each part of Cand i
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 2730 std::vector<LoopCand> Cand;
2757 Cand.push_back(LoopCand(&B, PB, EB));
2761 for (auto &C : Cand)
|