/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { argument 74 switch ((Imm >> 6) & 0x7) { 85 static inline unsigned getShiftValue(unsigned Imm) { argument 86 return Imm & 0x3f; 99 unsigned Imm) { 100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); 110 return (STEnc << 6) | (Imm & 0x3f); 118 static inline unsigned getArithShiftValue(unsigned Imm) { argument 119 return Imm 98 getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm) argument 123 getExtendType(unsigned Imm) argument 138 getArithExtendType(unsigned Imm) argument 170 getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm) argument 178 getMemDoShift(unsigned Imm) argument 184 getMemExtendType(unsigned Imm) argument 213 processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding) argument 342 getFPImmFloat(unsigned Imm) argument 370 getFP16Imm(const APInt &Imm) argument 396 getFP32Imm(const APInt &Imm) argument 424 getFP64Imm(const APInt &Imm) argument 454 isAdvSIMDModImmType1(uint64_t Imm) argument 459 encodeAdvSIMDModImmType1(uint64_t Imm) argument 463 decodeAdvSIMDModImmType1(uint8_t Imm) argument 469 isAdvSIMDModImmType2(uint64_t Imm) argument 474 encodeAdvSIMDModImmType2(uint64_t Imm) argument 478 decodeAdvSIMDModImmType2(uint8_t Imm) argument 484 isAdvSIMDModImmType3(uint64_t Imm) argument 489 encodeAdvSIMDModImmType3(uint64_t Imm) argument 493 decodeAdvSIMDModImmType3(uint8_t Imm) argument 499 isAdvSIMDModImmType4(uint64_t Imm) argument 504 encodeAdvSIMDModImmType4(uint64_t Imm) argument 508 decodeAdvSIMDModImmType4(uint8_t Imm) argument 514 isAdvSIMDModImmType5(uint64_t Imm) argument 520 encodeAdvSIMDModImmType5(uint64_t Imm) argument 524 decodeAdvSIMDModImmType5(uint8_t Imm) argument 530 isAdvSIMDModImmType6(uint64_t Imm) argument 536 encodeAdvSIMDModImmType6(uint64_t Imm) argument 540 decodeAdvSIMDModImmType6(uint8_t Imm) argument 546 isAdvSIMDModImmType7(uint64_t Imm) argument 551 encodeAdvSIMDModImmType7(uint64_t Imm) argument 555 decodeAdvSIMDModImmType7(uint8_t Imm) argument 561 isAdvSIMDModImmType8(uint64_t Imm) argument 566 decodeAdvSIMDModImmType8(uint8_t Imm) argument 571 encodeAdvSIMDModImmType8(uint64_t Imm) argument 576 isAdvSIMDModImmType9(uint64_t Imm) argument 582 encodeAdvSIMDModImmType9(uint64_t Imm) argument 586 decodeAdvSIMDModImmType9(uint8_t Imm) argument 596 isAdvSIMDModImmType10(uint64_t Imm) argument 616 encodeAdvSIMDModImmType10(uint64_t Imm) argument 644 decodeAdvSIMDModImmType10(uint8_t Imm) argument 658 isAdvSIMDModImmType11(uint64_t Imm) argument 665 encodeAdvSIMDModImmType11(uint64_t Imm) argument 693 decodeAdvSIMDModImmType11(uint8_t Imm) argument 708 isAdvSIMDModImmType12(uint64_t Imm) argument 714 encodeAdvSIMDModImmType12(uint64_t Imm) argument 742 decodeAdvSIMDModImmType12(uint8_t Imm) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZTargetTransformInfo.cpp | 34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { argument 46 if (Imm == 0) 49 if (Imm.getBitWidth() <= 64) { 51 if (isInt<32>(Imm.getSExtValue())) 54 if (isUInt<32>(Imm.getZExtValue())) 57 if ((Imm.getZExtValue() & 0xffffffff) == 0) 67 const APInt &Imm, Type *Ty) { 90 if (Idx == 0 && Imm.getBitWidth() <= 64) { 95 if (isInt<16>(Imm.getSExtValue())) 100 if (Idx == 1 && Imm 66 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) argument 184 getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty) argument [all...] |
H A D | SystemZTargetTransformInfo.h | 45 int getIntImmCost(const APInt &Imm, Type *Ty); 47 int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty); 48 int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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/external/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, argument 31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); 32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); 35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, argument 37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); 38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); 41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, argument 43 unsigned Shamt = countTrailingZeros(Imm); 44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); 48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigne argument 126 Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu) argument [all...] |
H A D | MipsISelDAGToDAG.h | 87 virtual bool selectVSplat(SDNode *N, APInt &Imm, 90 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; 92 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; 94 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; 96 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; 98 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; 100 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; 102 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; 104 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; 106 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons 122 getImm(const SDNode *Node, uint64_t Imm) argument [all...] |
H A D | MipsAnalyzeImmediate.h | 25 /// Analyze - Get an instruction sequence to load immediate Imm. The last 28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); 36 /// load immediate Imm 37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 40 /// load immediate Imm 41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 44 /// load immediate Imm 45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); 47 /// GetInstSeqLs - Get instruction sequences to load immediate Imm. 48 void GetInstSeqLs(uint64_t Imm, unsigne [all...] |
H A D | MipsSEISelDAGToDAG.h | 81 bool selectVSplat(SDNode *N, APInt &Imm, 84 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, 87 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override; 89 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override; 91 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override; 93 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override; 95 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override; 97 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override; 99 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override; 101 bool selectVSplatSimm5(SDValue N, SDValue &Imm) cons [all...] |
H A D | MipsISelDAGToDAG.cpp | 117 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, argument 123 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { 128 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { 133 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { 138 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { 143 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { 148 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { 153 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { 158 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { 163 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) cons [all...] |
H A D | MipsSEISelDAGToDAG.cpp | 478 // Returns true and sets Imm if: 481 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, argument 499 Imm = SplatValue; 507 // true and sets Imm if: 521 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, argument 534 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy); 544 selectVSplatUimm1(SDValue N, SDValue &Imm) const { 545 return selectVSplatCommon(N, Imm, false, 1); 549 selectVSplatUimm2(SDValue N, SDValue &Imm) const { 550 return selectVSplatCommon(N, Imm, fals 766 int64_t Imm = CN->getSExtValue(); local [all...] |
/external/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm(); 20 Target = Addr+Size+Imm;
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 113 return ShOp | (Imm << 3); 124 static inline unsigned getSOImmValImm(unsigned Imm) { 125 return Imm & 0xFF; 129 static inline unsigned getSOImmValRot(unsigned Imm) { 130 return (Imm >> 8) * 2; 133 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 137 static inline unsigned getSOImmValRotate(unsigned Imm) { argument 140 if ((Imm & ~255U) == 0) return 0; 143 unsigned TZ = countTrailingZeros(Imm); 218 getThumbImmValShift(unsigned Imm) argument 237 getThumbImm16ValShift(unsigned Imm) argument 271 unsigned u, Vs, Imm; local 335 isT2SOImmTwoPartVal(unsigned Imm) argument 362 getT2SOImmTwoPartFirst(unsigned Imm) argument 379 getT2SOImmTwoPartSecond(unsigned Imm) argument 628 getFPImmFloat(unsigned Imm) argument 656 getFP32Imm(const APInt &Imm) argument 684 getFP64Imm(const APInt &Imm) argument [all...] |
/external/llvm/lib/Target/X86/Utils/ |
H A D | X86ShuffleDecode.h | 31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 55 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 63 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 84 void DecodeBLENDMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask); 86 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm, [all...] |
H A D | X86ShuffleDecode.cpp | 25 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 33 unsigned ZMask = Imm & 15; 34 unsigned CountD = (Imm >> 4) & 3; 35 unsigned CountS = (Imm >> 6) & 3; 96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 105 if (i >= Imm) M = i - Imm + l; 110 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { argument 118 unsigned Base = i + Imm; 125 void DecodePALIGNRMask(MVT VT, unsigned Imm, argument 146 DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 163 DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 179 DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 208 DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 270 decodeVSHUF64x2FamilyMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument 287 DecodeVPERM2X128Mask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) argument [all...] |
/external/llvm/test/MC/Mips/ |
H A D | sym-expr.s | 11 jal __start + 0x4 # CHECK: instruction: [jal, Imm<__start+4>] 12 jal __start + (-0x10) # CHECK: instruction: [jal, Imm<__start-16>] 13 jal (__start + (-0x10)) # CHECK: instruction: [jal, Imm<__start-16>]
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonInstPrinter.cpp | 131 int64_t Imm; local 132 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); 133 Imm = SignExtend64<9>(Imm); 135 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO."); 136 O << formatImm(Imm/64); 141 int64_t Imm; local 142 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); 143 Imm = SignExtend64<10>(Imm); 151 int64_t Imm; local 161 int64_t Imm; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 38 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { argument 40 return BaseT::getIntImmCost(Imm, Ty); 48 if (Imm == 0) 51 if (Imm.getBitWidth() <= 64) { 52 if (isInt<16>(Imm.getSExtValue())) 55 if (isInt<32>(Imm.getSExtValue())) { 57 if ((Imm.getZExtValue() & 0xFFFF) == 0) 67 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, argument 70 return BaseT::getIntImmCost(IID, Idx, Imm, Ty); 85 if ((Idx == 1) && Imm 101 getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) argument [all...] |
/external/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 126 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { 127 if (!isUInt<N>(Imm)) 129 Inst.addOperand(MCOperand::createImm(Imm)); 134 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { 135 if (!isUInt<N>(Imm)) 137 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 141 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, 144 return decodeUImmOperand<4>(Inst, Imm); 147 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, 149 return decodeUImmOperand<1>(Inst, Imm); [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMCInstLower.cpp | 84 const ConstantFP *Imm = MO.getFPImm(); local 85 if (Imm->getType()->isFloatTy()) 86 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat()); 87 else if (Imm->getType()->isDoubleTy()) 88 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
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/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 83 uint16_t Imm = MI->getOperand(OpNo).getImm(); local 84 if (Imm != 0) { 232 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) { argument 233 int32_t SImm = static_cast<int32_t>(Imm); 239 if (Imm == FloatToBits(0.0f)) 241 else if (Imm == FloatToBits(1.0f)) 243 else if (Imm == FloatToBits(-1.0f)) 245 else if (Imm == FloatToBits(0.5f)) 247 else if (Imm == FloatToBits(-0.5f)) 249 else if (Imm 261 printImmediate64(uint64_t Imm, raw_ostream &O) argument 365 unsigned Imm = MI->getOperand(OpNum).getImm(); local 415 int Imm = MI->getOperand(OpNo).getImm(); local 426 int32_t Imm = MI->getOperand(OpNo).getImm(); local [all...] |
/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 95 int64_t Imm = MO.getImm(); local 99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) 103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) 107 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { 145 int64_t Imm = MO.getImm(); local 149 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) 152 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { 219 int Imm = (int) MO.getImm(); local 221 if (Imm) 224 switch (Imm) { [all...] |
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 89 static uint32_t getIntInlineImmEncoding(IntTy Imm) { argument 90 if (Imm >= 0 && Imm <= 64) 91 return 128 + Imm; 93 if (Imm >= -16 && Imm <= -1) 94 return 192 + std::abs(Imm); 212 int64_t Imm = 0; local 215 Imm = Op.getImm(); 220 OS.write((uint8_t) ((Imm >> ( [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | SIInstrInfo.h | 46 int64_t Imm) const;
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H A D | SIInstrInfo.cpp | 53 int64_t Imm) const 57 MachineInstrBuilder(MI).addImm(Imm);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 195 const MCOperand &Imm, int AlignSize) { 198 if (Imm.getExpr()->evaluateAsAbsolute(Value)) { 228 assert(Imm.isExpr() && "Expected expression and found none"); 252 OutStreamer.EmitValue(Imm.getExpr(), AlignSize); 271 const MCOperand &Imm = MappedInst.getOperand(1); local 274 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8); 292 MCOperand &Imm = MappedInst.getOperand(1); local 294 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4); 367 int64_t Imm; local 369 bool Success = Expr->evaluateAsAbsolute(Imm); 193 smallData(AsmPrinter &AP, const MachineInstr &MI, MCStreamer &OutStreamer, const MCOperand &Imm, int AlignSize) argument 392 int64_t Imm; local 425 int64_t Imm; local 469 int64_t Imm; local 522 MCOperand &Imm = MappedInst.getOperand(2); local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.h | 67 int getIntImmCost(const APInt &Imm, Type *Ty); 68 int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty); 69 int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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