| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmInstrumentation.cpp | 213 bool IsWrite,
217 bool IsWrite,
224 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
283 X86Operand &Op, unsigned AccessSize, bool IsWrite,
290 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
292 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
316 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
326 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
335 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
344 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCt
282 InstrumentMemOperand( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
415 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); local
598 EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out, const RegisterContext &RegCtx) argument
619 InstrumentMemOperandSmall( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
694 InstrumentMemOperandLarge( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
867 EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out, const RegisterContext &RegCtx) argument
890 InstrumentMemOperandSmall( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
966 InstrumentMemOperandLarge( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
[all...] |
| /external/compiler-rt/lib/tsan/tests/unit/ |
| H A D | tsan_shadow_test.cc | 28 EXPECT_EQ(s.IsWrite(), true);
|
| /external/llvm/lib/Transforms/Instrumentation/ |
| H A D | AddressSanitizer.cpp | 434 /// and set IsWrite/Alignment. Otherwise return nullptr.
435 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
441 Value *Addr, uint32_t TypeSize, bool IsWrite,
444 uint32_t TypeSize, bool IsWrite,
450 bool IsWrite, size_t AccessSizeIndex,
874 /// and set IsWrite/Alignment. Otherwise return nullptr.
876 bool *IsWrite,
886 *IsWrite = false;
892 *IsWrite = true;
898 *IsWrite
875 isInterestingMemoryAccess(Instruction *I, bool *IsWrite, uint64_t *TypeSize, unsigned *Alignment) argument
961 bool IsWrite = false; local
1017 generateCrashCode(Instruction *InsertBefore, Value *Addr, bool IsWrite, size_t AccessSizeIndex, Value *SizeArgument, uint32_t Exp) argument
1066 instrumentAddress(Instruction *OrigIns, Instruction *InsertBefore, Value *Addr, uint32_t TypeSize, bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) argument
1128 instrumentUnusualSizeOrAlignment( Instruction *I, Value *Addr, uint32_t TypeSize, bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) argument
1608 bool IsWrite; local
[all...] |
| H A D | ThreadSanitizer.cpp | 409 bool IsWrite = isa<StoreInst>(*I); local
410 Value *Addr = IsWrite
416 if (IsWrite && isVtableAccess(I)) {
434 if (!IsWrite && isVtableAccess(I)) {
440 const unsigned Alignment = IsWrite
447 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx];
449 OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx];
451 if (IsWrite) NumInstrumentedWrites++;
|
| /external/llvm/lib/Analysis/ |
| H A D | LoopAccessAnalysis.cpp | 561 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); local
562 MemAccessInfo Access(Ptr, IsWrite);
564 if (IsWrite)
587 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE);
702 bool IsWrite = AC.getInt(); local
706 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite;
711 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite ||
715 MemAccessInfo Access(Ptr, IsWrite);
722 // "a[b[i]] +="). Hence, we need the second check for "!IsWrite".
732 if ((IsWrite || IsReadOnlyPt
[all...] |
| /external/compiler-rt/lib/tsan/rtl/ |
| H A D | tsan_rtl.h | 200 DCHECK_EQ(kAccessIsWrite, IsWrite());
250 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } function in class:__tsan::Shadow
279 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic));
287 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite));
295 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite));
|
| H A D | tsan_rtl_report.cc | 166 mop->write = s.IsWrite();
|
| /external/pdfium/third_party/lcms2-2.6/src/ |
| H A D | cmsio0.c | 1020 NewIcc -> IsWrite = TRUE;
1048 NewIcc -> IsWrite = TRUE;
1082 NewIcc -> IsWrite = TRUE;
1398 if (Icc ->IsWrite) {
1400 Icc ->IsWrite = FALSE; // Assure no further writting
|
| H A D | lcms2_internal.h | 738 cmsBool IsWrite; member in struct:_cms_iccprofile_struct
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3235 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3236 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1793 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); local
1809 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
|