Searched refs:RegIndex (Results 1 - 10 of 10) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.cpp121 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); local
123 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
135 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); local
137 unsigned Address = calculateIndirectAddress(RegIndex, Channel);
144 calculateIndirectAddress(RegIndex, Channel),
286 unsigned RegIndex; local
288 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
289 ++RegIndex) {
290 if (IndirectRC->getRegister(RegIndex)
[all...]
H A DAMDGPUInstrInfo.h157 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and
162 /// address in this virtual address space that maps to the given \p RegIndex
164 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
H A DR600InstrInfo.h217 unsigned calculateIndirectAddress(unsigned RegIndex,
H A DSIInstrInfo.h422 unsigned calculateIndirectAddress(unsigned RegIndex,
H A DR600InstrInfo.cpp1094 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, argument
1098 return RegIndex;
H A DR600ISelLowering.cpp619 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); local
620 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
653 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); local
654 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
H A DSIInstrInfo.cpp2613 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2616 return RegIndex;
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ISelLowering.cpp99 int64_t RegIndex = MI->getOperand(1).getImm(); local
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); local
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); local
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
/external/llvm/lib/CodeGen/
H A DRegisterCoalescer.cpp1114 SlotIndex RegIndex = Idx.getRegSlot(); local
1117 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex);
1126 VNInfo *SVNI = SR.getVNInfoAt(RegIndex);
1127 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex));
1132 LIS->removeVRegDefAt(DstLI, RegIndex);
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp546 /// Warn if RegIndex is the same as the current AT.
547 void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
3676 void MipsAsmParser::warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc) { argument
3677 if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex)
3678 Warning(Loc, "used $at (currently $" + Twine(RegIndex) +

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