Searched refs:RegSeq (Results 1 - 2 of 2) sorted by relevance
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1029 SDValue RegSeq = createQTuple(Regs); local 1034 Ops.push_back(RegSeq); 1195 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); local 1197 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)}; 1213 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); local 1215 SDValue Ops[] = {RegSeq, 1272 SDValue RegSeq = createQTuple(Regs); local 1279 SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64), 1284 EVT WideVT = RegSeq.getOperand(1)->getValueType(0); 1312 SDValue RegSeq local 1368 SDValue RegSeq = createQTuple(Regs); local 1398 SDValue RegSeq = createQTuple(Regs); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 2053 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0); local 2057 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; 2074 Ops.push_back(RegSeq); 2294 SDValue RegSeq; local 2298 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); 2306 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); 2312 Ops.push_back(RegSeq); 3337 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0); local 3340 Ops.push_back(RegSeq);
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