/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 505 ARM_AM::ShiftOpc ShiftTy; member in struct:__anon12106::ARMOperand::PostIdxRegOp 515 ARM_AM::ShiftOpc ShiftTy; member in struct:__anon12106::ARMOperand::RegShiftedRegOp 522 ARM_AM::ShiftOpc ShiftTy; member in struct:__anon12106::ARMOperand::RegShiftedImmOp 1042 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 1163 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 1732 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1743 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 2316 PostIdxReg.ShiftTy); 2546 Op->RegShiftedReg.ShiftTy = ShTy; 2559 Op->RegShiftedImm.ShiftTy 2706 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument 2979 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) local 4527 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; local 7946 ARM_AM::ShiftOpc ShiftTy; local 7971 ARM_AM::ShiftOpc ShiftTy; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 1715 EVT ShiftTy = DCI.isBeforeLegalize() local 1724 ShiftTy))); 1733 ShiftTy))); 1750 EVT ShiftTy = DCI.isBeforeLegalize() local 1756 ShiftTy)); 1782 EVT ShiftTy = DCI.isBeforeLegalize() local 1787 DAG.getConstant(ShiftBits, dl, ShiftTy));
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H A D | LegalizeIntegerTypes.cpp | 2272 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); local 2273 assert(ShiftTy.getScalarType().getSizeInBits() >= 2276 if (ShiftOp.getValueType() != ShiftTy) 2277 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
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H A D | SelectionDAGBuilder.cpp | 2341 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( 2345 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2346 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2352 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2359 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 797 EVT ShiftTy, SelectionDAG &DAG) { 812 DAG.getConstant(Log2_64(C), DL, ShiftTy)); 822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); 823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); 829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); 830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); 796 genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 163 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 2753 ARM_AM::ShiftOpc ShiftTy) { 2796 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); 2799 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); 2752 SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy) argument
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | [all...] |