Searched refs:fcvtxn (Results 1 - 12 of 12) sorted by relevance
| /external/llvm/test/MC/AArch64/ |
| H A D | neon-scalar-cvt.s | 82 fcvtxn s22, d13
84 // CHECK: fcvtxn s22, d13 // encoding: [0xb6,0x69,0x61,0x7e]
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| H A D | neon-simd-misc.s | 438 fcvtxn v4.2s, v0.2d
441 // CHECK: fcvtxn v4.2s, v0.2d // encoding: [0x04,0x68,0x61,0x2e]
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| H A D | neon-diagnostics.s | 5820 fcvtxn v6.4s, v8.2d
5824 // CHECK-ERROR: fcvtxn v6.4s, v8.2d
7166 fcvtxn s0, s1
7169 // CHECK-ERROR: fcvtxn s0, s1
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| H A D | arm64-advsimd.s | 866 fcvtxn v6.2s, v9.2d
873 ; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e]
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| /external/vixl/src/vixl/a64/ |
| H A D | simulator-a64.h | 2353 LogicVRegister fcvtxn(VectorFormat vform,
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| H A D | simulator-a64.cc | 2503 fcvtxn(vf_fcvtn, rd, rn);
3451 // Unlike all of the other FP instructions above, fcvtxn encodes dest
3454 fcvtxn(kFormatS, rd, rn);
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| H A D | assembler-a64.h | 2186 void fcvtxn(const VRegister& vd, const VRegister& vn);
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| H A D | macro-assembler-a64.h | 1214 fcvtxn(vd, vn);
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| H A D | assembler-a64.cc | 2838 void Assembler::fcvtxn(const VRegister& vd,
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| H A D | logic-a64.cc | 4500 LogicVRegister Simulator::fcvtxn(VectorFormat vform, function in class:vixl::Simulator
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| /external/vixl/test/ |
| H A D | test-simulator-a64.cc | 3977 DEFINE_TEST_NEON_2DIFF_FP_NARROW_2S(fcvtxn, Conversions)
4024 CALL_TEST_NEON_HELPER_2DIFF(fcvtxn, S, D, kInputDoubleConversions);
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| /external/valgrind/none/tests/arm64/ |
| H A D | fp_and_simd.stdout.exp | 26838 fcvtxn s10, d21 6703e8d6cbffa3e96e2088fe0c404ef3 acdc6e6f4bf5a9501d87ee7e4d861e1c 00000000000000000000000000000000 acdc6e6f4bf5a9501d87ee7e4d861e1c fpsr=00000000
26839 fcvtxn v10.2s, v21.2d d2dcb2a585e4bade8d3a11f81ddbd8a4 3b2152911c72e8d11d9fc6b5613bb6b1 0000000000000000190a948900000000 3b2152911c72e8d11d9fc6b5613bb6b1 fpsr=00000000
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