| /external/ltrace/sysdeps/linux-gnu/arm/ |
| H A D | trace.c | 445 const unsigned imm2 = BITS(inst2, 0, 10); local
450 = ((imm1 << 12) + (imm2 << 1));
477 const unsigned imm2 = BITS(inst2, 0, 10); local
483 offset += (imm1 << 12) + (imm2 << 1);
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| /external/v8/src/arm64/ |
| H A D | assembler-arm64-inl.h | 1186 Instr Assembler::ImmBarrierDomain(int imm2) { argument
1187 DCHECK(is_uint2(imm2));
1188 return imm2 << ImmBarrierDomain_offset;
1192 Instr Assembler::ImmBarrierType(int imm2) { argument
1193 DCHECK(is_uint2(imm2));
1194 return imm2 << ImmBarrierType_offset;
|
| H A D | assembler-arm64.h | 1745 inline static Instr ImmBarrierDomain(int imm2);
1746 inline static Instr ImmBarrierType(int imm2);
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| /external/valgrind/none/tests/ppc32/ |
| H A D | test_dfp5.c | 239 typedef void (*test_funcp_t)(unsigned int imm, unsigned int imm2, dfp_val_t *valB);
|
| /external/valgrind/none/tests/ppc64/ |
| H A D | test_dfp5.c | 239 typedef void (*test_funcp_t)(unsigned int imm, unsigned int imm2, dfp_val_t *valB);
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| /external/vixl/src/vixl/a64/ |
| H A D | assembler-a64.h | 4027 static Instr ImmBarrierDomain(int imm2) {
4028 VIXL_ASSERT(is_uint2(imm2));
4029 return imm2 << ImmBarrierDomain_offset;
4032 static Instr ImmBarrierType(int imm2) {
4033 VIXL_ASSERT(is_uint2(imm2));
4034 return imm2 << ImmBarrierType_offset;
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| /external/vixl/test/ |
| H A D | test-simulator-a64.cc | 175 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2405 for (unsigned imm2 = 0; imm2 < inputs_imm2_length; imm2++) {
2415 (imm2 * vd_lane_count) + lane;
2437 (imm2 * vd_lane_count) + lane;
2441 unsigned input_index_imm2 = imm2;
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| /external/pcre/dist/sljit/ |
| H A D | sljitNativeARM_32.c | 1182 sljit_uw imm2; local
1225 imm2 = SRC2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8);
1248 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8);
1278 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8);
1284 FAIL_IF(push_inst(compiler, EMIT_DATA_PROCESS_INS(positive ? ORR_DP : BIC_DP, 0, reg, reg, imm2)));
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1793 MCOperand imm2(MCOperand::createExpr(
1795 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| H A D | nv50_ir_peephole.cpp | 552 const int s, ImmediateValue& imm2)
558 float f = imm2.reg.data.f32;
574 // d = mul a, imm2 -> d = mul r, (imm1 * imm2)
551 tryCollapseChainedMULs(Instruction *mul2, const int s, ImmediateValue& imm2) argument
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| /external/valgrind/VEX/priv/ |
| H A D | host_ppc_defs.c | 3138 UInt imm1, UInt imm2, UInt opc2,
3146 vassert(imm2 < 0x40);
3148 imm2 = ((imm2 & 0x1F) << 1) | (imm2 >> 5);
3150 ((imm1 & 0x1F)<<11) | (imm2<<5) |
3137 mkFormMD( UChar* p, UInt opc1, UInt r1, UInt r2, UInt imm1, UInt imm2, UInt opc2, VexEndness endness_host ) argument
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| H A D | guest_arm_toIR.c | 20277 /* ------------- LD/ST reg+(reg<<imm2) ------------- */
20316 UInt imm2 = INSN1(5,4); local
20353 binop(Iop_Shl32, getIRegT(rM), mkU8(imm2)) ));
20423 nm, rT, rN, rM, imm2);
21611 UInt imm2 = INSN1(5,4); local
21613 DIP("pld%s [r%u, r%u, lsl %u]\n", bW ? "w" : "", rN, rM, imm2);
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 175 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
173 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument
|