Searched refs:ld4r (Results 1 - 10 of 10) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-one-elem.s63 ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
64 ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
65 ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
66 ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
67 ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
68 ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
69 ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
70 ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
71 // CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0xe0,0x60,0x4d]
72 // CHECK: ld4r { v1
[all...]
H A Darm64-simd-ldst.s1012 ld4r: label
1013 ld4r.8b {v4, v5, v6, v7}, [x2]
1014 ld4r.8b {v4, v5, v6, v7}, [x2], x3
1015 ld4r.16b {v4, v5, v6, v7}, [x2]
1016 ld4r.16b {v4, v5, v6, v7}, [x2], x3
1017 ld4r.4h {v4, v5, v6, v7}, [x2]
1018 ld4r.4h {v4, v5, v6, v7}, [x2], x3
1019 ld4r.8h {v4, v5, v6, v7}, [x2]
1020 ld4r.8h {v4, v5, v6, v7}, [x2], x3
1021 ld4r
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H A Dneon-diagnostics.s4196 ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp]
4207 // CHECK-ERROR: ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp]
4255 ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], sp
4266 // CHECK-ERROR: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], sp
/external/valgrind/none/tests/arm64/
H A Dmemory.stdout.exp19355 ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5] with x5 = middle_of_block+3, x6=-5
19385 ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
19415 ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5] with x5 = middle_of_block+3, x6=-3
19445 ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
19475 ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5] with x5 = middle_of_block+3, x6=-5
19505 ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
19535 ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+3, x6=-3
19565 ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
[all...]
/external/vixl/src/vixl/a64/
H A Dsimulator-a64.h1379 void ld4r(VectorFormat vform,
H A Dassembler-a64.h2862 void ld4r(const VRegister& vt,
H A Dmacro-assembler-a64.h2640 ld4r(vt, vt2, vt3, vt4, src);
H A Dsimulator-a64.cc3197 ld4r(vf, vreg(rt), vreg(rt2), vreg(rt3), vreg(rt4), addr);
H A Dassembler-a64.cc2165 void Assembler::ld4r(const VRegister& vt,
H A Dlogic-a64.cc568 void Simulator::ld4r(VectorFormat vform, function in class:vixl::Simulator

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