/external/mesa3d/src/mesa/drivers/dri/i915/ |
H A D | intel_regions.c | 136 if (region->tiling != I915_TILING_NONE) 156 if (region->tiling != I915_TILING_NONE) 171 uint32_t tiling, drm_intel_bo *buffer) 185 region->tiling = tiling; 194 uint32_t tiling, 208 &tiling, &aligned_pitch, flags); 213 aligned_pitch / cpp, tiling, buffer); 247 uint32_t bit_6_swizzle, tiling; local 266 ret = drm_intel_bo_get_tiling(buffer, &tiling, 168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument 193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument 411 uint32_t tiling = region->tiling; local 444 uint32_t tiling = region->tiling; local [all...] |
H A D | intel_tex_copy.c | 108 if (intelImage->mt->region->tiling == I915_TILING_Y) { 127 region->tiling, 131 intelImage->mt->region->tiling,
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H A D | intel_clear.c | 126 * the tiling bits to determine how to clear. */ 135 if (stencilRegion->tiling == I915_TILING_Y || 155 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
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H A D | intel_tex_subimage.c | 66 /* The blitter can't handle Y tiling */ 67 if (intelImage->mt->region->tiling == I915_TILING_Y) 140 intelImage->mt->region->tiling,
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | intel_regions.c | 136 if (region->tiling != I915_TILING_NONE) 156 if (region->tiling != I915_TILING_NONE) 171 uint32_t tiling, drm_intel_bo *buffer) 185 region->tiling = tiling; 194 uint32_t tiling, 208 &tiling, &aligned_pitch, flags); 213 aligned_pitch / cpp, tiling, buffer); 247 uint32_t bit_6_swizzle, tiling; local 266 ret = drm_intel_bo_get_tiling(buffer, &tiling, 168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument 193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument 411 uint32_t tiling = region->tiling; local 444 uint32_t tiling = region->tiling; local [all...] |
H A D | intel_tex_copy.c | 108 if (intelImage->mt->region->tiling == I915_TILING_Y) { 127 region->tiling, 131 intelImage->mt->region->tiling,
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H A D | intel_tex_subimage.c | 66 /* The blitter can't handle Y tiling */ 67 if (intelImage->mt->region->tiling == I915_TILING_Y) 140 intelImage->mt->region->tiling,
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/external/mesa3d/src/mesa/drivers/dri/intel/ |
H A D | intel_regions.c | 136 if (region->tiling != I915_TILING_NONE) 156 if (region->tiling != I915_TILING_NONE) 171 uint32_t tiling, drm_intel_bo *buffer) 185 region->tiling = tiling; 194 uint32_t tiling, 208 &tiling, &aligned_pitch, flags); 213 aligned_pitch / cpp, tiling, buffer); 247 uint32_t bit_6_swizzle, tiling; local 266 ret = drm_intel_bo_get_tiling(buffer, &tiling, 168 intel_region_alloc_internal(struct intel_screen *screen, GLuint cpp, GLuint width, GLuint height, GLuint pitch, uint32_t tiling, drm_intel_bo *buffer) argument 193 intel_region_alloc(struct intel_screen *screen, uint32_t tiling, GLuint cpp, GLuint width, GLuint height, bool expect_accelerated_upload) argument 411 uint32_t tiling = region->tiling; local 444 uint32_t tiling = region->tiling; local [all...] |
H A D | intel_tex_copy.c | 108 if (intelImage->mt->region->tiling == I915_TILING_Y) { 127 region->tiling, 131 intelImage->mt->region->tiling,
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H A D | intel_regions.h | 70 uint32_t tiling; /**< Which tiling mode the region is in */ member in struct:intel_region 81 uint32_t tiling,
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/external/mesa3d/src/gallium/drivers/i915/ |
H A D | i915_screen.h | 50 boolean tiling; member in struct:i915_screen::__anon13541
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H A D | i915_winsys.h | 153 * the tiling mode provide in *tiling. If tiling is no possible, *tiling will 160 enum i915_winsys_buffer_tile *tiling, 172 enum i915_winsys_buffer_tile *tiling,
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H A D | i915_state_static.c | 79 buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling) argument 83 switch (tiling) { 110 buf_3d_tiling_bits(tex->tiling); 135 buf_3d_tiling_bits(tex->tiling); 219 if (is->is_i945 && tex->tiling != I915_TILE_NONE
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H A D | i915_resource.h | 69 /* tiling flags */ 70 enum i915_winsys_buffer_tile tiling; member in struct:i915_texture
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/external/drm_gralloc/ |
H A D | gralloc_drm_radeon.c | 81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling) argument 86 if (tiling & RADEON_TILING_MACRO) { 92 } else if (tiling & RADEON_TILING_MICRO) { 112 if (tiling) 122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling) argument 127 if (tiling & RADEON_TILING_MACRO) 129 else if (tiling & RADEON_TILING_MICRO) 135 if (tiling) 146 int bpe, uint32_t tiling) 148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling); 145 radeon_get_base_align(struct radeon_info *info, int bpe, uint32_t tiling) argument 191 uint32_t tiling, domain; local [all...] |
H A D | gralloc_drm_intel.c | 71 uint32_t tiling; member in struct:intel_buffer 243 uint32_t *tiling, unsigned long *stride) 275 *tiling = I915_TILING_X; 278 *tiling = I915_TILING_NONE; 287 bpp, tiling, stride, flags); 294 if (*tiling != I915_TILING_NONE) { 296 *tiling = I915_TILING_NONE; 309 *tiling = I915_TILING_NONE; 313 *tiling = I915_TILING_X; 315 *tiling 241 alloc_ibo(struct intel_info *info, const struct gralloc_drm_handle_t *handle, uint32_t *tiling, unsigned long *stride) argument [all...] |
/external/mesa3d/src/gallium/winsys/i915/sw/ |
H A D | i915_sw_buffer.c | 33 enum i915_winsys_buffer_tile *tiling, 44 buf->tiling = *tiling; 31 i915_sw_buffer_create_tiled(struct i915_winsys *iws, unsigned *stride, unsigned height, enum i915_winsys_buffer_tile *tiling, enum i915_winsys_buffer_type type) argument
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H A D | i915_sw_winsys.h | 46 enum i915_winsys_buffer_tile tiling; member in struct:i915_sw_buffer
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/external/libdrm/tegra/ |
H A D | tegra.h | 61 struct drm_tegra_bo_tiling *tiling); 63 const struct drm_tegra_bo_tiling *tiling);
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H A D | tegra.c | 341 struct drm_tegra_bo_tiling *tiling) 358 if (tiling) { 359 tiling->mode = args.mode; 360 tiling->value = args.value; 367 const struct drm_tegra_bo_tiling *tiling) 378 args.mode = tiling->mode; 379 args.value = tiling->value; 340 drm_tegra_bo_get_tiling(struct drm_tegra_bo *bo, struct drm_tegra_bo_tiling *tiling) argument 366 drm_tegra_bo_set_tiling(struct drm_tegra_bo *bo, const struct drm_tegra_bo_tiling *tiling) argument
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | radeon_mipmap_tree.h | 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target); 101 unsigned tiling);
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
H A D | radeon_mipmap_tree.h | 94 unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling, unsigned target); 101 unsigned tiling);
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/external/deqp/external/vulkancts/framework/vulkan/ |
H A D | vkQueryUtil.cpp | 110 VkImageFormatProperties getPhysicalDeviceImageFormatProperties (const InstanceInterface& vk, VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags) argument 116 VK_CHECK(vk.getPhysicalDeviceImageFormatProperties(physicalDevice, format, type, tiling, usage, flags, &properties)); 120 std::vector<VkSparseImageFormatProperties> getPhysicalDeviceSparseImageFormatProperties(const InstanceInterface& vk, VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling) argument 125 vk.getPhysicalDeviceSparseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, &numProp, DE_NULL); 130 vk.getPhysicalDeviceSparseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, &numProp, &properties[0]);
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H A D | vkInstanceDriverImpl.inl | 25 VkResult InstanceDriver::getPhysicalDeviceImageFormatProperties (VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, VkImageFormatProperties* pImageFormatProperties) const 27 return m_vk.getPhysicalDeviceImageFormatProperties(physicalDevice, format, type, tiling, usage, flags, pImageFormatProperties); 65 void InstanceDriver::getPhysicalDeviceSparseImageFormatProperties (VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling, deUint32* pPropertyCount, VkSparseImageFormatProperties* pProperties) const 67 m_vk.getPhysicalDeviceSparseImageFormatProperties(physicalDevice, format, type, samples, usage, tiling, pPropertyCount, pProperties);
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/external/mesa3d/src/gallium/winsys/i915/drm/ |
H A D | i915_drm_buffer.c | 58 enum i915_winsys_buffer_tile *tiling, 64 uint32_t tiling_mode = *tiling; 82 *tiling = tiling_mode; 94 enum i915_winsys_buffer_tile *tiling, 115 *tiling = tile; 56 i915_drm_buffer_create_tiled(struct i915_winsys *iws, unsigned *stride, unsigned height, enum i915_winsys_buffer_tile *tiling, enum i915_winsys_buffer_type type) argument 92 i915_drm_buffer_from_handle(struct i915_winsys *iws, struct winsys_handle *whandle, enum i915_winsys_buffer_tile *tiling, unsigned *stride) argument
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