Searched refs:virtReg (Results 1 - 4 of 4) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h92 bool hasPhys(unsigned virtReg) const {
93 return getPhys(virtReg) != NO_PHYS_REG;
98 unsigned getPhys(unsigned virtReg) const {
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 return Virt2PhysMap[virtReg];
105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) { argument
106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
108 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
111 Virt2PhysMap[virtReg] = physReg;
116 void clearVirt(unsigned virtReg) { argument
138 setIsSplitFromReg(unsigned virtReg, unsigned SReg) argument
[all...]
H A DLiveIntervalUnion.h155 LiveInterval &virtReg() const { function in class:llvm::LiveIntervalUnion::Query
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIAssignInterpRegs.cpp39 unsigned physReg, unsigned virtReg);
124 unsigned physReg, unsigned virtReg)
128 MRI.addLiveIn(physReg, virtReg);
131 TII->get(TargetOpcode::COPY), virtReg)
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
122 AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, unsigned physReg, unsigned virtReg) argument
/external/llvm/lib/CodeGen/
H A DVirtRegMap.cpp102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { argument
103 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
104 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
106 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
107 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { argument
111 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
112 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
117 Virt2StackSlotMap[virtReg] = SS;

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