/art/test/442-checker-constant-folding/src/ |
H A D | Main.java | 1341 long imm = $inline$long(33L); 1342 return (int) imm; 1358 float imm = $inline$float(1.0e34f); 1359 return (int) imm; 1375 double imm = $inline$double(Double.NaN); 1376 return (int) imm; 1392 int imm = $inline$int(33); 1393 return (long) imm; 1409 float imm = $inline$float(34.0f); 1410 return (long) imm; [all...] |
/art/compiler/utils/x86/ |
H A D | assembler_x86.h | 320 void pushl(const Immediate& imm); 330 void movl(const Address& dst, const Immediate& imm); 345 void rorl(Register reg, const Immediate& imm); 347 void roll(Register reg, const Immediate& imm); 356 void movb(const Address& dst, const Immediate& imm); 364 void movw(const Address& dst, const Immediate& imm); 432 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm); 433 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm); 482 void cmpw(const Address& address, const Immediate& imm); 484 void cmpl(Register reg, const Immediate& imm); [all...] |
H A D | assembler_x86.cc | 81 void X86Assembler::pushl(const Immediate& imm) { argument 83 if (imm.is_int8()) { 85 EmitUint8(imm.value() & 0xFF); 88 EmitImmediate(imm); 106 void X86Assembler::movl(Register dst, const Immediate& imm) { argument 109 EmitImmediate(imm); 134 void X86Assembler::movl(const Address& dst, const Immediate& imm) { argument 138 EmitImmediate(imm); 249 void X86Assembler::movb(const Address& dst, const Immediate& imm) { argument 253 CHECK(imm 303 movw(const Address& dst, const Immediate& imm) argument 773 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 784 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 1033 cmpw(const Address& address, const Immediate& imm) argument 1040 cmpl(Register reg, const Immediate& imm) argument 1081 cmpl(const Address& address, const Immediate& imm) argument 1140 andl(Register dst, const Immediate& imm) argument 1160 orl(Register dst, const Immediate& imm) argument 1180 xorl(Register dst, const Immediate& imm) argument 1186 addl(Register reg, const Immediate& imm) argument 1199 addl(const Address& address, const Immediate& imm) argument 1205 adcl(Register reg, const Immediate& imm) argument 1232 subl(Register reg, const Immediate& imm) argument 1273 imull(Register dst, Register src, const Immediate& imm) argument 1291 imull(Register reg, const Immediate& imm) argument 1339 sbbl(Register reg, const Immediate& imm) argument 1385 shll(Register reg, const Immediate& imm) argument 1395 shll(const Address& address, const Immediate& imm) argument 1405 shrl(Register reg, const Immediate& imm) argument 1415 shrl(const Address& address, const Immediate& imm) argument 1425 sarl(Register reg, const Immediate& imm) argument 1435 sarl(const Address& address, const Immediate& imm) argument 1454 shld(Register dst, Register src, const Immediate& imm) argument 1472 shrd(Register dst, Register src, const Immediate& imm) argument 1481 roll(Register reg, const Immediate& imm) argument 1491 rorl(Register reg, const Immediate& imm) argument 1515 enter(const Immediate& imm) argument 1537 ret(const Immediate& imm) argument 1744 AddImmediate(Register reg, const Immediate& imm) argument 1835 EmitImmediate(const Immediate& imm) argument 1896 EmitGenericShift(int reg_or_opcode, const Operand& operand, const Immediate& imm) argument 2040 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) argument 2045 StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, ManagedRegister) argument [all...] |
/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.h | 349 void pushq(const Immediate& imm); 365 void movq(const Address& dst, const Immediate& imm); 367 void movl(const Address& dst, const Immediate& imm); 379 void movb(const Address& dst, const Immediate& imm); 387 void movw(const Address& dst, const Immediate& imm); 459 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm); 460 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm); 509 void cmpw(const Address& address, const Immediate& imm); 511 void cmpl(CpuRegister reg, const Immediate& imm); 515 void cmpl(const Address& address, const Immediate& imm); [all...] |
H A D | assembler_x86_64.cc | 78 void X86_64Assembler::pushq(const Immediate& imm) { argument 80 CHECK(imm.is_int32()); // pushq only supports 32b immediate. 81 if (imm.is_int8()) { 83 EmitUint8(imm.value() & 0xFF); 86 EmitImmediate(imm); 106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { argument 108 if (imm.is_int32()) { 113 EmitInt32(static_cast<int32_t>(imm.value())); 117 EmitInt64(imm.value()); 122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { argument 131 movq(const Address& dst, const Immediate& imm) argument 189 movl(const Address& dst, const Immediate& imm) argument 292 movb(const Address& dst, const Immediate& imm) argument 352 movw(const Address& dst, const Immediate& imm) argument 929 roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 941 roundss(XmmRegister dst, XmmRegister src, const Immediate& imm) argument 1227 cmpw(const Address& address, const Immediate& imm) argument 1236 cmpl(CpuRegister reg, const Immediate& imm) argument 1268 cmpl(const Address& address, const Immediate& imm) argument 1284 cmpq(CpuRegister reg, const Immediate& imm) argument 1300 cmpq(const Address& address, const Immediate& imm) argument 1398 andl(CpuRegister dst, const Immediate& imm) argument 1405 andq(CpuRegister reg, const Immediate& imm) argument 1445 orl(CpuRegister dst, const Immediate& imm) argument 1452 orq(CpuRegister dst, const Immediate& imm) argument 1492 xorl(CpuRegister dst, const Immediate& imm) argument 1507 xorq(CpuRegister dst, const Immediate& imm) argument 1575 addl(CpuRegister reg, const Immediate& imm) argument 1582 addq(CpuRegister reg, const Immediate& imm) argument 1615 addl(const Address& address, const Immediate& imm) argument 1630 subl(CpuRegister reg, const Immediate& imm) argument 1637 subq(CpuRegister reg, const Immediate& imm) argument 1706 imull(CpuRegister dst, CpuRegister src, const Immediate& imm) argument 1728 imull(CpuRegister reg, const Immediate& imm) argument 1751 imulq(CpuRegister reg, const Immediate& imm) argument 1755 imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) argument 1825 shll(CpuRegister reg, const Immediate& imm) argument 1830 shlq(CpuRegister reg, const Immediate& imm) argument 1845 shrl(CpuRegister reg, const Immediate& imm) argument 1850 shrq(CpuRegister reg, const Immediate& imm) argument 1865 sarl(CpuRegister reg, const Immediate& imm) argument 1875 sarq(CpuRegister reg, const Immediate& imm) argument 1885 roll(CpuRegister reg, const Immediate& imm) argument 1895 rorl(CpuRegister reg, const Immediate& imm) argument 1905 rolq(CpuRegister reg, const Immediate& imm) argument 1915 rorq(CpuRegister reg, const Immediate& imm) argument 1957 enter(const Immediate& imm) argument 1979 ret(const Immediate& imm) argument 2162 AddImmediate(CpuRegister reg, const Immediate& imm) argument 2396 EmitImmediate(const Immediate& imm) argument 2461 EmitGenericShift(bool wide, int reg_or_opcode, CpuRegister reg, const Immediate& imm) argument 2791 StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister) argument 2796 StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister) argument [all...] |
/art/compiler/utils/ |
H A D | assembler_test.h | 154 for (int64_t imm : imms) { 155 ImmType new_imm = CreateImmediate(imm); 174 sreg << imm; local 206 for (int64_t imm : imms) { 207 ImmType new_imm = CreateImmediate(imm); 226 sreg << imm; local 253 for (int64_t imm : imms) { 254 ImmType new_imm = CreateImmediate(imm); 267 sreg << imm; local 400 for (int64_t imm 408 sreg << imm; local 805 sreg << imm; local 893 sreg << imm; local [all...] |
H A D | assembler.cc | 166 uint32_t imm ATTRIBUTE_UNUSED, 172 uint32_t imm ATTRIBUTE_UNUSED,
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H A D | assembler.h | 392 virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, 395 virtual void StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, 397 virtual void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm,
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/art/compiler/linker/arm/ |
H A D | relative_patcher_thumb2.cc | 72 uint32_t imm = (diff16 >> 11) & 0x1u; local 75 insn = (insn & 0xfbf08f00u) | (imm << 26) | (imm4 << 16) | (imm3 << 12) | imm8;
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/art/compiler/utils/arm64/ |
H A D | assembler_arm64.h | 127 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister scratch) OVERRIDE; 128 void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, ManagedRegister scratch)
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H A D | assembler_arm64.cc | 158 void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm, argument 162 LoadImmediate(scratch.AsXRegister(), imm); 167 void Arm64Assembler::StoreImmediateToThread64(ThreadOffset<8> offs, uint32_t imm, argument 171 LoadImmediate(scratch.AsXRegister(), imm);
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/art/compiler/optimizing/ |
H A D | code_generator_x86_64.cc | 3022 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue()); 3023 __ subl(first.AsRegister<CpuRegister>(), imm); 3125 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue()); 3126 __ imull(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>(), imm); 3283 int64_t imm = Int64FromConstant(second.GetConstant()); local 3285 DCHECK(imm == 1 || imm == -1); 3293 if (imm == -1) { 3305 if (imm == -1) { 3324 int64_t imm local 3387 int imm = second.GetConstant()->AsIntConstant()->GetValue(); local 3430 int64_t imm = second.GetConstant()->AsLongConstant()->GetValue(); local 3498 int64_t imm = Int64FromConstant(second.GetConstant()); local [all...] |
H A D | code_generator_mips64.cc | 1029 int64_t imm = CodeGenerator::GetInt64ValueOf(right->AsConstant()); local 1031 can_use_imm = IsUint<16>(imm); 1033 can_use_imm = IsInt<16>(imm); 1036 can_use_imm = IsInt<16>(-imm); 1856 int64_t imm = Int64FromConstant(second.GetConstant()); local 1857 DCHECK(imm == 1 || imm == -1); 1862 if (imm == -1) { 1885 int64_t imm = Int64FromConstant(second.GetConstant()); local 1886 uint64_t abs_imm = static_cast<uint64_t>(AbsOrMin(imm)); 1988 int64_t imm = Int64FromConstant(second.GetConstant()); local 2063 int64_t imm = Int64FromConstant(second.GetConstant()); local [all...] |
H A D | code_generator_mips.cc | 1146 int32_t imm = CodeGenerator::GetInt32ValueOf(right->AsConstant()); local 1148 can_use_imm = IsUint<16>(imm); 1150 can_use_imm = IsInt<16>(imm); 1153 can_use_imm = IsInt<16>(-imm); 2272 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 2273 DCHECK(imm == 1 || imm == -1); 2278 if (imm == -1) { 2296 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 2297 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm)); 2345 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 2395 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 2838 int64_t imm = 0; local [all...] |
H A D | code_generator_x86.cc | 2996 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue()); 2997 __ imull(out.AsRegister<Register>(), first.AsRegister<Register>(), imm); 3236 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local 3238 DCHECK(imm == 1 || imm == -1); 3244 if (imm == -1) { 3256 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local 3257 DCHECK(IsPowerOfTwo(AbsOrMin(imm))); 3258 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm)); 3265 int shift = CTZ(imm); 3279 int imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); local 3369 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 5720 __ movl(Address(ESP, destination.GetStackIndex()), imm); local [all...] |
H A D | code_generator_arm64.cc | 2526 int64_t imm = Int64FromConstant(second.GetConstant()); local 2527 DCHECK(imm == 1 || imm == -1); 2532 if (imm == 1) { 2549 int64_t imm = Int64FromConstant(second.GetConstant()); local 2550 uint64_t abs_imm = static_cast<uint64_t>(AbsOrMin(imm)); 2560 if (imm > 0) { 2584 int64_t imm = Int64FromConstant(second.GetConstant()); local 2591 CalculateMagicAndShiftForDivRem(imm, type == Primitive::kPrimLong /* is_long */, &magic, &shift); 2605 if (imm > 2636 int64_t imm = Int64FromConstant(second.GetConstant()); local [all...] |
H A D | code_generator_arm.cc | 2705 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 2706 DCHECK(imm == 1 || imm == -1); 2711 if (imm == 1) { 2730 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 2731 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm)); 2744 if (imm < 0) { 2765 int64_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local 2769 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift); 2774 if (imm > 2802 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue(); local [all...] |
/art/runtime/interpreter/mterp/mips/ |
H A D | header.S | 443 #define LOAD_IMM(dest, imm) li dest, imm
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/art/compiler/utils/arm/ |
H A D | assembler_arm.cc | 143 // RRX is encoded as an ROR with imm 0. 562 void ArmAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, 566 LoadImmediate(scratch.AsCoreRegister(), imm); 570 void ArmAssembler::StoreImmediateToThread32(ThreadOffset<4> dest, uint32_t imm, 574 LoadImmediate(scratch.AsCoreRegister(), imm);
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H A D | assembler_arm32_test.cc | 173 // ShifterOperands of form "reg shift-type imm." 181 for (uint32_t imm = 1; imm < 32; ++imm) { 182 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, imm));
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H A D | assembler_thumb2.cc | 1384 uint32_t imm = so.GetImmediate(); local 1386 uint32_t i = (imm >> 11) & 1; 1387 uint32_t imm3 = (imm >> 8) & 7U /* 0b111 */; 1388 uint32_t imm8 = imm & 0xff; 1400 uint32_t imm = ModifiedImmediate(so.encodingThumb()); local 1401 if (imm == kInvalidModifiedImmediate) { 1410 imm; 1672 // ADD sp, sp, #imm 1686 // ADD rd, SP, #imm 1732 // SUB sp, sp, #imm 2725 ldrex(Register rt, Register rn, uint16_t imm, Condition cond) argument 2745 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument [all...] |
/art/compiler/utils/mips/ |
H A D | assembler_mips.h | 432 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE; 435 uint32_t imm, 764 void EmitI(int opcode, Register rs, Register rt, uint16_t imm); 768 void EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm);
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H A D | assembler_mips.cc | 138 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument 144 imm; 177 void MipsAssembler::EmitFI(int opcode, int fmt, FRegister ft, uint16_t imm) { argument 182 imm; 2565 void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, argument 2569 LoadConst32(scratch.AsCoreRegister(), imm); 2573 void MipsAssembler::StoreImmediateToThread32(ThreadOffset<kMipsWordSize> dest, uint32_t imm, argument 2578 LoadConst32(scratch.AsCoreRegister(), imm);
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/art/compiler/utils/mips64/ |
H A D | assembler_mips64.h | 384 void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE; 678 void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm); 682 void EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm);
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/art/disassembler/ |
H A D | disassembler_arm.cc | 169 uint32_t imm = (instruction & 0xff); local 170 value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate))); 898 // |1110|1110|1|D|11| iH | Vd |101|S|0|0|0|0| iL | VMOV (imm) 1906 // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt 1907 // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt 1916 // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii 1917 // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii
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