/external/llvm/test/MC/Mips/msa/ |
H A D | set-msa-directive.s | 4 # CHECK: addvi.b $w14, $w12, 14 8 # CHECK: subvi.b $w14, $w12, 14 14 addvi.b $w14, $w12, 14 19 subvi.b $w14, $w12, 14
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H A D | set-msa-directive-bad.s | 5 addvi.b $w14, $w12, 14 # CHECK: error: instruction requires a CPU feature not currently enabled
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H A D | test_i8.s | 11 # CHECK: shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82] 22 shf.w $w14, $w3, 93
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H A D | test_vec.s | 6 # CHECK: bsel.v $w8, $w0, $w14 # encoding: [0x78,0xce,0x02,0x1e] 14 bsel.v $w8, $w0, $w14
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H A D | test_3rf.s | 5 # CHECK: fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a] 10 # CHECK: fcle.d $w27, $w14, $w1 # encoding: [0x79,0xa1,0x76,0xda] 14 # CHECK: fcne.d $w14, $w20, $w15 # encoding: [0x78,0xef,0xa3,0x9c] 17 # CHECK: fcueq.w $w14, $w2, $w21 # encoding: [0x78,0xd5,0x13,0x9a] 56 # CHECK: fsne.d $w14, $w13, $w23 # encoding: [0x7a,0xf7,0x6b,0x9c] 62 # CHECK: fsueq.d $w18, $w14, $w14 # encoding: [0x7a,0xee,0x74,0x9a] 80 # CHECK: msubr_q.w $w1, $w14, $w20 # encoding: [0x7b,0xb4,0x70,0x5c] 88 fcaf.w $w14, $w11, $w25 93 fcle.d $w27, $w14, [all...] |
H A D | test_3r.s | 13 # CHECK: adds_s.w $w16, $w14, $w13 # encoding: [0x79,0x4d,0x74,0x10] 14 # CHECK: adds_s.d $w2, $w14, $w28 # encoding: [0x79,0x7c,0x70,0x90] 15 # CHECK: adds_u.b $w3, $w17, $w14 # encoding: [0x79,0x8e,0x88,0xd0] 21 # CHECK: addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce] 53 # CHECK: binsl.w $w14, $w15, $w13 # encoding: [0x7b,0x4d,0x7b,0x8d] 64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d] 69 # CHECK: ceq.w $w9, $w5, $w14 # encoding: [0x78,0x4e,0x2a,0x4f] 92 # CHECK: div_u.h $w24, $w21, $w14 # encoding: [0x7a,0xae,0xae,0x12] 93 # CHECK: div_u.w $w29, $w14, $w25 # encoding: [0x7a,0xd9,0x77,0x52] 96 # CHECK: dotp_s.w $w20, $w14, [all...] |
H A D | test_2rf.s | 22 # CHECK: frcp.d $w4, $w14 # encoding: [0x7b,0x2b,0x71,0x1e] 29 # CHECK: ftint_u.w $w20, $w14 # encoding: [0x7b,0x3a,0x75,0x1e] 55 frcp.d $w4, $w14 62 ftint_u.w $w20, $w14
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H A D | test_i5.s | 23 # CHECK: clti_u.b $w14, $w9, 29 # encoding: [0x79,0x9d,0x4b,0x87] 32 # CHECK: maxi_u.h $w1, $w14, 3 # encoding: [0x79,0xa3,0x70,0x46] 68 clti_u.b $w14, $w9, 29 77 maxi_u.h $w1, $w14, 3
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H A D | test_mi10.s | 20 # CHECK: ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3] 47 ld.d $w14, -4096($15)
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/external/llvm/test/MC/AArch64/ |
H A D | neon-simd-copy.s | 10 ins v7.h[7], w14 15 mov v7.h[7], w14 20 // CHECK: {{mov|ins}} v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] 25 // CHECK: {{mov|ins}} v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] 34 smov w14, v6.h[4] 40 // CHECK: smov w14, v6.h[4] // encoding: [0xce,0x2c,0x12,0x0e] 50 umov w14, v6.h[4] 58 // CHECK: {{mov|umov}} w14, v6.h[4] // encoding: [0xce,0x3c,0x12,0x0e] 112 dup v11.4h, w14 120 // CHECK: {{mov|dup}} v11.4h, w14 // encodin [all...] |
H A D | tls-relocs.s | 63 movn w14, #:dtprel_g0:var 71 // CHECK: movn w14, #:dtprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12] 178 movz w14, #:gottprel_g1:var 182 // CHECK: movz w14, #:gottprel_g1:var // encoding: [0bAAA01110,A,0b101AAAAA,0x12] 265 movn w14, #:tprel_g0:var 273 // CHECK: movn w14, #:tprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12]
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H A D | arm64-arithmetic-encoding.s | 106 add w12, w13, w14 108 add w12, w13, w14, lsl #12 113 ; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b] 115 ; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b] 120 sub w12, w13, w14 122 sub w12, w13, w14, lsl #12 127 ; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b] 129 ; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b] 134 adds w12, w13, w14 136 adds w12, w13, w14, ls [all...] |
H A D | arm64-leaf-compact-unwind.s | 145 ldr w14, [x8] 162 add w9, w9, w14
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/external/opencv3/3rdparty/openexr/IlmImf/ |
H A D | ImfWav.cpp | 152 bool w14 = (mx < (1 << 14)); local 194 if (w14) 218 if (w14) 240 if (w14) 272 bool w14 = (mx < (1 << 14)); local 325 if (w14) 349 if (w14) 371 if (w14)
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/external/libhevc/common/arm64/ |
H A D | ihevc_intra_pred_chroma_horz.s | 196 ldrb w14,[x12],#1 //pu1_ref[two_nt] 197 sxtw x14,w14 200 dup v28.8b,w14 278 ldrb w14,[x12] //pu1_ref[two_nt] 279 sxtw x14,w14 288 dup v28.8b,w14 326 ldrb w14,[x12] //pu1_ref[two_nt] 327 sxtw x14,w14 333 dup v28.8b,w14
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H A D | ihevc_intra_pred_luma_horz.s | 196 ldrb w14,[x12],#1 //pu1_ref[two_nt] 197 sxtw x14,w14 202 dup v28.8b,w14 277 ldrb w14,[x12] //pu1_ref[two_nt] 278 sxtw x14,w14 285 dup v28.8b,w14 323 ldrb w14,[x12] //pu1_ref[two_nt] 324 sxtw x14,w14 330 dup v28.8b,w14
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H A D | ihevc_sao_edge_offset_class0.s | 158 LDRB w14,[x6,x5] //pu1_src_org[(ht - row) * src_strd + 16 - 1 + (wd - col)] 166 STRB w14,[x2],#1 //pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)] 191 LDRB w14,[x6,x5] //II pu1_src_org[(ht - row) * src_strd + 16 - 1 + (wd - col)] 196 STRB w14,[x2],#1 //II pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)] 329 LDRB w14,[x6, x11] //pu1_src_org[(ht - row) * src_strd + (wd - 1)] 330 STRB w14,[x2],#1 //pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)]
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H A D | ihevc_intra_pred_filters_luma_mode_19_to_25.s | 265 umov w14, v5.s[0] //(i row)extract idx to the r register 266 sxtw x14,w14 311 umov w14, v5.s[1] //extract idx to the r register 312 sxtw x14,w14 388 umov w14, v3.s[0] //(i)extract idx to the r register 389 sxtw x14,w14 430 umov w14, v3.s[1] //extract idx to the r register 431 sxtw x14,w14 501 umov w14, v3.s[0] //(i)extract idx to the r register 502 sxtw x14,w14 [all...] |
H A D | ihevc_intra_pred_luma_mode_27_to_33.s | 153 umov w14, v5.s[0] //(i row)extract idx to the r register 154 sxtw x14,w14 202 umov w14, v5.s[1] //extract idx to the r register 203 sxtw x14,w14 282 umov w14, v3.s[0] //(i)extract idx to the r register 283 sxtw x14,w14 322 umov w14, v3.s[1] //extract idx to the r register 323 sxtw x14,w14 393 umov w14, v3.s[0] //(i)extract idx to the r register 394 sxtw x14,w14 [all...] |
H A D | ihevc_sao_edge_offset_class0_chroma.s | 187 LDRH w14,[x6,x5] //pu1_src_org[(ht - row) * src_strd + 14 + (wd - col)] 199 STRH w14,[x2],#2 //pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)] 288 LDRH w14,[x6,x5] //II pu1_src_org[(ht - row) * src_strd + 14 + (wd - col)] 291 STRH w14,[x2],#2 //II pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)] 380 LDRH w14,[x6, x5] //pu1_src_org[(ht - row) * 2* src_strd + (wd - 2)] 386 STRH w14,[x2],#2 //pu1_src_left[(ht - row) * 2] = au1_src_left_tmp[(ht - row) * 2] 453 LDRH w14,[x6, x5] //II pu1_src_org[(ht - row) * 2* src_strd + (wd - 2)] 460 STRH w14,[x2],#2 //II pu1_src_left[(ht - row) * 2] = au1_src_left_tmp[(ht - row) * 2]
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/external/boringssl/linux-aarch64/crypto/sha/ |
H A D | sha1-armv8.S | 176 add w23,w23,w14 // future e+=X[i] 261 eor w6,w6,w14 334 eor w12,w12,w14 358 eor w14,w14,w16 362 eor w14,w14,w6 366 eor w14,w14,w11 369 ror w14,w1 [all...] |
H A D | sha256-armv8.S | 241 eor w14,w24,w24,ror#14 247 eor w16,w16,w14,ror#11 // Sigma1(e) 248 ror w14,w20,#2 255 eor w17,w14,w17,ror#13 // Sigma0(a) 262 ldp w13,w14,[x1],#2*4 309 rev w14,w14 // 11 319 add w24,w24,w14 // h+=X[i] 502 add w5,w5,w14 541 str w14,[s [all...] |
/external/libmpeg2/common/armv8/ |
H A D | impeg2_format_conv.s | 136 ldr w14, [sp, #112] //// Load convert_uv_only 138 cmp w14, #1 308 ldr w14, [sp, #112] //// Load convert_uv_only 310 cmp w14, #1
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/external/llvm/test/MC/Mips/mips32r2/ |
H A D | invalid-msa.s | 12 fclass.d $w14,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 19 ffint_s.w $w16,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 40 ftint_s.w $w27,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 53 nlzc.d $w14,$w14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/v8/test/cctest/ |
H A D | test-disasm-arm64.cc | 156 COMPARE(Mov(w14, Operand(w15, SXTH, 2)), "sbfiz w14, w15, #2, #16"); 198 COMPARE(movn(w14, 0x1234), "movn w14, #0x1234"); 284 COMPARE(adds(w14, w15, Operand(0xff)), "adds w14, w15, #0xff (255)"); 314 COMPARE(subs(w14, w15, Operand(0xff)), "subs w14, w15, #0xff (255)"); 337 COMPARE(add(w12, w13, Operand(w14, LSR, 3)), "add w12, w13, w14, ls [all...] |