1200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung%default {"preinstr":"", "result":"a0", "chkzero":"0"} 2200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 3200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * Generic 32-bit binary operation. Provide an "instr" line that 4200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * specifies an instruction that performs "result = a0 op a1". 5200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * This could be a MIPS instruction or a function call. (If the result 6200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * comes back in a register other than a0, you can override "result".) 7200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 8200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * If "chkzero" is set to 1, we perform a divide-by-zero check on 9200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * vCC (a1). Useful for integer division and modulus. Note that we 10f1e74af7c84e0bdb37a8fc901852dfca125fc8ddRoland Levillain * *don't* check for (INT_MIN / -1) here, because the CPU handles it 11f1e74af7c84e0bdb37a8fc901852dfca125fc8ddRoland Levillain * correctly. 12200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * 13200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 14200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung * xor-int, shl-int, shr-int, ushr-int 15200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung */ 16200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* binop vAA, vBB, vCC */ 17200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH(a0, 1) # a0 <- CCBB 18200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_OPA(rOBJ) # rOBJ <- AA 19200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung srl a3, a0, 8 # a3 <- CC 20200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung and a2, a0, 255 # a2 <- BB 21200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a1, a3) # a1 <- vCC 22200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_VREG(a0, a2) # a0 <- vBB 23200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .if $chkzero 24200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung # is second operand zero? 25200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung beqz a1, common_errDivideByZero 26200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung .endif 27200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung 28200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung FETCH_ADVANCE_INST(2) # advance rPC, load rINST 29200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung $preinstr # optional op 30200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung $instr # $result <- op, a0-a3 changed 31200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung GET_INST_OPCODE(t0) # extract opcode from rINST 32200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung SET_VREG_GOTO($result, rOBJ, t0) # vAA <- $result 33200f040af3e4fe9e178cb63c90860d58d90ef665Douglas Leung /* 11-14 instructions */ 34