1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/**************************************************************************** 2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** This header was automatically generated from a Linux kernel header 5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** of the same name, to make information necessary for userspace to 6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** call into the kernel available to libc. It contains only constants, 7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** structures, and macros generated from the original header, and thus, 8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** contains no copyrightable information. 9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** To edit the content of this header, modify the corresponding 11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** source file (e.g. under external/kernel-headers/original/) then 12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** run bionic/libc/kernel/tools/update_all.py 13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** Any manual change here will be lost the next time this script will 15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** be run. You've been warned! 16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/ 19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef LINUX_PCI_REGS_H 20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define LINUX_PCI_REGS_H 21655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STD_HEADER_SIZEOF 64 22655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VENDOR_ID 0x00 23655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DEVICE_ID 0x02 25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND 0x04 26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_IO 0x1 27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MEMORY 0x2 28655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MASTER 0x4 30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SPECIAL 0x8 31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INVALIDATE 0x10 32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_VGA_PALETTE 0x20 33655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_PARITY 0x40 35655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_WAIT 0x80 36655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SERR 0x100 37655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_FAST_BACK 0x200 38655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INTX_DISABLE 0x400 40655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS 0x06 41655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_INTERRUPT 0x08 42655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_CAP_LIST 0x10 43655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_66MHZ 0x20 45655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_UDF 0x40 46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_FAST_BACK 0x80 47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_PARITY 0x100 48655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MASK 0x600 50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_FAST 0x000 51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MEDIUM 0x200 52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_SLOW 0x400 53655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_TARGET_ABORT 0x800 55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_TARGET_ABORT 0x1000 56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_MASTER_ABORT 0x2000 57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 58655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DETECTED_PARITY 0x8000 60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_REVISION 0x08 61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REVISION_ID 0x08 62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_PROG 0x09 63655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_DEVICE 0x0a 65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CACHE_LINE_SIZE 0x0c 66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LATENCY_TIMER 0x0d 67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE 0x0e 68655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_NORMAL 0 70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_BRIDGE 1 71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_CARDBUS 2 72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST 0x0f 73655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CODE_MASK 0x0f 75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_START 0x40 76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CAPABLE 0x80 77655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_0 0x10 78655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_1 0x14 80655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_2 0x18 81655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_3 0x1c 82655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_4 0x20 83655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_5 0x24 85655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE 0x01 86655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_IO 0x01 87655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 88655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 91655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 93655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 95655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 96655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 97655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CARDBUS_CIS 0x28 98655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 100655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_ID 0x2e 101655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS 0x30 102655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_ENABLE 0x01 103655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAPABILITY_LIST 0x34 106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_LINE 0x3c 107655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_PIN 0x3d 108655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MIN_GNT 0x3e 110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MAX_LAT 0x3f 111655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRIMARY_BUS 0x18 112655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SECONDARY_BUS 0x19 113655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBORDINATE_BUS 0x1a 115655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_LATENCY_TIMER 0x1b 116655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE 0x1c 117655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT 0x1d 118655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 120655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_16 0x00 121655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_32 0x01 122655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_MASK (~0x0fUL) 123655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_1K_RANGE_MASK (~0x03UL) 125655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_STATUS 0x1e 126655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_BASE 0x20 127655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_LIMIT 0x22 128655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 130655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 131655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_BASE 0x24 132655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_LIMIT 0x26 133655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 135655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_32 0x00 136655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_64 0x01 137655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_MASK (~0x0fUL) 138655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_BASE_UPPER32 0x28 140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_LIMIT_UPPER32 0x2c 141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE_UPPER16 0x30 142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT_UPPER16 0x32 143655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS1 0x38 145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CONTROL 0x3e 146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_PARITY 0x01 147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_SERR 0x02 148655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_ISA 0x04 150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_VGA 0x08 151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 152655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_BUS_RESET 0x40 153655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_FAST_BACK 0x80 155655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CAPABILITY_LIST 0x14 156655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SEC_STATUS 0x16 157655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_PRIMARY_BUS 0x18 158655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CARD_BUS 0x19 160655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBORDINATE_BUS 0x1a 161655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LATENCY_TIMER 0x1b 162655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_0 0x1c 163655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_0 0x20 165655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_1 0x24 166655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_1 0x28 167655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0 0x2c 168655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0_HI 0x2e 170655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0 0x30 171655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0_HI 0x32 172655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1 0x34 173655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1_HI 0x36 175655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1 0x38 176655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1_HI 0x3a 177655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_RANGE_MASK (~0x03UL) 178655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CONTROL 0x3e 180655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PARITY 0x01 181655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_SERR 0x02 182655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_ISA 0x04 183655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_VGA 0x08 185655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 186655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 187655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 188655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 190655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 191655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 192655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 193655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_ID 0x42 195655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LEGACY_MODE_BASE 0x44 196655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_LIST_ID 0 197655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PM 0x01 198655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP 0x02 200655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VPD 0x03 201655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SLOTID 0x04 202655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSI 0x05 203655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CHSWP 0x06 205655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PCIX 0x07 206655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_HT 0x08 207655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VNDR 0x09 208655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_DBG 0x0A 210655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CCRC 0x0B 211655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SHPC 0x0C 212655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SSVID 0x0D 213655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP3 0x0E 215655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SECDEV 0x0F 216655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_EXP 0x10 217655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSIX 0x11 218655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SATA 0x12 220655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AF 0x13 22105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_ID_EA 0x14 22205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_ID_MAX PCI_CAP_ID_EA 223655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 22405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CAP_LIST_NEXT 1 225655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_FLAGS 2 226655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_SIZEOF 4 227655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PMC 2 228655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 22905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_VER_MASK 0x0007 230655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_CLOCK 0x0008 231655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_RESERVED 0x0010 232655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_DSI 0x0020 233655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 23405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_AUX_POWER 0x01C0 235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D1 0x0200 236655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D2 0x0400 237655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME 0x0800 238655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 23905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_PME_MASK 0xF800 240655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D0 0x0800 241655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D1 0x1000 242655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D2 0x2000 243655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CAP_PME_D3 0x4000 245655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D3cold 0x8000 246655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_SHIFT 11 247655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL 4 248655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CTRL_STATE_MASK 0x0003 250655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 251655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_ENABLE 0x0100 252655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 253655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 25405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 255655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_STATUS 0x8000 256655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_EXTENSIONS 6 257655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_B2_B3 0x40 258655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 25905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_PM_BPCC_ENABLE 0x80 260655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_DATA_REGISTER 7 261655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_SIZEOF 8 262655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_VERSION 2 263655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 26405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_RFU 3 265655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS 4 266655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RQ_MASK 0xff000000 267655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_SBA 0x0200 268655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 26905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_STATUS_64BIT 0x0020 270655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_FW 0x0010 271655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE4 0x0004 272655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE2 0x0002 273655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 27405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_STATUS_RATE1 0x0001 275655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND 8 276655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 277655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_SBA 0x0200 278655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 27905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_COMMAND_AGP 0x0100 280655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_64BIT 0x0020 281655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_FW 0x0010 282655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE4 0x0004 283655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 28405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AGP_COMMAND_RATE2 0x0002 285655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE1 0x0001 286655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_SIZEOF 12 287655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR 2 288655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 28905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_VPD_ADDR_MASK 0x7fff 290655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR_F 0x8000 291655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_DATA 4 292655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VPD_SIZEOF 8 293655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_SID_ESR 2 295655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_NSLOTS 0x1f 296655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_FIC 0x20 297655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_CHASSIS_NR 3 298655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_FLAGS 2 300655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_ENABLE 0x0001 301655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QMASK 0x000e 302655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QSIZE 0x0070 303655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 30405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_FLAGS_64BIT 0x0080 305655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_MASKBIT 0x0100 306655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_RFU 3 307655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_ADDRESS_LO 4 308655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 30905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_ADDRESS_HI 8 310655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_DATA_32 8 311655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_32 12 312655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_32 16 313655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 31405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSI_DATA_64 12 315655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_64 16 316655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_64 20 317655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS 2 318655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 31905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_FLAGS_QSIZE 0x07FF 320655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_MASKALL 0x4000 321655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_ENABLE 0x8000 322655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE 4 323655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 32405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_TABLE_BIR 0x00000007 325655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 326655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA 8 327655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA_BIR 0x00000007 328655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 32905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_PBA_OFFSET 0xfffffff8 330915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR 331655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_MSIX_SIZEOF 12 332655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_SIZE 16 33338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 33405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_ENTRY_LOWER_ADDR 0 335915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_MSIX_ENTRY_UPPER_ADDR 4 336655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_DATA 8 337655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 33838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 33905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 340915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CHSWP_CSR 2 341655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_DHA 0x01 342655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EIM 0x02 34338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CHSWP_PIE 0x04 345915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CHSWP_LOO 0x08 346655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_PI 0x30 347655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EXT 0x40 34838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_CHSWP_INS 0x80 350915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_AF_LENGTH 2 351655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP 3 352655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP_TP 0x01 35338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 35405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AF_CAP_FLR 0x02 355915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_AF_CTRL 4 356655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CTRL_FLR 0x01 357655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_STATUS 5 35838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 35905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_AF_STATUS_TP 0x01 360915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_AF_SIZEOF 6 36105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_NUM_ENT 2 36205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_NUM_ENT_MASK 0x3f 36305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIRST_ENT 4 36505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIRST_ENT_BRIDGE 8 36605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_ES 0x00000007 36705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI 0x000000f0 36805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 36905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BAR0 0 37005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BAR5 5 37105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_BRIDGE 6 37205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_ENI 7 37305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_ROM 8 37505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_VF_BAR0 9 37605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_VF_BAR5 14 37705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BEI_RESERVED 15 37805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 37905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_PP 0x0000ff00 38005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_SP 0x00ff0000 38105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM 0x00 38205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM_PREFETCH 0x01 38305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_IO 0x02 38505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_VF_MEM_PREFETCH 0x03 38605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_VF_MEM 0x04 38705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_MEM 0x05 38805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 38905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 39005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_BRIDGE_IO 0x07 39105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_MEM_RESERVED 0xfd 39205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_IO_RESERVED 0xfe 39305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_P_UNAVAILABLE 0xff 39505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_WRITABLE 0x40000000 39605d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_ENABLE 0x80000000 39705d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_BASE 4 39805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39905d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_MAX_OFFSET 8 40005d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_IS_64 0x00000002 40105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EA_FIELD_MASK 0xfffffffc 402655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD 2 40305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_DPERR_E 0x0001 405655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_ERO 0x0002 406915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_READ_512 0x0000 407655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_1K 0x0004 40805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_2K 0x0008 410655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_4K 0x000c 411915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_MAX_READ 0x000c 412655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_1 0x0000 41305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_2 0x0010 415655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_3 0x0020 416915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_SPLIT_4 0x0030 417655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_8 0x0040 41805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_12 0x0050 420655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_16 0x0060 421915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_CMD_SPLIT_32 0x0070 422655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_MAX_SPLIT 0x0070 42305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 425655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS 4 426915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_DEVFN 0x000000ff 427655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_BUS 0x0000ff00 42805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_64BIT 0x00010000 430655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_133MHZ 0x00020000 431915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_SPL_DISC 0x00040000 432655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_UNX_SPL 0x00080000 43305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_COMPLEX 0x00100000 435655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_READ 0x00600000 436915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_MAX_SPLIT 0x03800000 437655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_CUM 0x1c000000 43805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_SPL_ERR 0x20000000 440655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_266MHZ 0x40000000 441915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_STATUS_533MHZ 0x80000000 442655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_ECC_CSR 8 44305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V0 8 445655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V1 24 446915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 447655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_SSTATUS 2 44805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_64BIT 0x0001 450655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_133MHZ 0x0002 451915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_SSTATUS_FREQ 0x03c0 452655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_VERS 0x3000 45305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V1 0x1000 455655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V2 0x2000 456915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_X_SSTATUS_266MHZ 0x4000 457655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_533MHZ 0x8000 45805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_STATUS 4 460655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SSVID_VENDOR_ID 4 461915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SSVID_DEVICE_ID 6 462655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS 2 46305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_VERS 0x000f 465655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_TYPE 0x00f0 466915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_ENDPOINT 0x0 467655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_LEG_END 0x1 46805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_ROOT_PORT 0x4 470655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_UPSTREAM 0x5 471915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_DOWNSTREAM 0x6 472655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 47305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 475655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_RC_END 0x9 476915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_TYPE_RC_EC 0xa 477655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_SLOT 0x0100 47805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_IRQ 0x3e00 480655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP 4 481915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 48238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 48305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 48438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 48538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_L0S 0x000001c0 486915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_L1 0x00000e00 48738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 48805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 48938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 49038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 491915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP_RBER 0x00008000 49238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 49305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 495655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_FLR 0x10000000 496915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL 8 497655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_CERE 0x0001 49805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NFERE 0x0002 500655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_FERE 0x0004 501915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_URRE 0x0008 502655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 50305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 505655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 506915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_PHANTOM 0x0200 507655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_AUX_PME 0x0400 50805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 510655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_READRQ 0x7000 51105d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_128B 0x0000 51205d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_256B 0x1000 513655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51405d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_512B 0x2000 51505d08e9716b5974d6ed08973f44930804890b902Christopher Ferris#define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 516915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 51738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA 10 51805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_CED 0x0001 52038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_NFED 0x0002 521915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVSTA_FED 0x0004 52238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_URD 0x0008 52305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 52438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_AUXPD 0x0010 52538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_TRPND 0x0020 526915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP 12 52738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS 0x0000000f 52805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 52938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 53038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 531915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_MLW 0x000003f0 532655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 53305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L0SEL 0x00007000 535655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L1EL 0x00038000 536915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_CLKPM 0x00040000 537655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SDERC 0x00080000 53805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 540655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_LBNC 0x00200000 541915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP_PN 0xff000000 542655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL 16 54305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ASPMC 0x0003 54538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 546915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 547655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RCB 0x0008 54805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LD 0x0010 550655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RL 0x0020 551915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_CCC 0x0040 552655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ES 0x0080 55305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 55438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 555655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_HAWD 0x0200 556915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCTL_LBMIE 0x0400 557655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LABIE 0x0800 55805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA 18 560655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_CLS 0x000f 561915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 56238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 56305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 565655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_NLW 0x03f0 566915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_NLW_X1 0x0010 56738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X2 0x0020 56805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X4 0x0040 57038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X8 0x0080 571915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_NLW_SHIFT 4 572655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LT 0x0800 57305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_SLC 0x1000 575655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_DLLLA 0x2000 576915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA_LBMS 0x4000 577655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LABS 0x8000 57805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 580655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP 20 581915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_ABP 0x00000001 582655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PCP 0x00000002 58305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_MRLSP 0x00000004 585655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_AIP 0x00000008 586915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_PIP 0x00000010 587655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPS 0x00000020 58805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPC 0x00000040 590655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_SPLV 0x00007f80 591915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCAP_SPLS 0x00018000 592655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_EIP 0x00020000 59305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_NCCS 0x00040000 595655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PSN 0xfff80000 596915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL 24 597655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_ABPE 0x0001 59805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PFDE 0x0002 600655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_MRLSCE 0x0004 601915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PDCE 0x0008 602655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_CCIE 0x0010 60305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_HPIE 0x0020 605655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_AIC 0x00c0 606915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 60738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 60805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 60938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 610655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PIC 0x0300 611915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 61238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 61305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 61438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 615655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PCC 0x0400 616915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTCTL_PWR_ON 0x0000 61738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 61805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_EIC 0x0800 620655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_DLLSCE 0x1000 621915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA 26 622655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_ABP 0x0001 62305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PFD 0x0002 625655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSC 0x0004 626915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA_PDC 0x0008 627655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_CC 0x0010 62805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSS 0x0020 630655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PDS 0x0040 631915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_SLTSTA_EIS 0x0080 632655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_DLLSC 0x0100 63305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL 28 63538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SECEE 0x0001 636915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTCTL_SENFEE 0x0002 63738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SEFEE 0x0004 63805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 63938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_PMEIE 0x0008 64038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_CRSSVE 0x0010 641915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTCAP 30 64282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_RTCAP_CRSVIS 0x0001 64305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTSTA 32 64538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTSTA_PME 0x00010000 646915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_RTSTA_PENDING 0x00020000 64782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCAP2 36 64805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_ARI 0x00000020 65038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_LTR 0x00000800 651915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 65282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 65305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 65438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 655655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL2 40 656915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 65782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCTL2_ARI 0x0020 65805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 65938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 66038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 661915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 66282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 66305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 66438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 66538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 666915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_DEVSTA2 42 66782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 66805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2 44 67038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 671915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 67282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 67305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 67438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 675655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL2 48 676915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXP_LNKSTA2 50 67782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXP_SLTCAP2 52 67805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL2 56 68038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTSTA2 58 681915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 68282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 68305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 685655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ERR 0x01 686915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_VC 0x02 68782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_DSN 0x03 68805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PWR 0x04 690655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCLD 0x05 691915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_RCILC 0x06 69282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_RCEC 0x07 69305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MFVC 0x08 695655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VC9 0x09 696915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_RCRB 0x0A 69782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_VNDR 0x0B 69805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_CAC 0x0C 700655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ACS 0x0D 701915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_ARI 0x0E 70282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_ATS 0x0F 70305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SRIOV 0x10 705655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MRIOV 0x11 706915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_MCAST 0x12 70782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_PRI 0x13 70805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_AMD_XXX 0x14 710655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_REBAR 0x15 711915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_DPA 0x16 71282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_TPH 0x17 71305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_LTR 0x18 715655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SECPCI 0x19 716915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ID_PMUX 0x1A 71782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_EXT_CAP_ID_PASID 0x1B 71805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID 720655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_DSN_SIZEOF 12 721915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 72282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNCOR_STATUS 4 72305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 72482d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNC_UND 0x00000001 725655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_DLP 0x00000010 726915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_SURPDN 0x00000020 72782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNC_POISON_TLP 0x00001000 72805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_FCP 0x00002000 730655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_COMP_TIME 0x00004000 731915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_COMP_ABORT 0x00008000 73282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNC_UNX_COMP 0x00010000 73305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_RX_OVER 0x00020000 735655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_MALF_TLP 0x00040000 736915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_ECRC 0x00080000 73782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNC_UNSUP 0x00100000 73805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ACSV 0x00200000 740655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_INTN 0x00400000 741915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNC_MCBTLP 0x00800000 74282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_UNC_ATOMEG 0x01000000 74305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_TLPPRE 0x02000000 745655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_MASK 8 746915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_UNCOR_SEVER 12 74782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_COR_STATUS 16 74805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_RCVR 0x00000001 750655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_BAD_TLP 0x00000040 751915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_COR_BAD_DLLP 0x00000080 75282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_COR_REP_ROLL 0x00000100 75305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_REP_TIMER 0x00001000 755655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_ADV_NFAT 0x00002000 756915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_COR_INTERNAL 0x00004000 75782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_COR_LOG_OVER 0x00008000 75805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_MASK 20 760655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP 24 761915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_CAP_FEP(x) ((x) & 31) 76282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_CAP_ECRC_GENC 0x00000020 76305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_GENE 0x00000040 765655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 766915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 76782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_HEADER_LOG 28 76805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COMMAND 44 770655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 771915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 77282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 77305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_STATUS 48 775655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COR_RCV 0x00000001 776915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 77782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 77805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 780655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 781915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 78282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 78305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_ERR_SRC 52 78538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP1 4 786915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_CAP1_EVCC 0x00000007 78782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VC_CAP1_LPEVCC 0x00000070 78805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 78938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 79038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP2 8 791915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_CAP2_32_PHASE 0x00000002 79282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VC_CAP2_64_PHASE 0x00000004 79305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_128_PHASE 0x00000008 79538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_ARB_OFF 0xff000000 796915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_PORT_CTRL 12 79782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 79805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_STATUS 14 80038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_STATUS_TABLE 0x00000001 801915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CAP 16 80282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VC_RES_CAP_32_PHASE 0x00000002 80305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_64_PHASE 0x00000004 80538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_128_PHASE 0x00000008 806915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 80782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VC_RES_CAP_256_PHASE 0x00000020 80805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 810655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_CTRL 20 811915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 81282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 81305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ID 0x07000000 81538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ENABLE 0x80000000 816915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VC_RES_STATUS 26 81782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VC_RES_STATUS_TABLE 0x00000001 81805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_STATUS_NEGO 0x00000002 820655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VC_BASE_SIZEOF 0x10 821915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 82282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PWR_DSR 4 82305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA 8 825655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 826915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 82782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 82805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 830655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 831915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 83282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PWR_CAP 12 83305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 835655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_PWR_SIZEOF 16 836915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_VNDR_HEADER 4 83782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 83805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 840655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 841915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_3BIT_CAP_MASK 0xE0 84282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define HT_CAPTYPE_SLAVE 0x00 84305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_HOST 0x20 845655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_5BIT_CAP_MASK 0xF8 846915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_IRQ 0x80 84782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define HT_CAPTYPE_REMAPPING_40 0xA0 84805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_REMAPPING_64 0xA2 850655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_UNITID_CLUMP 0x90 851915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_EXTCONF 0x98 85282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define HT_CAPTYPE_MSI_MAPPING 0xA8 85305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_FLAGS 0x02 855655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS_ENABLE 0x1 856915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_MSI_FLAGS_FIXED 0x2 85782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 85805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_ADDR_LO 0x04 860655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_LO_MASK 0xFFF00000 861915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_MSI_ADDR_HI 0x08 86282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 86305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_VCSET 0xB8 865655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_ERROR_RETRY 0xC0 866915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define HT_CAPTYPE_GEN3 0xD0 86782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define HT_CAPTYPE_PM 0xE0 86805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAP_SIZEOF_LONG 28 870655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAP_SIZEOF_SHORT 24 871915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ARI_CAP 0x04 87282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ARI_CAP_MFVC 0x0001 87305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CAP_ACS 0x0002 875655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 876915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ARI_CTRL 0x06 87782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ARI_CTRL_MFVC 0x0001 87805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CTRL_ACS 0x0002 880655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 881915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ARI_SIZEOF 8 88282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ATS_CAP 0x04 88305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 885655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MAX_QDEP 32 886915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ATS_CTRL 0x06 88782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ATS_CTRL_ENABLE 0x8000 88805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 890655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MIN_STU 12 891915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_ATS_SIZEOF 8 89282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PRI_CTRL 0x04 89305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_CTRL_ENABLE 0x01 895655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL_RESET 0x02 896915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PRI_STATUS 0x06 89782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PRI_STATUS_RF 0x001 89805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_STATUS_UPRGI 0x002 900655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_STOPPED 0x100 901915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PRI_MAX_REQ 0x08 90282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PRI_ALLOC_REQ 0x0c 90305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 90438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PRI_SIZEOF 16 905655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP 0x04 906915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PASID_CAP_EXEC 0x02 90782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PASID_CAP_PRIV 0x04 90805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 90938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PASID_CTRL 0x06 910655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_ENABLE 0x01 911915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_PASID_CTRL_EXEC 0x02 91282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_PASID_CTRL_PRIV 0x04 91305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 91438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PASID_SIZEOF 8 915655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP 0x04 916915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_CAP_VFM 0x01 91782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 91805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 91938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL 0x08 920655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_VFE 0x01 921915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_CTRL_VFM 0x02 92282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SRIOV_CTRL_INTR 0x04 92305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 92438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL_MSE 0x08 925655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_ARI 0x10 926915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_STATUS 0x0a 92782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SRIOV_STATUS_VFM 0x01 92805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 92938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_INITIAL_VF 0x0c 930655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_TOTAL_VF 0x0e 931915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_NUM_VF 0x10 93282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SRIOV_FUNC_LINK 0x12 93305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 93438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VF_OFFSET 0x14 935655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_STRIDE 0x16 936915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_VF_DID 0x1a 93782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SRIOV_SUP_PGSIZE 0x1c 93805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 93938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_SYS_PGSIZE 0x20 940655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_BAR 0x24 941915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_NUM_BARS 6 94282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SRIOV_VFM 0x3c 94305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 945655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 946915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SRIOV_VFM_UA 0x0 94782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SRIOV_VFM_MI 0x1 94805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_MO 0x2 950655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_AV 0x3 951915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_EXT_CAP_SRIOV_SIZEOF 64 95282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_LTR_MAX_SNOOP_LAT 0x4 95305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 95438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 955655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_VALUE_MASK 0x000003ff 956915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_LTR_SCALE_MASK 0x00001c00 95782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_LTR_SCALE_SHIFT 10 95805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 95938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_LTR_SIZEOF 8 960655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CAP 0x04 961915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_SV 0x01 96282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ACS_TB 0x02 96305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 96438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_RR 0x04 965655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CR 0x08 966915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_UF 0x10 96782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ACS_EC 0x20 96805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 96938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_DT 0x40 970655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EGRESS_BITS 0x05 971915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_ACS_CTRL 0x06 97282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_ACS_EGRESS_CTL_V 0x08 97305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 97438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VSEC_HDR 4 975655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VSEC_HDR_LEN_SHIFT 20 976915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SATA_REGS 4 97782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_SATA_REGS_MASK 0xF 97805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 97938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SATA_REGS_INLINE 0xF 980655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_SIZEOF_SHORT 8 981915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_SATA_SIZEOF_LONG 16 98282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_REBAR_CTRL 8 98305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 98438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) 985655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL_NBAR_SHIFT 5 986915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_DPA_CAP 4 98782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 98805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 98938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_DPA_BASE_SIZEOF 16 990655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP 4 991915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_TPH_CAP_LOC_MASK 0x600 99282d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_TPH_LOC_NONE 0x000 99305d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_LOC_CAP 0x200 995655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_MSIX 0x400 996915bf813ad8761ce270d1422c483cfd252151d42Christopher Ferris#define PCI_TPH_CAP_ST_MASK 0x07FF0000 99782d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0fChristopher Ferris#define PCI_TPH_CAP_ST_SHIFT 16 99805d08e9716b5974d6ed08973f44930804890b902Christopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_BASE_SIZEOF 12 1000655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 1001