pci_regs.h revision 38062f954c637861348dd8078cefb73554e6f12c
1655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/**************************************************************************** 2655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 3655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 4655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** This header was automatically generated from a Linux kernel header 5655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** of the same name, to make information necessary for userspace to 6655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** call into the kernel available to libc. It contains only constants, 7655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** structures, and macros generated from the original header, and thus, 8655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** contains no copyrightable information. 9655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 10655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** To edit the content of this header, modify the corresponding 11655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** source file (e.g. under external/kernel-headers/original/) then 12655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** run bionic/libc/kernel/tools/update_all.py 13655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 14655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** Any manual change here will be lost the next time this script will 15655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** be run. You've been warned! 16655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng *** 17655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng **************************************************************************** 18655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng ****************************************************************************/ 19655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#ifndef LINUX_PCI_REGS_H 20655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define LINUX_PCI_REGS_H 21655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STD_HEADER_SIZEOF 64 22655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VENDOR_ID 0x00 23655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DEVICE_ID 0x02 25655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND 0x04 26655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_IO 0x1 27655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MEMORY 0x2 28655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_MASTER 0x4 30655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SPECIAL 0x8 31655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INVALIDATE 0x10 32655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_VGA_PALETTE 0x20 33655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_PARITY 0x40 35655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_WAIT 0x80 36655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_SERR 0x100 37655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_FAST_BACK 0x200 38655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_COMMAND_INTX_DISABLE 0x400 40655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS 0x06 41655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_INTERRUPT 0x08 42655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_CAP_LIST 0x10 43655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_66MHZ 0x20 45655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_UDF 0x40 46655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_FAST_BACK 0x80 47655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_PARITY 0x100 48655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MASK 0x600 50655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_FAST 0x000 51655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_MEDIUM 0x200 52655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DEVSEL_SLOW 0x400 53655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_TARGET_ABORT 0x800 55655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_TARGET_ABORT 0x1000 56655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_REC_MASTER_ABORT 0x2000 57655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 58655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_STATUS_DETECTED_PARITY 0x8000 60655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_REVISION 0x08 61655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REVISION_ID 0x08 62655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_PROG 0x09 63655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CLASS_DEVICE 0x0a 65655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CACHE_LINE_SIZE 0x0c 66655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LATENCY_TIMER 0x0d 67655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE 0x0e 68655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_NORMAL 0 70655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_BRIDGE 1 71655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_HEADER_TYPE_CARDBUS 2 72655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST 0x0f 73655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CODE_MASK 0x0f 75655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_START 0x40 76655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BIST_CAPABLE 0x80 77655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_0 0x10 78655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_1 0x14 80655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_2 0x18 81655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_3 0x1c 82655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_4 0x20 83655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_5 0x24 85655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE 0x01 86655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_IO 0x01 87655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 88655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 90655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 91655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 92655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 93655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 95655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 96655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 97655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CARDBUS_CIS 0x28 98655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 100655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBSYSTEM_ID 0x2e 101655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS 0x30 102655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_ENABLE 0x01 103655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 105655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAPABILITY_LIST 0x34 106655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_LINE 0x3c 107655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_INTERRUPT_PIN 0x3d 108655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MIN_GNT 0x3e 110655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MAX_LAT 0x3f 111655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRIMARY_BUS 0x18 112655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SECONDARY_BUS 0x19 113655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SUBORDINATE_BUS 0x1a 115655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_LATENCY_TIMER 0x1b 116655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE 0x1c 117655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT 0x1d 118655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_MASK 0x0fUL 120655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_16 0x00 121655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_TYPE_32 0x01 122655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_RANGE_MASK (~0x0fUL) 123655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_1K_RANGE_MASK (~0x03UL) 125655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SEC_STATUS 0x1e 126655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_BASE 0x20 127655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_LIMIT 0x22 128655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 130655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 131655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_BASE 0x24 132655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_MEMORY_LIMIT 0x26 133655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 135655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_32 0x00 136655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_TYPE_64 0x01 137655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_RANGE_MASK (~0x0fUL) 138655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_BASE_UPPER32 0x28 140655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PREF_LIMIT_UPPER32 0x2c 141655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_BASE_UPPER16 0x30 142655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_IO_LIMIT_UPPER16 0x32 143655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ROM_ADDRESS1 0x38 145655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CONTROL 0x3e 146655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_PARITY 0x01 147655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_SERR 0x02 148655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_ISA 0x04 150655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_VGA 0x08 151655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 152655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_BUS_RESET 0x40 153655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_BRIDGE_CTL_FAST_BACK 0x80 155655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CAPABILITY_LIST 0x14 156655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SEC_STATUS 0x16 157655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_PRIMARY_BUS 0x18 158655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_CARD_BUS 0x19 160655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBORDINATE_BUS 0x1a 161655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LATENCY_TIMER 0x1b 162655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_0 0x1c 163655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_0 0x20 165655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_BASE_1 0x24 166655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_MEMORY_LIMIT_1 0x28 167655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0 0x2c 168655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_0_HI 0x2e 170655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0 0x30 171655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_0_HI 0x32 172655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1 0x34 173655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_BASE_1_HI 0x36 175655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1 0x38 176655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_LIMIT_1_HI 0x3a 177655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_IO_RANGE_MASK (~0x03UL) 178655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CONTROL 0x3e 180655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PARITY 0x01 181655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_SERR 0x02 182655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_ISA 0x04 183655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_VGA 0x08 185655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 186655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 187655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 188655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 190655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 191655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 192655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 193655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_SUBSYSTEM_ID 0x42 195655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CB_LEGACY_MODE_BASE 0x44 196655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_LIST_ID 0 197655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PM 0x01 198655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP 0x02 200655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VPD 0x03 201655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SLOTID 0x04 202655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSI 0x05 203655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CHSWP 0x06 205655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_PCIX 0x07 206655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_HT 0x08 207655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_VNDR 0x09 208655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_DBG 0x0A 210655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_CCRC 0x0B 211655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SHPC 0x0C 212655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SSVID 0x0D 213655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AGP3 0x0E 215655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SECDEV 0x0F 216655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_EXP 0x10 217655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MSIX 0x11 218655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_SATA 0x12 220655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_AF 0x13 221655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_ID_MAX PCI_CAP_ID_AF 222655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_LIST_NEXT 1 223655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_FLAGS 2 225655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_SIZEOF 4 226655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PMC 2 227655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_VER_MASK 0x0007 228655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_CLOCK 0x0008 230655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_RESERVED 0x0010 231655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_DSI 0x0020 232655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_AUX_POWER 0x01C0 233655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D1 0x0200 235655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_D2 0x0400 236655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME 0x0800 237655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_MASK 0xF800 238655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D0 0x0800 240655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D1 0x1000 241655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D2 0x2000 242655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D3 0x4000 243655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_D3cold 0x8000 245655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CAP_PME_SHIFT 11 246655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL 4 247655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_STATE_MASK 0x0003 248655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 250655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_ENABLE 0x0100 251655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 252655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 253655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_CTRL_PME_STATUS 0x8000 255655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_EXTENSIONS 6 256655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_PPB_B2_B3 0x40 257655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_BPCC_ENABLE 0x80 258655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_DATA_REGISTER 7 260655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PM_SIZEOF 8 261655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_VERSION 2 262655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_RFU 3 263655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS 4 265655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RQ_MASK 0xff000000 266655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_SBA 0x0200 267655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_64BIT 0x0020 268655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_FW 0x0010 270655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE4 0x0004 271655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE2 0x0002 272655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_STATUS_RATE1 0x0001 273655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND 8 275655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 276655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_SBA 0x0200 277655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_AGP 0x0100 278655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_64BIT 0x0020 280655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_FW 0x0010 281655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE4 0x0004 282655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE2 0x0002 283655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_COMMAND_RATE1 0x0001 285655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AGP_SIZEOF 12 286655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR 2 287655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR_MASK 0x7fff 288655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_ADDR_F 0x8000 290655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VPD_DATA 4 291655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VPD_SIZEOF 8 292655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR 2 293655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_NSLOTS 0x1f 295655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_ESR_FIC 0x20 296655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SID_CHASSIS_NR 3 297655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS 2 298655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_ENABLE 0x0001 300655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QMASK 0x000e 301655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_QSIZE 0x0070 302655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_64BIT 0x0080 303655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_FLAGS_MASKBIT 0x0100 305655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_RFU 3 306655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_ADDRESS_LO 4 307655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_ADDRESS_HI 8 308655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_DATA_32 8 310655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_32 12 311655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_32 16 312655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_DATA_64 12 313655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_MASK_64 16 315655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSI_PENDING_64 20 316655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS 2 317655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_QSIZE 0x07FF 318655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_MASKALL 0x4000 320655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_FLAGS_ENABLE 0x8000 321655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE 4 322655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE_BIR 0x00000007 323655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 325655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA 8 326655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA_BIR 0x00000007 327655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_PBA_OFFSET 0xfffffff8 328655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_MSIX_SIZEOF 12 330655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_SIZE 16 331655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_LOWER_ADDR 0 332655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_UPPER_ADDR 4 33338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_DATA 8 335655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 336655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 337655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_CSR 2 33838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_DHA 0x01 340655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EIM 0x02 341655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_PIE 0x04 342655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_LOO 0x08 34338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_PI 0x30 345655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_EXT 0x40 346655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CHSWP_INS 0x80 347655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_LENGTH 2 34838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP 3 350655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP_TP 0x01 351655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CAP_FLR 0x02 352655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CTRL 4 35338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_CTRL_FLR 0x01 355655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_STATUS 5 356655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_AF_STATUS_TP 0x01 357655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_AF_SIZEOF 6 35838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD 2 360655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_DPERR_E 0x0001 361655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_ERO 0x0002 362655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_512 0x0000 36338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_1K 0x0004 365655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_2K 0x0008 366655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_READ_4K 0x000c 367655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_MAX_READ 0x000c 36838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_1 0x0000 370655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_2 0x0010 371655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_3 0x0020 372655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_4 0x0030 37338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_8 0x0040 375655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_12 0x0050 376655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_16 0x0060 377655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_SPLIT_32 0x0070 37838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_MAX_SPLIT 0x0070 380655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 381655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS 4 382655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_DEVFN 0x000000ff 38338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_BUS 0x0000ff00 385655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_64BIT 0x00010000 386655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_133MHZ 0x00020000 387655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_SPL_DISC 0x00040000 38838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_UNX_SPL 0x00080000 390655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_COMPLEX 0x00100000 391655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_READ 0x00600000 392655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_SPLIT 0x03800000 39338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_MAX_CUM 0x1c000000 395655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_SPL_ERR 0x20000000 396655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_266MHZ 0x40000000 397655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_STATUS_533MHZ 0x80000000 39838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_ECC_CSR 8 400655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V0 8 401655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V1 24 402655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 40338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_SSTATUS 2 405655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_64BIT 0x0001 406655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_133MHZ 0x0002 407655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_FREQ 0x03c0 40838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_VERS 0x3000 410655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V1 0x1000 411655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_V2 0x2000 412655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_266MHZ 0x4000 41338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_SSTATUS_533MHZ 0x8000 415655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_X_BRIDGE_STATUS 4 416655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SSVID_VENDOR_ID 4 417655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SSVID_DEVICE_ID 6 41838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS 2 420655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_VERS 0x000f 421655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_TYPE 0x00f0 422655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_ENDPOINT 0x0 42338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_LEG_END 0x1 425655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_ROOT_PORT 0x4 426655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_UPSTREAM 0x5 427655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_DOWNSTREAM 0x6 42838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 430655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 431655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_RC_END 0x9 432655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_TYPE_RC_EC 0xa 43338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_SLOT 0x0100 435655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_FLAGS_IRQ 0x3e00 436655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP 4 43738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 438655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 43938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 44038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 44138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_L0S 0x000001c0 44238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_L1 0x00000e00 443655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 44538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 44638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 44738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_RBER 0x00008000 448655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 45038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 451655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP_FLR 0x10000000 452655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL 8 45338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_CERE 0x0001 455655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NFERE 0x0002 456655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_FERE 0x0004 457655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_URRE 0x0008 45838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 460655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 461655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 462655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_PHANTOM 0x0200 46338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_AUX_PME 0x0400 465655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 466655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_READRQ 0x7000 467655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 468655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 46938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA 10 47038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_CED 0x0001 47138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_NFED 0x0002 47238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_FED 0x0004 473655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 47438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_URD 0x0008 47538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_AUXPD 0x0010 47638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA_TRPND 0x0020 477655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP 12 478655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 47938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS 0x0000000f 48038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 48138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 482655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_MLW 0x000003f0 48338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 485655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L0SEL 0x00007000 486655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_L1EL 0x00038000 487655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_CLKPM 0x00040000 48838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_SDERC 0x00080000 490655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 491655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_LBNC 0x00200000 492655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP_PN 0xff000000 49338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL 16 495655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ASPMC 0x0003 49638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 49738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 498655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RCB 0x0008 500655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LD 0x0010 501655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_RL 0x0020 502655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_CCC 0x0040 50338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_ES 0x0080 50538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 506655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_HAWD 0x0200 507655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LBMIE 0x0400 50838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL_LABIE 0x0800 510655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA 18 511655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_CLS 0x000f 51238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 513655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 51538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 516655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_NLW 0x03f0 51738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X1 0x0010 51838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 51938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X2 0x0020 52038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X4 0x0040 52138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKSTA_NLW_X8 0x0080 522655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_NLW_SHIFT 4 523655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LT 0x0800 525655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_SLC 0x1000 526655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_DLLLA 0x2000 527655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LBMS 0x4000 528655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA_LABS 0x8000 530655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 531655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP 20 532655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_ABP 0x00000001 533655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PCP 0x00000002 535655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_MRLSP 0x00000004 536655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_AIP 0x00000008 537655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PIP 0x00000010 538655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPS 0x00000020 540655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_HPC 0x00000040 541655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_SPLV 0x00007f80 542655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_SPLS 0x00018000 543655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_EIP 0x00020000 545655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_NCCS 0x00040000 546655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCAP_PSN 0xfff80000 547655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL 24 548655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_ABPE 0x0001 550655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PFDE 0x0002 551655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_MRLSCE 0x0004 552655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PDCE 0x0008 553655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_CCIE 0x0010 555655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_HPIE 0x0020 556655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_AIC 0x00c0 55738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 55838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 55938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 56038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 561655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PIC 0x0300 56238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 563655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 56538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 566655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_PCC 0x0400 56738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_ON 0x0000 56838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 56938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 570655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_EIC 0x0800 571655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL_DLLSCE 0x1000 572655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA 26 573655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_ABP 0x0001 575655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PFD 0x0002 576655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSC 0x0004 577655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PDC 0x0008 578655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_CC 0x0010 580655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_MRLSS 0x0020 581655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_PDS 0x0040 582655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_EIS 0x0080 583655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTSTA_DLLSC 0x0100 585655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCTL 28 58638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SECEE 0x0001 58738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SENFEE 0x0002 588655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 58938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_SEFEE 0x0004 59038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_PMEIE 0x0008 59138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTCTL_CRSSVE 0x0010 592655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTCAP 30 593655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_RTSTA 32 59538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTSTA_PME 0x00010000 59638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_RTSTA_PENDING 0x00020000 597655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCAP2 36 598655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_ARI 0x00000020 60038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_LTR 0x00000800 60138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 60238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 603655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 60438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 605655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_DEVCTL2 40 60638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 60738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_ARI 0x0020 608655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 60938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 61038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 61138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 61238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 613655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 61438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 61538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 61638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_DEVSTA2 42 617655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 61838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCAP2 44 62038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 62138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 62238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 623655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 62438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 625655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKCTL2 48 626655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_LNKSTA2 50 62738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTCAP2 52 62838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXP_SLTCTL2 56 63038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXP_SLTSTA2 58 631655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 632655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 633655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 635655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ERR 0x01 636655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VC 0x02 637655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_DSN 0x03 638655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PWR 0x04 640655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCLD 0x05 641655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCILC 0x06 642655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCEC 0x07 643655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MFVC 0x08 645655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VC9 0x09 646655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_RCRB 0x0A 647655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_VNDR 0x0B 648655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_CAC 0x0C 650655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ACS 0x0D 651655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ARI 0x0E 652655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_ATS 0x0F 653655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SRIOV 0x10 655655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MRIOV 0x11 656655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MCAST 0x12 657655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PRI 0x13 658655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_AMD_XXX 0x14 660655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_REBAR 0x15 661655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_DPA 0x16 662655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_TPH 0x17 663655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_LTR 0x18 665655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_SECPCI 0x19 666655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PMUX 0x1A 667655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_PASID 0x1B 668655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID 670655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_DSN_SIZEOF 12 671655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 672655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_STATUS 4 673655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_TRAIN 0x00000001 675655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_DLP 0x00000010 676655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_SURPDN 0x00000020 677655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_POISON_TLP 0x00001000 678655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_FCP 0x00002000 680655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_COMP_TIME 0x00004000 681655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_COMP_ABORT 0x00008000 682655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_UNX_COMP 0x00010000 683655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_RX_OVER 0x00020000 685655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_MALF_TLP 0x00040000 686655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ECRC 0x00080000 687655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_UNSUP 0x00100000 688655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ACSV 0x00200000 690655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_INTN 0x00400000 691655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_MCBTLP 0x00800000 692655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_ATOMEG 0x01000000 693655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNC_TLPPRE 0x02000000 695655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_MASK 8 696655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_UNCOR_SEVER 12 697655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_STATUS 16 698655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_RCVR 0x00000001 700655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_BAD_TLP 0x00000040 701655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_BAD_DLLP 0x00000080 702655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_REP_ROLL 0x00000100 703655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_REP_TIMER 0x00001000 705655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_ADV_NFAT 0x00002000 706655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_INTERNAL 0x00004000 707655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_LOG_OVER 0x00008000 708655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_COR_MASK 20 710655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP 24 711655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_FEP(x) ((x) & 31) 712655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_GENC 0x00000020 713655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_GENE 0x00000040 715655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 716655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 717655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_HEADER_LOG 28 718655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COMMAND 44 720655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 721655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 722655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 723655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_STATUS 48 725655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_COR_RCV 0x00000001 726655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 727655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 728655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 730655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 731655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 732655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 733655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ERR_ROOT_ERR_SRC 52 73538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP1 4 73638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP1_EVCC 0x00000007 73738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP1_LPEVCC 0x00000070 738655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 73938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 74038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CAP2 8 74138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_32_PHASE 0x00000002 74238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_64_PHASE 0x00000004 74338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_128_PHASE 0x00000008 74538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_CAP2_ARB_OFF 0xff000000 746655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_CTRL 12 74738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 748655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_PORT_STATUS 14 75038062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_PORT_STATUS_TABLE 0x00000001 751655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_CAP 16 75238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_32_PHASE 0x00000002 75338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 75438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_64_PHASE 0x00000004 75538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_128_PHASE 0x00000008 75638062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 75738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_256_PHASE 0x00000020 75838062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 75938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 760655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_CTRL 20 76138062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 76238062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 76338062f954c637861348dd8078cefb73554e6f12cChristopher Ferris/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 76438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ID 0x07000000 76538062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_CTRL_ENABLE 0x80000000 766655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VC_RES_STATUS 26 76738062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_STATUS_TABLE 0x00000001 768655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 76938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VC_RES_STATUS_NEGO 0x00000002 770655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VC_BASE_SIZEOF 0x10 771655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 772655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DSR 4 773655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 77438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA 8 775655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 776655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 777655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 778655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 77938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 780655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 781655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 782655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PWR_CAP 12 783655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 78438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 785655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_PWR_SIZEOF 16 786655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER 4 787655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 788655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 78938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 790655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 791655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_3BIT_CAP_MASK 0xE0 792655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_SLAVE 0x00 793655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_HOST 0x20 795655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_5BIT_CAP_MASK 0xF8 796655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_IRQ 0x80 797655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_REMAPPING_40 0xA0 798655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_REMAPPING_64 0xA2 800655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_UNITID_CLUMP 0x90 801655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_EXTCONF 0x98 802655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_MSI_MAPPING 0xA8 803655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_FLAGS 0x02 805655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS_ENABLE 0x1 806655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FLAGS_FIXED 0x2 807655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 808655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 80938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_MSI_ADDR_LO 0x04 810655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_LO_MASK 0xFFF00000 811655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_MSI_ADDR_HI 0x08 812655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 813655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAPTYPE_VCSET 0xB8 815655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_ERROR_RETRY 0xC0 816655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_GEN3 0xD0 817655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAPTYPE_PM 0xE0 818655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 81938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define HT_CAP_SIZEOF_LONG 28 820655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define HT_CAP_SIZEOF_SHORT 24 821655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP 0x04 822655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_MFVC 0x0001 823655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CAP_ACS 0x0002 825655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 826655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL 0x06 827655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_MFVC 0x0001 828655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 82938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ARI_CTRL_ACS 0x0002 830655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 831655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ARI_SIZEOF 8 832655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CAP 0x04 833655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 835655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MAX_QDEP 32 836655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CTRL 0x06 837655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_CTRL_ENABLE 0x8000 838655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 83938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 840655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ATS_MIN_STU 12 841655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_ATS_SIZEOF 8 842655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL 0x04 843655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_CTRL_ENABLE 0x01 845655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_CTRL_RESET 0x02 846655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS 0x06 847655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_RF 0x001 848655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PRI_STATUS_UPRGI 0x002 850655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_STATUS_STOPPED 0x100 851655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_MAX_REQ 0x08 852655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PRI_ALLOC_REQ 0x0c 853655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PRI_SIZEOF 16 855655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP 0x04 856655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP_EXEC 0x02 857655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CAP_PRIV 0x04 858655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 85938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_PASID_CTRL 0x06 860655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_ENABLE 0x01 861655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_EXEC 0x02 862655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_PASID_CTRL_PRIV 0x04 863655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_PASID_SIZEOF 8 865655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP 0x04 866655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP_VFM 0x01 867655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 868655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 86938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL 0x08 870655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_VFE 0x01 871655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_VFM 0x02 872655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_INTR 0x04 873655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_CTRL_MSE 0x08 875655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_CTRL_ARI 0x10 876655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_STATUS 0x0a 877655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_STATUS_VFM 0x01 878655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 87938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_INITIAL_VF 0x0c 880655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_TOTAL_VF 0x0e 881655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_NUM_VF 0x10 882655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_FUNC_LINK 0x12 883655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VF_OFFSET 0x14 885655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_STRIDE 0x16 886655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VF_DID 0x1a 887655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_SUP_PGSIZE 0x1c 888655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 88938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_SYS_PGSIZE 0x20 890655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_BAR 0x24 891655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_NUM_BARS 6 892655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM 0x3c 893655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 895655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 896655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_UA 0x0 897655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_MI 0x1 898655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SRIOV_VFM_MO 0x2 900655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SRIOV_VFM_AV 0x3 901655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_EXT_CAP_SRIOV_SIZEOF 64 902655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_MAX_SNOOP_LAT 0x4 903655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 90438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 905655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_VALUE_MASK 0x000003ff 906655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_SCALE_MASK 0x00001c00 907655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_LTR_SCALE_SHIFT 10 908655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 90938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_EXT_CAP_LTR_SIZEOF 8 910655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CAP 0x04 911655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_SV 0x01 912655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_TB 0x02 913655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 91438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_RR 0x04 915655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CR 0x08 916655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_UF 0x10 917655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EC 0x20 918655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 91938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_ACS_DT 0x40 920655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EGRESS_BITS 0x05 921655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_CTRL 0x06 922655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_ACS_EGRESS_CTL_V 0x08 923655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 92438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_VSEC_HDR 4 925655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_VSEC_HDR_LEN_SHIFT 20 926655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_REGS 4 927655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_REGS_MASK 0xF 928655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 92938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_SATA_REGS_INLINE 0xF 930655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_SIZEOF_SHORT 8 931655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_SATA_SIZEOF_LONG 16 932655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL 8 933655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 93438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) 935655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_REBAR_CTRL_NBAR_SHIFT 5 936655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DPA_CAP 4 937655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 938655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 93938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_DPA_BASE_SIZEOF 16 940655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP 4 941655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP_LOC_MASK 0x600 942655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_NONE 0x000 943655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94438062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_LOC_CAP 0x200 945655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_LOC_MSIX 0x400 946655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP_ST_MASK 0x07FF0000 947655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#define PCI_TPH_CAP_ST_SHIFT 16 948655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94938062f954c637861348dd8078cefb73554e6f12cChristopher Ferris#define PCI_TPH_BASE_SIZEOF 12 950655a7c081f83b8351ed5f11a6c6accd9458293a8Ben Cheng#endif 951