TargetInfo.cpp revision 2363072da26da25009bf61c3d9d056a028d4d720
1//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// These classes wrap the information about a call or function 11// definition used to handle ABI compliancy. 12// 13//===----------------------------------------------------------------------===// 14 15#include "TargetInfo.h" 16#include "ABIInfo.h" 17#include "CGCXXABI.h" 18#include "CodeGenFunction.h" 19#include "clang/AST/RecordLayout.h" 20#include "clang/Frontend/CodeGenOptions.h" 21#include "llvm/ADT/Triple.h" 22#include "llvm/IR/DataLayout.h" 23#include "llvm/IR/Type.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace clang; 26using namespace CodeGen; 27 28static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, 29 llvm::Value *Array, 30 llvm::Value *Value, 31 unsigned FirstIndex, 32 unsigned LastIndex) { 33 // Alternatively, we could emit this as a loop in the source. 34 for (unsigned I = FirstIndex; I <= LastIndex; ++I) { 35 llvm::Value *Cell = Builder.CreateConstInBoundsGEP1_32(Array, I); 36 Builder.CreateStore(Value, Cell); 37 } 38} 39 40static bool isAggregateTypeForABI(QualType T) { 41 return !CodeGenFunction::hasScalarEvaluationKind(T) || 42 T->isMemberFunctionPointerType(); 43} 44 45ABIInfo::~ABIInfo() {} 46 47static bool isRecordReturnIndirect(const RecordType *RT, 48 CGCXXABI &CXXABI) { 49 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); 50 if (!RD) 51 return false; 52 return CXXABI.isReturnTypeIndirect(RD); 53} 54 55 56static bool isRecordReturnIndirect(QualType T, CGCXXABI &CXXABI) { 57 const RecordType *RT = T->getAs<RecordType>(); 58 if (!RT) 59 return false; 60 return isRecordReturnIndirect(RT, CXXABI); 61} 62 63static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, 64 CGCXXABI &CXXABI) { 65 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); 66 if (!RD) 67 return CGCXXABI::RAA_Default; 68 return CXXABI.getRecordArgABI(RD); 69} 70 71static CGCXXABI::RecordArgABI getRecordArgABI(QualType T, 72 CGCXXABI &CXXABI) { 73 const RecordType *RT = T->getAs<RecordType>(); 74 if (!RT) 75 return CGCXXABI::RAA_Default; 76 return getRecordArgABI(RT, CXXABI); 77} 78 79CGCXXABI &ABIInfo::getCXXABI() const { 80 return CGT.getCXXABI(); 81} 82 83ASTContext &ABIInfo::getContext() const { 84 return CGT.getContext(); 85} 86 87llvm::LLVMContext &ABIInfo::getVMContext() const { 88 return CGT.getLLVMContext(); 89} 90 91const llvm::DataLayout &ABIInfo::getDataLayout() const { 92 return CGT.getDataLayout(); 93} 94 95const TargetInfo &ABIInfo::getTarget() const { 96 return CGT.getTarget(); 97} 98 99void ABIArgInfo::dump() const { 100 raw_ostream &OS = llvm::errs(); 101 OS << "(ABIArgInfo Kind="; 102 switch (TheKind) { 103 case Direct: 104 OS << "Direct Type="; 105 if (llvm::Type *Ty = getCoerceToType()) 106 Ty->print(OS); 107 else 108 OS << "null"; 109 break; 110 case Extend: 111 OS << "Extend"; 112 break; 113 case Ignore: 114 OS << "Ignore"; 115 break; 116 case Indirect: 117 OS << "Indirect Align=" << getIndirectAlign() 118 << " ByVal=" << getIndirectByVal() 119 << " Realign=" << getIndirectRealign(); 120 break; 121 case Expand: 122 OS << "Expand"; 123 break; 124 } 125 OS << ")\n"; 126} 127 128TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; } 129 130// If someone can figure out a general rule for this, that would be great. 131// It's probably just doomed to be platform-dependent, though. 132unsigned TargetCodeGenInfo::getSizeOfUnwindException() const { 133 // Verified for: 134 // x86-64 FreeBSD, Linux, Darwin 135 // x86-32 FreeBSD, Linux, Darwin 136 // PowerPC Linux, Darwin 137 // ARM Darwin (*not* EABI) 138 // AArch64 Linux 139 return 32; 140} 141 142bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args, 143 const FunctionNoProtoType *fnType) const { 144 // The following conventions are known to require this to be false: 145 // x86_stdcall 146 // MIPS 147 // For everything else, we just prefer false unless we opt out. 148 return false; 149} 150 151void 152TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib, 153 llvm::SmallString<24> &Opt) const { 154 // This assumes the user is passing a library name like "rt" instead of a 155 // filename like "librt.a/so", and that they don't care whether it's static or 156 // dynamic. 157 Opt = "-l"; 158 Opt += Lib; 159} 160 161static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays); 162 163/// isEmptyField - Return true iff a the field is "empty", that is it 164/// is an unnamed bit-field or an (array of) empty record(s). 165static bool isEmptyField(ASTContext &Context, const FieldDecl *FD, 166 bool AllowArrays) { 167 if (FD->isUnnamedBitfield()) 168 return true; 169 170 QualType FT = FD->getType(); 171 172 // Constant arrays of empty records count as empty, strip them off. 173 // Constant arrays of zero length always count as empty. 174 if (AllowArrays) 175 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 176 if (AT->getSize() == 0) 177 return true; 178 FT = AT->getElementType(); 179 } 180 181 const RecordType *RT = FT->getAs<RecordType>(); 182 if (!RT) 183 return false; 184 185 // C++ record fields are never empty, at least in the Itanium ABI. 186 // 187 // FIXME: We should use a predicate for whether this behavior is true in the 188 // current ABI. 189 if (isa<CXXRecordDecl>(RT->getDecl())) 190 return false; 191 192 return isEmptyRecord(Context, FT, AllowArrays); 193} 194 195/// isEmptyRecord - Return true iff a structure contains only empty 196/// fields. Note that a structure with a flexible array member is not 197/// considered empty. 198static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) { 199 const RecordType *RT = T->getAs<RecordType>(); 200 if (!RT) 201 return 0; 202 const RecordDecl *RD = RT->getDecl(); 203 if (RD->hasFlexibleArrayMember()) 204 return false; 205 206 // If this is a C++ record, check the bases first. 207 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 208 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 209 e = CXXRD->bases_end(); i != e; ++i) 210 if (!isEmptyRecord(Context, i->getType(), true)) 211 return false; 212 213 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 214 i != e; ++i) 215 if (!isEmptyField(Context, *i, AllowArrays)) 216 return false; 217 return true; 218} 219 220/// isSingleElementStruct - Determine if a structure is a "single 221/// element struct", i.e. it has exactly one non-empty field or 222/// exactly one field which is itself a single element 223/// struct. Structures with flexible array members are never 224/// considered single element structs. 225/// 226/// \return The field declaration for the single non-empty field, if 227/// it exists. 228static const Type *isSingleElementStruct(QualType T, ASTContext &Context) { 229 const RecordType *RT = T->getAsStructureType(); 230 if (!RT) 231 return 0; 232 233 const RecordDecl *RD = RT->getDecl(); 234 if (RD->hasFlexibleArrayMember()) 235 return 0; 236 237 const Type *Found = 0; 238 239 // If this is a C++ record, check the bases first. 240 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 241 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 242 e = CXXRD->bases_end(); i != e; ++i) { 243 // Ignore empty records. 244 if (isEmptyRecord(Context, i->getType(), true)) 245 continue; 246 247 // If we already found an element then this isn't a single-element struct. 248 if (Found) 249 return 0; 250 251 // If this is non-empty and not a single element struct, the composite 252 // cannot be a single element struct. 253 Found = isSingleElementStruct(i->getType(), Context); 254 if (!Found) 255 return 0; 256 } 257 } 258 259 // Check for single element. 260 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 261 i != e; ++i) { 262 const FieldDecl *FD = *i; 263 QualType FT = FD->getType(); 264 265 // Ignore empty fields. 266 if (isEmptyField(Context, FD, true)) 267 continue; 268 269 // If we already found an element then this isn't a single-element 270 // struct. 271 if (Found) 272 return 0; 273 274 // Treat single element arrays as the element. 275 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 276 if (AT->getSize().getZExtValue() != 1) 277 break; 278 FT = AT->getElementType(); 279 } 280 281 if (!isAggregateTypeForABI(FT)) { 282 Found = FT.getTypePtr(); 283 } else { 284 Found = isSingleElementStruct(FT, Context); 285 if (!Found) 286 return 0; 287 } 288 } 289 290 // We don't consider a struct a single-element struct if it has 291 // padding beyond the element type. 292 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T)) 293 return 0; 294 295 return Found; 296} 297 298static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) { 299 // Treat complex types as the element type. 300 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) 301 Ty = CTy->getElementType(); 302 303 // Check for a type which we know has a simple scalar argument-passing 304 // convention without any padding. (We're specifically looking for 32 305 // and 64-bit integer and integer-equivalents, float, and double.) 306 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() && 307 !Ty->isEnumeralType() && !Ty->isBlockPointerType()) 308 return false; 309 310 uint64_t Size = Context.getTypeSize(Ty); 311 return Size == 32 || Size == 64; 312} 313 314/// canExpandIndirectArgument - Test whether an argument type which is to be 315/// passed indirectly (on the stack) would have the equivalent layout if it was 316/// expanded into separate arguments. If so, we prefer to do the latter to avoid 317/// inhibiting optimizations. 318/// 319// FIXME: This predicate is missing many cases, currently it just follows 320// llvm-gcc (checks that all fields are 32-bit or 64-bit primitive types). We 321// should probably make this smarter, or better yet make the LLVM backend 322// capable of handling it. 323static bool canExpandIndirectArgument(QualType Ty, ASTContext &Context) { 324 // We can only expand structure types. 325 const RecordType *RT = Ty->getAs<RecordType>(); 326 if (!RT) 327 return false; 328 329 // We can only expand (C) structures. 330 // 331 // FIXME: This needs to be generalized to handle classes as well. 332 const RecordDecl *RD = RT->getDecl(); 333 if (!RD->isStruct() || isa<CXXRecordDecl>(RD)) 334 return false; 335 336 uint64_t Size = 0; 337 338 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 339 i != e; ++i) { 340 const FieldDecl *FD = *i; 341 342 if (!is32Or64BitBasicType(FD->getType(), Context)) 343 return false; 344 345 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know 346 // how to expand them yet, and the predicate for telling if a bitfield still 347 // counts as "basic" is more complicated than what we were doing previously. 348 if (FD->isBitField()) 349 return false; 350 351 Size += Context.getTypeSize(FD->getType()); 352 } 353 354 // Make sure there are not any holes in the struct. 355 if (Size != Context.getTypeSize(Ty)) 356 return false; 357 358 return true; 359} 360 361namespace { 362/// DefaultABIInfo - The default implementation for ABI specific 363/// details. This implementation provides information which results in 364/// self-consistent and sensible LLVM IR generation, but does not 365/// conform to any particular ABI. 366class DefaultABIInfo : public ABIInfo { 367public: 368 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 369 370 ABIArgInfo classifyReturnType(QualType RetTy) const; 371 ABIArgInfo classifyArgumentType(QualType RetTy) const; 372 373 virtual void computeInfo(CGFunctionInfo &FI) const { 374 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 375 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 376 it != ie; ++it) 377 it->info = classifyArgumentType(it->type); 378 } 379 380 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 381 CodeGenFunction &CGF) const; 382}; 383 384class DefaultTargetCodeGenInfo : public TargetCodeGenInfo { 385public: 386 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 387 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 388}; 389 390llvm::Value *DefaultABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 391 CodeGenFunction &CGF) const { 392 return 0; 393} 394 395ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const { 396 if (isAggregateTypeForABI(Ty)) { 397 // Records with non trivial destructors/constructors should not be passed 398 // by value. 399 if (isRecordReturnIndirect(Ty, getCXXABI())) 400 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 401 402 return ABIArgInfo::getIndirect(0); 403 } 404 405 // Treat an enum type as its underlying type. 406 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 407 Ty = EnumTy->getDecl()->getIntegerType(); 408 409 return (Ty->isPromotableIntegerType() ? 410 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 411} 412 413ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const { 414 if (RetTy->isVoidType()) 415 return ABIArgInfo::getIgnore(); 416 417 if (isAggregateTypeForABI(RetTy)) 418 return ABIArgInfo::getIndirect(0); 419 420 // Treat an enum type as its underlying type. 421 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 422 RetTy = EnumTy->getDecl()->getIntegerType(); 423 424 return (RetTy->isPromotableIntegerType() ? 425 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 426} 427 428//===----------------------------------------------------------------------===// 429// le32/PNaCl bitcode ABI Implementation 430// 431// This is a simplified version of the x86_32 ABI. Arguments and return values 432// are always passed on the stack. 433//===----------------------------------------------------------------------===// 434 435class PNaClABIInfo : public ABIInfo { 436 public: 437 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 438 439 ABIArgInfo classifyReturnType(QualType RetTy) const; 440 ABIArgInfo classifyArgumentType(QualType RetTy) const; 441 442 virtual void computeInfo(CGFunctionInfo &FI) const; 443 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 444 CodeGenFunction &CGF) const; 445}; 446 447class PNaClTargetCodeGenInfo : public TargetCodeGenInfo { 448 public: 449 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 450 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {} 451}; 452 453void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const { 454 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 455 456 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 457 it != ie; ++it) 458 it->info = classifyArgumentType(it->type); 459 } 460 461llvm::Value *PNaClABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 462 CodeGenFunction &CGF) const { 463 return 0; 464} 465 466/// \brief Classify argument of given type \p Ty. 467ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const { 468 if (isAggregateTypeForABI(Ty)) { 469 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 470 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 471 return ABIArgInfo::getIndirect(0); 472 } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) { 473 // Treat an enum type as its underlying type. 474 Ty = EnumTy->getDecl()->getIntegerType(); 475 } else if (Ty->isFloatingType()) { 476 // Floating-point types don't go inreg. 477 return ABIArgInfo::getDirect(); 478 } 479 480 return (Ty->isPromotableIntegerType() ? 481 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 482} 483 484ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const { 485 if (RetTy->isVoidType()) 486 return ABIArgInfo::getIgnore(); 487 488 // In the PNaCl ABI we always return records/structures on the stack. 489 if (isAggregateTypeForABI(RetTy)) 490 return ABIArgInfo::getIndirect(0); 491 492 // Treat an enum type as its underlying type. 493 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 494 RetTy = EnumTy->getDecl()->getIntegerType(); 495 496 return (RetTy->isPromotableIntegerType() ? 497 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 498} 499 500/// IsX86_MMXType - Return true if this is an MMX type. 501bool IsX86_MMXType(llvm::Type *IRType) { 502 // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>. 503 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 && 504 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() && 505 IRType->getScalarSizeInBits() != 64; 506} 507 508static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 509 StringRef Constraint, 510 llvm::Type* Ty) { 511 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) { 512 if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) { 513 // Invalid MMX constraint 514 return 0; 515 } 516 517 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); 518 } 519 520 // No operation needed 521 return Ty; 522} 523 524//===----------------------------------------------------------------------===// 525// X86-32 ABI Implementation 526//===----------------------------------------------------------------------===// 527 528/// X86_32ABIInfo - The X86-32 ABI information. 529class X86_32ABIInfo : public ABIInfo { 530 enum Class { 531 Integer, 532 Float 533 }; 534 535 static const unsigned MinABIStackAlignInBytes = 4; 536 537 bool IsDarwinVectorABI; 538 bool IsSmallStructInRegABI; 539 bool IsWin32StructABI; 540 unsigned DefaultNumRegisterParameters; 541 542 static bool isRegisterSize(unsigned Size) { 543 return (Size == 8 || Size == 16 || Size == 32 || Size == 64); 544 } 545 546 static bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context, 547 unsigned callingConvention); 548 549 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 550 /// such that the argument will be passed in memory. 551 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, 552 unsigned &FreeRegs) const; 553 554 /// \brief Return the alignment to use for the given type on the stack. 555 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const; 556 557 Class classify(QualType Ty) const; 558 ABIArgInfo classifyReturnType(QualType RetTy, 559 unsigned callingConvention) const; 560 ABIArgInfo classifyArgumentType(QualType RetTy, unsigned &FreeRegs, 561 bool IsFastCall) const; 562 bool shouldUseInReg(QualType Ty, unsigned &FreeRegs, 563 bool IsFastCall, bool &NeedsPadding) const; 564 565public: 566 567 virtual void computeInfo(CGFunctionInfo &FI) const; 568 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 569 CodeGenFunction &CGF) const; 570 571 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w, 572 unsigned r) 573 : ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p), 574 IsWin32StructABI(w), DefaultNumRegisterParameters(r) {} 575}; 576 577class X86_32TargetCodeGenInfo : public TargetCodeGenInfo { 578public: 579 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, 580 bool d, bool p, bool w, unsigned r) 581 :TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {} 582 583 static bool isStructReturnInRegABI( 584 const llvm::Triple &Triple, const CodeGenOptions &Opts); 585 586 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 587 CodeGen::CodeGenModule &CGM) const; 588 589 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 590 // Darwin uses different dwarf register numbers for EH. 591 if (CGM.getTarget().getTriple().isOSDarwin()) return 5; 592 return 4; 593 } 594 595 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 596 llvm::Value *Address) const; 597 598 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 599 StringRef Constraint, 600 llvm::Type* Ty) const { 601 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 602 } 603 604}; 605 606} 607 608/// shouldReturnTypeInRegister - Determine if the given type should be 609/// passed in a register (for the Darwin ABI). 610bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty, 611 ASTContext &Context, 612 unsigned callingConvention) { 613 uint64_t Size = Context.getTypeSize(Ty); 614 615 // Type must be register sized. 616 if (!isRegisterSize(Size)) 617 return false; 618 619 if (Ty->isVectorType()) { 620 // 64- and 128- bit vectors inside structures are not returned in 621 // registers. 622 if (Size == 64 || Size == 128) 623 return false; 624 625 return true; 626 } 627 628 // If this is a builtin, pointer, enum, complex type, member pointer, or 629 // member function pointer it is ok. 630 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() || 631 Ty->isAnyComplexType() || Ty->isEnumeralType() || 632 Ty->isBlockPointerType() || Ty->isMemberPointerType()) 633 return true; 634 635 // Arrays are treated like records. 636 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) 637 return shouldReturnTypeInRegister(AT->getElementType(), Context, 638 callingConvention); 639 640 // Otherwise, it must be a record type. 641 const RecordType *RT = Ty->getAs<RecordType>(); 642 if (!RT) return false; 643 644 // FIXME: Traverse bases here too. 645 646 // For thiscall conventions, structures will never be returned in 647 // a register. This is for compatibility with the MSVC ABI 648 if (callingConvention == llvm::CallingConv::X86_ThisCall && 649 RT->isStructureType()) { 650 return false; 651 } 652 653 // Structure types are passed in register if all fields would be 654 // passed in a register. 655 for (RecordDecl::field_iterator i = RT->getDecl()->field_begin(), 656 e = RT->getDecl()->field_end(); i != e; ++i) { 657 const FieldDecl *FD = *i; 658 659 // Empty fields are ignored. 660 if (isEmptyField(Context, FD, true)) 661 continue; 662 663 // Check fields recursively. 664 if (!shouldReturnTypeInRegister(FD->getType(), Context, 665 callingConvention)) 666 return false; 667 } 668 return true; 669} 670 671ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy, 672 unsigned callingConvention) const { 673 if (RetTy->isVoidType()) 674 return ABIArgInfo::getIgnore(); 675 676 if (const VectorType *VT = RetTy->getAs<VectorType>()) { 677 // On Darwin, some vectors are returned in registers. 678 if (IsDarwinVectorABI) { 679 uint64_t Size = getContext().getTypeSize(RetTy); 680 681 // 128-bit vectors are a special case; they are returned in 682 // registers and we need to make sure to pick a type the LLVM 683 // backend will like. 684 if (Size == 128) 685 return ABIArgInfo::getDirect(llvm::VectorType::get( 686 llvm::Type::getInt64Ty(getVMContext()), 2)); 687 688 // Always return in register if it fits in a general purpose 689 // register, or if it is 64 bits and has a single element. 690 if ((Size == 8 || Size == 16 || Size == 32) || 691 (Size == 64 && VT->getNumElements() == 1)) 692 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 693 Size)); 694 695 return ABIArgInfo::getIndirect(0); 696 } 697 698 return ABIArgInfo::getDirect(); 699 } 700 701 if (isAggregateTypeForABI(RetTy)) { 702 if (const RecordType *RT = RetTy->getAs<RecordType>()) { 703 if (isRecordReturnIndirect(RT, getCXXABI())) 704 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 705 706 // Structures with flexible arrays are always indirect. 707 if (RT->getDecl()->hasFlexibleArrayMember()) 708 return ABIArgInfo::getIndirect(0); 709 } 710 711 // If specified, structs and unions are always indirect. 712 if (!IsSmallStructInRegABI && !RetTy->isAnyComplexType()) 713 return ABIArgInfo::getIndirect(0); 714 715 // Small structures which are register sized are generally returned 716 // in a register. 717 if (X86_32ABIInfo::shouldReturnTypeInRegister(RetTy, getContext(), 718 callingConvention)) { 719 uint64_t Size = getContext().getTypeSize(RetTy); 720 721 // As a special-case, if the struct is a "single-element" struct, and 722 // the field is of type "float" or "double", return it in a 723 // floating-point register. (MSVC does not apply this special case.) 724 // We apply a similar transformation for pointer types to improve the 725 // quality of the generated IR. 726 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) 727 if ((!IsWin32StructABI && SeltTy->isRealFloatingType()) 728 || SeltTy->hasPointerRepresentation()) 729 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 730 731 // FIXME: We should be able to narrow this integer in cases with dead 732 // padding. 733 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size)); 734 } 735 736 return ABIArgInfo::getIndirect(0); 737 } 738 739 // Treat an enum type as its underlying type. 740 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 741 RetTy = EnumTy->getDecl()->getIntegerType(); 742 743 return (RetTy->isPromotableIntegerType() ? 744 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 745} 746 747static bool isSSEVectorType(ASTContext &Context, QualType Ty) { 748 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128; 749} 750 751static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) { 752 const RecordType *RT = Ty->getAs<RecordType>(); 753 if (!RT) 754 return 0; 755 const RecordDecl *RD = RT->getDecl(); 756 757 // If this is a C++ record, check the bases first. 758 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 759 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 760 e = CXXRD->bases_end(); i != e; ++i) 761 if (!isRecordWithSSEVectorType(Context, i->getType())) 762 return false; 763 764 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 765 i != e; ++i) { 766 QualType FT = i->getType(); 767 768 if (isSSEVectorType(Context, FT)) 769 return true; 770 771 if (isRecordWithSSEVectorType(Context, FT)) 772 return true; 773 } 774 775 return false; 776} 777 778unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty, 779 unsigned Align) const { 780 // Otherwise, if the alignment is less than or equal to the minimum ABI 781 // alignment, just use the default; the backend will handle this. 782 if (Align <= MinABIStackAlignInBytes) 783 return 0; // Use default alignment. 784 785 // On non-Darwin, the stack type alignment is always 4. 786 if (!IsDarwinVectorABI) { 787 // Set explicit alignment, since we may need to realign the top. 788 return MinABIStackAlignInBytes; 789 } 790 791 // Otherwise, if the type contains an SSE vector type, the alignment is 16. 792 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) || 793 isRecordWithSSEVectorType(getContext(), Ty))) 794 return 16; 795 796 return MinABIStackAlignInBytes; 797} 798 799ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal, 800 unsigned &FreeRegs) const { 801 if (!ByVal) { 802 if (FreeRegs) { 803 --FreeRegs; // Non byval indirects just use one pointer. 804 return ABIArgInfo::getIndirectInReg(0, false); 805 } 806 return ABIArgInfo::getIndirect(0, false); 807 } 808 809 // Compute the byval alignment. 810 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; 811 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign); 812 if (StackAlign == 0) 813 return ABIArgInfo::getIndirect(4); 814 815 // If the stack alignment is less than the type alignment, realign the 816 // argument. 817 if (StackAlign < TypeAlign) 818 return ABIArgInfo::getIndirect(StackAlign, /*ByVal=*/true, 819 /*Realign=*/true); 820 821 return ABIArgInfo::getIndirect(StackAlign); 822} 823 824X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const { 825 const Type *T = isSingleElementStruct(Ty, getContext()); 826 if (!T) 827 T = Ty.getTypePtr(); 828 829 if (const BuiltinType *BT = T->getAs<BuiltinType>()) { 830 BuiltinType::Kind K = BT->getKind(); 831 if (K == BuiltinType::Float || K == BuiltinType::Double) 832 return Float; 833 } 834 return Integer; 835} 836 837bool X86_32ABIInfo::shouldUseInReg(QualType Ty, unsigned &FreeRegs, 838 bool IsFastCall, bool &NeedsPadding) const { 839 NeedsPadding = false; 840 Class C = classify(Ty); 841 if (C == Float) 842 return false; 843 844 unsigned Size = getContext().getTypeSize(Ty); 845 unsigned SizeInRegs = (Size + 31) / 32; 846 847 if (SizeInRegs == 0) 848 return false; 849 850 if (SizeInRegs > FreeRegs) { 851 FreeRegs = 0; 852 return false; 853 } 854 855 FreeRegs -= SizeInRegs; 856 857 if (IsFastCall) { 858 if (Size > 32) 859 return false; 860 861 if (Ty->isIntegralOrEnumerationType()) 862 return true; 863 864 if (Ty->isPointerType()) 865 return true; 866 867 if (Ty->isReferenceType()) 868 return true; 869 870 if (FreeRegs) 871 NeedsPadding = true; 872 873 return false; 874 } 875 876 return true; 877} 878 879ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, 880 unsigned &FreeRegs, 881 bool IsFastCall) const { 882 // FIXME: Set alignment on indirect arguments. 883 if (isAggregateTypeForABI(Ty)) { 884 if (const RecordType *RT = Ty->getAs<RecordType>()) { 885 if (IsWin32StructABI) 886 return getIndirectResult(Ty, true, FreeRegs); 887 888 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI())) 889 return getIndirectResult(Ty, RAA == CGCXXABI::RAA_DirectInMemory, FreeRegs); 890 891 // Structures with flexible arrays are always indirect. 892 if (RT->getDecl()->hasFlexibleArrayMember()) 893 return getIndirectResult(Ty, true, FreeRegs); 894 } 895 896 // Ignore empty structs/unions. 897 if (isEmptyRecord(getContext(), Ty, true)) 898 return ABIArgInfo::getIgnore(); 899 900 llvm::LLVMContext &LLVMContext = getVMContext(); 901 llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext); 902 bool NeedsPadding; 903 if (shouldUseInReg(Ty, FreeRegs, IsFastCall, NeedsPadding)) { 904 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 905 SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32); 906 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); 907 return ABIArgInfo::getDirectInReg(Result); 908 } 909 llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : 0; 910 911 // Expand small (<= 128-bit) record types when we know that the stack layout 912 // of those arguments will match the struct. This is important because the 913 // LLVM backend isn't smart enough to remove byval, which inhibits many 914 // optimizations. 915 if (getContext().getTypeSize(Ty) <= 4*32 && 916 canExpandIndirectArgument(Ty, getContext())) 917 return ABIArgInfo::getExpandWithPadding(IsFastCall, PaddingType); 918 919 return getIndirectResult(Ty, true, FreeRegs); 920 } 921 922 if (const VectorType *VT = Ty->getAs<VectorType>()) { 923 // On Darwin, some vectors are passed in memory, we handle this by passing 924 // it as an i8/i16/i32/i64. 925 if (IsDarwinVectorABI) { 926 uint64_t Size = getContext().getTypeSize(Ty); 927 if ((Size == 8 || Size == 16 || Size == 32) || 928 (Size == 64 && VT->getNumElements() == 1)) 929 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 930 Size)); 931 } 932 933 if (IsX86_MMXType(CGT.ConvertType(Ty))) 934 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64)); 935 936 return ABIArgInfo::getDirect(); 937 } 938 939 940 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 941 Ty = EnumTy->getDecl()->getIntegerType(); 942 943 bool NeedsPadding; 944 bool InReg = shouldUseInReg(Ty, FreeRegs, IsFastCall, NeedsPadding); 945 946 if (Ty->isPromotableIntegerType()) { 947 if (InReg) 948 return ABIArgInfo::getExtendInReg(); 949 return ABIArgInfo::getExtend(); 950 } 951 if (InReg) 952 return ABIArgInfo::getDirectInReg(); 953 return ABIArgInfo::getDirect(); 954} 955 956void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { 957 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), 958 FI.getCallingConvention()); 959 960 unsigned CC = FI.getCallingConvention(); 961 bool IsFastCall = CC == llvm::CallingConv::X86_FastCall; 962 unsigned FreeRegs; 963 if (IsFastCall) 964 FreeRegs = 2; 965 else if (FI.getHasRegParm()) 966 FreeRegs = FI.getRegParm(); 967 else 968 FreeRegs = DefaultNumRegisterParameters; 969 970 // If the return value is indirect, then the hidden argument is consuming one 971 // integer register. 972 if (FI.getReturnInfo().isIndirect() && FreeRegs) { 973 --FreeRegs; 974 ABIArgInfo &Old = FI.getReturnInfo(); 975 Old = ABIArgInfo::getIndirectInReg(Old.getIndirectAlign(), 976 Old.getIndirectByVal(), 977 Old.getIndirectRealign()); 978 } 979 980 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 981 it != ie; ++it) 982 it->info = classifyArgumentType(it->type, FreeRegs, IsFastCall); 983} 984 985llvm::Value *X86_32ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 986 CodeGenFunction &CGF) const { 987 llvm::Type *BPP = CGF.Int8PtrPtrTy; 988 989 CGBuilderTy &Builder = CGF.Builder; 990 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 991 "ap"); 992 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 993 994 // Compute if the address needs to be aligned 995 unsigned Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); 996 Align = getTypeStackAlignInBytes(Ty, Align); 997 Align = std::max(Align, 4U); 998 if (Align > 4) { 999 // addr = (addr + align - 1) & -align; 1000 llvm::Value *Offset = 1001 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1); 1002 Addr = CGF.Builder.CreateGEP(Addr, Offset); 1003 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(Addr, 1004 CGF.Int32Ty); 1005 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align); 1006 Addr = CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 1007 Addr->getType(), 1008 "ap.cur.aligned"); 1009 } 1010 1011 llvm::Type *PTy = 1012 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 1013 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 1014 1015 uint64_t Offset = 1016 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, Align); 1017 llvm::Value *NextAddr = 1018 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 1019 "ap.next"); 1020 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 1021 1022 return AddrTyped; 1023} 1024 1025void X86_32TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 1026 llvm::GlobalValue *GV, 1027 CodeGen::CodeGenModule &CGM) const { 1028 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 1029 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { 1030 // Get the LLVM function. 1031 llvm::Function *Fn = cast<llvm::Function>(GV); 1032 1033 // Now add the 'alignstack' attribute with a value of 16. 1034 llvm::AttrBuilder B; 1035 B.addStackAlignmentAttr(16); 1036 Fn->addAttributes(llvm::AttributeSet::FunctionIndex, 1037 llvm::AttributeSet::get(CGM.getLLVMContext(), 1038 llvm::AttributeSet::FunctionIndex, 1039 B)); 1040 } 1041 } 1042} 1043 1044bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable( 1045 CodeGen::CodeGenFunction &CGF, 1046 llvm::Value *Address) const { 1047 CodeGen::CGBuilderTy &Builder = CGF.Builder; 1048 1049 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 1050 1051 // 0-7 are the eight integer registers; the order is different 1052 // on Darwin (for EH), but the range is the same. 1053 // 8 is %eip. 1054 AssignToArrayRange(Builder, Address, Four8, 0, 8); 1055 1056 if (CGF.CGM.getTarget().getTriple().isOSDarwin()) { 1057 // 12-16 are st(0..4). Not sure why we stop at 4. 1058 // These have size 16, which is sizeof(long double) on 1059 // platforms with 8-byte alignment for that type. 1060 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 1061 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16); 1062 1063 } else { 1064 // 9 is %eflags, which doesn't get a size on Darwin for some 1065 // reason. 1066 Builder.CreateStore(Four8, Builder.CreateConstInBoundsGEP1_32(Address, 9)); 1067 1068 // 11-16 are st(0..5). Not sure why we stop at 5. 1069 // These have size 12, which is sizeof(long double) on 1070 // platforms with 4-byte alignment for that type. 1071 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12); 1072 AssignToArrayRange(Builder, Address, Twelve8, 11, 16); 1073 } 1074 1075 return false; 1076} 1077 1078//===----------------------------------------------------------------------===// 1079// X86-64 ABI Implementation 1080//===----------------------------------------------------------------------===// 1081 1082 1083namespace { 1084/// X86_64ABIInfo - The X86_64 ABI information. 1085class X86_64ABIInfo : public ABIInfo { 1086 enum Class { 1087 Integer = 0, 1088 SSE, 1089 SSEUp, 1090 X87, 1091 X87Up, 1092 ComplexX87, 1093 NoClass, 1094 Memory 1095 }; 1096 1097 /// merge - Implement the X86_64 ABI merging algorithm. 1098 /// 1099 /// Merge an accumulating classification \arg Accum with a field 1100 /// classification \arg Field. 1101 /// 1102 /// \param Accum - The accumulating classification. This should 1103 /// always be either NoClass or the result of a previous merge 1104 /// call. In addition, this should never be Memory (the caller 1105 /// should just return Memory for the aggregate). 1106 static Class merge(Class Accum, Class Field); 1107 1108 /// postMerge - Implement the X86_64 ABI post merging algorithm. 1109 /// 1110 /// Post merger cleanup, reduces a malformed Hi and Lo pair to 1111 /// final MEMORY or SSE classes when necessary. 1112 /// 1113 /// \param AggregateSize - The size of the current aggregate in 1114 /// the classification process. 1115 /// 1116 /// \param Lo - The classification for the parts of the type 1117 /// residing in the low word of the containing object. 1118 /// 1119 /// \param Hi - The classification for the parts of the type 1120 /// residing in the higher words of the containing object. 1121 /// 1122 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 1123 1124 /// classify - Determine the x86_64 register classes in which the 1125 /// given type T should be passed. 1126 /// 1127 /// \param Lo - The classification for the parts of the type 1128 /// residing in the low word of the containing object. 1129 /// 1130 /// \param Hi - The classification for the parts of the type 1131 /// residing in the high word of the containing object. 1132 /// 1133 /// \param OffsetBase - The bit offset of this type in the 1134 /// containing object. Some parameters are classified different 1135 /// depending on whether they straddle an eightbyte boundary. 1136 /// 1137 /// \param isNamedArg - Whether the argument in question is a "named" 1138 /// argument, as used in AMD64-ABI 3.5.7. 1139 /// 1140 /// If a word is unused its result will be NoClass; if a type should 1141 /// be passed in Memory then at least the classification of \arg Lo 1142 /// will be Memory. 1143 /// 1144 /// The \arg Lo class will be NoClass iff the argument is ignored. 1145 /// 1146 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 1147 /// also be ComplexX87. 1148 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi, 1149 bool isNamedArg) const; 1150 1151 llvm::Type *GetByteVectorType(QualType Ty) const; 1152 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType, 1153 unsigned IROffset, QualType SourceTy, 1154 unsigned SourceOffset) const; 1155 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType, 1156 unsigned IROffset, QualType SourceTy, 1157 unsigned SourceOffset) const; 1158 1159 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1160 /// such that the argument will be returned in memory. 1161 ABIArgInfo getIndirectReturnResult(QualType Ty) const; 1162 1163 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1164 /// such that the argument will be passed in memory. 1165 /// 1166 /// \param freeIntRegs - The number of free integer registers remaining 1167 /// available. 1168 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const; 1169 1170 ABIArgInfo classifyReturnType(QualType RetTy) const; 1171 1172 ABIArgInfo classifyArgumentType(QualType Ty, 1173 unsigned freeIntRegs, 1174 unsigned &neededInt, 1175 unsigned &neededSSE, 1176 bool isNamedArg) const; 1177 1178 bool IsIllegalVectorType(QualType Ty) const; 1179 1180 /// The 0.98 ABI revision clarified a lot of ambiguities, 1181 /// unfortunately in ways that were not always consistent with 1182 /// certain previous compilers. In particular, platforms which 1183 /// required strict binary compatibility with older versions of GCC 1184 /// may need to exempt themselves. 1185 bool honorsRevision0_98() const { 1186 return !getTarget().getTriple().isOSDarwin(); 1187 } 1188 1189 bool HasAVX; 1190 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on 1191 // 64-bit hardware. 1192 bool Has64BitPointers; 1193 1194public: 1195 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool hasavx) : 1196 ABIInfo(CGT), HasAVX(hasavx), 1197 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) { 1198 } 1199 1200 bool isPassedUsingAVXType(QualType type) const { 1201 unsigned neededInt, neededSSE; 1202 // The freeIntRegs argument doesn't matter here. 1203 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE, 1204 /*isNamedArg*/true); 1205 if (info.isDirect()) { 1206 llvm::Type *ty = info.getCoerceToType(); 1207 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty)) 1208 return (vectorTy->getBitWidth() > 128); 1209 } 1210 return false; 1211 } 1212 1213 virtual void computeInfo(CGFunctionInfo &FI) const; 1214 1215 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1216 CodeGenFunction &CGF) const; 1217}; 1218 1219/// WinX86_64ABIInfo - The Windows X86_64 ABI information. 1220class WinX86_64ABIInfo : public ABIInfo { 1221 1222 ABIArgInfo classify(QualType Ty, bool IsReturnType) const; 1223 1224public: 1225 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 1226 1227 virtual void computeInfo(CGFunctionInfo &FI) const; 1228 1229 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1230 CodeGenFunction &CGF) const; 1231}; 1232 1233class X86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1234public: 1235 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 1236 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, HasAVX)) {} 1237 1238 const X86_64ABIInfo &getABIInfo() const { 1239 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 1240 } 1241 1242 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1243 return 7; 1244 } 1245 1246 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1247 llvm::Value *Address) const { 1248 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1249 1250 // 0-15 are the 16 integer registers. 1251 // 16 is %rip. 1252 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1253 return false; 1254 } 1255 1256 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 1257 StringRef Constraint, 1258 llvm::Type* Ty) const { 1259 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 1260 } 1261 1262 bool isNoProtoCallVariadic(const CallArgList &args, 1263 const FunctionNoProtoType *fnType) const { 1264 // The default CC on x86-64 sets %al to the number of SSA 1265 // registers used, and GCC sets this when calling an unprototyped 1266 // function, so we override the default behavior. However, don't do 1267 // that when AVX types are involved: the ABI explicitly states it is 1268 // undefined, and it doesn't work in practice because of how the ABI 1269 // defines varargs anyway. 1270 if (fnType->getCallConv() == CC_C) { 1271 bool HasAVXType = false; 1272 for (CallArgList::const_iterator 1273 it = args.begin(), ie = args.end(); it != ie; ++it) { 1274 if (getABIInfo().isPassedUsingAVXType(it->Ty)) { 1275 HasAVXType = true; 1276 break; 1277 } 1278 } 1279 1280 if (!HasAVXType) 1281 return true; 1282 } 1283 1284 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType); 1285 } 1286 1287}; 1288 1289static std::string qualifyWindowsLibrary(llvm::StringRef Lib) { 1290 // If the argument does not end in .lib, automatically add the suffix. This 1291 // matches the behavior of MSVC. 1292 std::string ArgStr = Lib; 1293 if (Lib.size() <= 4 || 1294 Lib.substr(Lib.size() - 4).compare_lower(".lib") != 0) { 1295 ArgStr += ".lib"; 1296 } 1297 return ArgStr; 1298} 1299 1300class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo { 1301public: 1302 WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, 1303 bool d, bool p, bool w, unsigned RegParms) 1304 : X86_32TargetCodeGenInfo(CGT, d, p, w, RegParms) {} 1305 1306 void getDependentLibraryOption(llvm::StringRef Lib, 1307 llvm::SmallString<24> &Opt) const { 1308 Opt = "/DEFAULTLIB:"; 1309 Opt += qualifyWindowsLibrary(Lib); 1310 } 1311 1312 void getDetectMismatchOption(llvm::StringRef Name, 1313 llvm::StringRef Value, 1314 llvm::SmallString<32> &Opt) const { 1315 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; 1316 } 1317}; 1318 1319class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1320public: 1321 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 1322 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {} 1323 1324 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1325 return 7; 1326 } 1327 1328 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1329 llvm::Value *Address) const { 1330 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1331 1332 // 0-15 are the 16 integer registers. 1333 // 16 is %rip. 1334 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1335 return false; 1336 } 1337 1338 void getDependentLibraryOption(llvm::StringRef Lib, 1339 llvm::SmallString<24> &Opt) const { 1340 Opt = "/DEFAULTLIB:"; 1341 Opt += qualifyWindowsLibrary(Lib); 1342 } 1343 1344 void getDetectMismatchOption(llvm::StringRef Name, 1345 llvm::StringRef Value, 1346 llvm::SmallString<32> &Opt) const { 1347 Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; 1348 } 1349}; 1350 1351} 1352 1353void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, 1354 Class &Hi) const { 1355 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done: 1356 // 1357 // (a) If one of the classes is Memory, the whole argument is passed in 1358 // memory. 1359 // 1360 // (b) If X87UP is not preceded by X87, the whole argument is passed in 1361 // memory. 1362 // 1363 // (c) If the size of the aggregate exceeds two eightbytes and the first 1364 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole 1365 // argument is passed in memory. NOTE: This is necessary to keep the 1366 // ABI working for processors that don't support the __m256 type. 1367 // 1368 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE. 1369 // 1370 // Some of these are enforced by the merging logic. Others can arise 1371 // only with unions; for example: 1372 // union { _Complex double; unsigned; } 1373 // 1374 // Note that clauses (b) and (c) were added in 0.98. 1375 // 1376 if (Hi == Memory) 1377 Lo = Memory; 1378 if (Hi == X87Up && Lo != X87 && honorsRevision0_98()) 1379 Lo = Memory; 1380 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) 1381 Lo = Memory; 1382 if (Hi == SSEUp && Lo != SSE) 1383 Hi = SSE; 1384} 1385 1386X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) { 1387 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is 1388 // classified recursively so that always two fields are 1389 // considered. The resulting class is calculated according to 1390 // the classes of the fields in the eightbyte: 1391 // 1392 // (a) If both classes are equal, this is the resulting class. 1393 // 1394 // (b) If one of the classes is NO_CLASS, the resulting class is 1395 // the other class. 1396 // 1397 // (c) If one of the classes is MEMORY, the result is the MEMORY 1398 // class. 1399 // 1400 // (d) If one of the classes is INTEGER, the result is the 1401 // INTEGER. 1402 // 1403 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class, 1404 // MEMORY is used as class. 1405 // 1406 // (f) Otherwise class SSE is used. 1407 1408 // Accum should never be memory (we should have returned) or 1409 // ComplexX87 (because this cannot be passed in a structure). 1410 assert((Accum != Memory && Accum != ComplexX87) && 1411 "Invalid accumulated classification during merge."); 1412 if (Accum == Field || Field == NoClass) 1413 return Accum; 1414 if (Field == Memory) 1415 return Memory; 1416 if (Accum == NoClass) 1417 return Field; 1418 if (Accum == Integer || Field == Integer) 1419 return Integer; 1420 if (Field == X87 || Field == X87Up || Field == ComplexX87 || 1421 Accum == X87 || Accum == X87Up) 1422 return Memory; 1423 return SSE; 1424} 1425 1426void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, 1427 Class &Lo, Class &Hi, bool isNamedArg) const { 1428 // FIXME: This code can be simplified by introducing a simple value class for 1429 // Class pairs with appropriate constructor methods for the various 1430 // situations. 1431 1432 // FIXME: Some of the split computations are wrong; unaligned vectors 1433 // shouldn't be passed in registers for example, so there is no chance they 1434 // can straddle an eightbyte. Verify & simplify. 1435 1436 Lo = Hi = NoClass; 1437 1438 Class &Current = OffsetBase < 64 ? Lo : Hi; 1439 Current = Memory; 1440 1441 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 1442 BuiltinType::Kind k = BT->getKind(); 1443 1444 if (k == BuiltinType::Void) { 1445 Current = NoClass; 1446 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) { 1447 Lo = Integer; 1448 Hi = Integer; 1449 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) { 1450 Current = Integer; 1451 } else if ((k == BuiltinType::Float || k == BuiltinType::Double) || 1452 (k == BuiltinType::LongDouble && 1453 getTarget().getTriple().isOSNaCl())) { 1454 Current = SSE; 1455 } else if (k == BuiltinType::LongDouble) { 1456 Lo = X87; 1457 Hi = X87Up; 1458 } 1459 // FIXME: _Decimal32 and _Decimal64 are SSE. 1460 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp). 1461 return; 1462 } 1463 1464 if (const EnumType *ET = Ty->getAs<EnumType>()) { 1465 // Classify the underlying integer type. 1466 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg); 1467 return; 1468 } 1469 1470 if (Ty->hasPointerRepresentation()) { 1471 Current = Integer; 1472 return; 1473 } 1474 1475 if (Ty->isMemberPointerType()) { 1476 if (Ty->isMemberFunctionPointerType() && Has64BitPointers) 1477 Lo = Hi = Integer; 1478 else 1479 Current = Integer; 1480 return; 1481 } 1482 1483 if (const VectorType *VT = Ty->getAs<VectorType>()) { 1484 uint64_t Size = getContext().getTypeSize(VT); 1485 if (Size == 32) { 1486 // gcc passes all <4 x char>, <2 x short>, <1 x int>, <1 x 1487 // float> as integer. 1488 Current = Integer; 1489 1490 // If this type crosses an eightbyte boundary, it should be 1491 // split. 1492 uint64_t EB_Real = (OffsetBase) / 64; 1493 uint64_t EB_Imag = (OffsetBase + Size - 1) / 64; 1494 if (EB_Real != EB_Imag) 1495 Hi = Lo; 1496 } else if (Size == 64) { 1497 // gcc passes <1 x double> in memory. :( 1498 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) 1499 return; 1500 1501 // gcc passes <1 x long long> as INTEGER. 1502 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::LongLong) || 1503 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULongLong) || 1504 VT->getElementType()->isSpecificBuiltinType(BuiltinType::Long) || 1505 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULong)) 1506 Current = Integer; 1507 else 1508 Current = SSE; 1509 1510 // If this type crosses an eightbyte boundary, it should be 1511 // split. 1512 if (OffsetBase && OffsetBase != 64) 1513 Hi = Lo; 1514 } else if (Size == 128 || (HasAVX && isNamedArg && Size == 256)) { 1515 // Arguments of 256-bits are split into four eightbyte chunks. The 1516 // least significant one belongs to class SSE and all the others to class 1517 // SSEUP. The original Lo and Hi design considers that types can't be 1518 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense. 1519 // This design isn't correct for 256-bits, but since there're no cases 1520 // where the upper parts would need to be inspected, avoid adding 1521 // complexity and just consider Hi to match the 64-256 part. 1522 // 1523 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in 1524 // registers if they are "named", i.e. not part of the "..." of a 1525 // variadic function. 1526 Lo = SSE; 1527 Hi = SSEUp; 1528 } 1529 return; 1530 } 1531 1532 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 1533 QualType ET = getContext().getCanonicalType(CT->getElementType()); 1534 1535 uint64_t Size = getContext().getTypeSize(Ty); 1536 if (ET->isIntegralOrEnumerationType()) { 1537 if (Size <= 64) 1538 Current = Integer; 1539 else if (Size <= 128) 1540 Lo = Hi = Integer; 1541 } else if (ET == getContext().FloatTy) 1542 Current = SSE; 1543 else if (ET == getContext().DoubleTy || 1544 (ET == getContext().LongDoubleTy && 1545 getTarget().getTriple().isOSNaCl())) 1546 Lo = Hi = SSE; 1547 else if (ET == getContext().LongDoubleTy) 1548 Current = ComplexX87; 1549 1550 // If this complex type crosses an eightbyte boundary then it 1551 // should be split. 1552 uint64_t EB_Real = (OffsetBase) / 64; 1553 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64; 1554 if (Hi == NoClass && EB_Real != EB_Imag) 1555 Hi = Lo; 1556 1557 return; 1558 } 1559 1560 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) { 1561 // Arrays are treated like structures. 1562 1563 uint64_t Size = getContext().getTypeSize(Ty); 1564 1565 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1566 // than four eightbytes, ..., it has class MEMORY. 1567 if (Size > 256) 1568 return; 1569 1570 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned 1571 // fields, it has class MEMORY. 1572 // 1573 // Only need to check alignment of array base. 1574 if (OffsetBase % getContext().getTypeAlign(AT->getElementType())) 1575 return; 1576 1577 // Otherwise implement simplified merge. We could be smarter about 1578 // this, but it isn't worth it and would be harder to verify. 1579 Current = NoClass; 1580 uint64_t EltSize = getContext().getTypeSize(AT->getElementType()); 1581 uint64_t ArraySize = AT->getSize().getZExtValue(); 1582 1583 // The only case a 256-bit wide vector could be used is when the array 1584 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1585 // to work for sizes wider than 128, early check and fallback to memory. 1586 if (Size > 128 && EltSize != 256) 1587 return; 1588 1589 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) { 1590 Class FieldLo, FieldHi; 1591 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg); 1592 Lo = merge(Lo, FieldLo); 1593 Hi = merge(Hi, FieldHi); 1594 if (Lo == Memory || Hi == Memory) 1595 break; 1596 } 1597 1598 postMerge(Size, Lo, Hi); 1599 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification."); 1600 return; 1601 } 1602 1603 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1604 uint64_t Size = getContext().getTypeSize(Ty); 1605 1606 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1607 // than four eightbytes, ..., it has class MEMORY. 1608 if (Size > 256) 1609 return; 1610 1611 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial 1612 // copy constructor or a non-trivial destructor, it is passed by invisible 1613 // reference. 1614 if (getRecordArgABI(RT, getCXXABI())) 1615 return; 1616 1617 const RecordDecl *RD = RT->getDecl(); 1618 1619 // Assume variable sized types are passed in memory. 1620 if (RD->hasFlexibleArrayMember()) 1621 return; 1622 1623 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 1624 1625 // Reset Lo class, this will be recomputed. 1626 Current = NoClass; 1627 1628 // If this is a C++ record, classify the bases first. 1629 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1630 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1631 e = CXXRD->bases_end(); i != e; ++i) { 1632 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1633 "Unexpected base class!"); 1634 const CXXRecordDecl *Base = 1635 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1636 1637 // Classify this field. 1638 // 1639 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a 1640 // single eightbyte, each is classified separately. Each eightbyte gets 1641 // initialized to class NO_CLASS. 1642 Class FieldLo, FieldHi; 1643 uint64_t Offset = 1644 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base)); 1645 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg); 1646 Lo = merge(Lo, FieldLo); 1647 Hi = merge(Hi, FieldHi); 1648 if (Lo == Memory || Hi == Memory) 1649 break; 1650 } 1651 } 1652 1653 // Classify the fields one at a time, merging the results. 1654 unsigned idx = 0; 1655 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1656 i != e; ++i, ++idx) { 1657 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1658 bool BitField = i->isBitField(); 1659 1660 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than 1661 // four eightbytes, or it contains unaligned fields, it has class MEMORY. 1662 // 1663 // The only case a 256-bit wide vector could be used is when the struct 1664 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1665 // to work for sizes wider than 128, early check and fallback to memory. 1666 // 1667 if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) { 1668 Lo = Memory; 1669 return; 1670 } 1671 // Note, skip this test for bit-fields, see below. 1672 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) { 1673 Lo = Memory; 1674 return; 1675 } 1676 1677 // Classify this field. 1678 // 1679 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate 1680 // exceeds a single eightbyte, each is classified 1681 // separately. Each eightbyte gets initialized to class 1682 // NO_CLASS. 1683 Class FieldLo, FieldHi; 1684 1685 // Bit-fields require special handling, they do not force the 1686 // structure to be passed in memory even if unaligned, and 1687 // therefore they can straddle an eightbyte. 1688 if (BitField) { 1689 // Ignore padding bit-fields. 1690 if (i->isUnnamedBitfield()) 1691 continue; 1692 1693 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1694 uint64_t Size = i->getBitWidthValue(getContext()); 1695 1696 uint64_t EB_Lo = Offset / 64; 1697 uint64_t EB_Hi = (Offset + Size - 1) / 64; 1698 FieldLo = FieldHi = NoClass; 1699 if (EB_Lo) { 1700 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes."); 1701 FieldLo = NoClass; 1702 FieldHi = Integer; 1703 } else { 1704 FieldLo = Integer; 1705 FieldHi = EB_Hi ? Integer : NoClass; 1706 } 1707 } else 1708 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg); 1709 Lo = merge(Lo, FieldLo); 1710 Hi = merge(Hi, FieldHi); 1711 if (Lo == Memory || Hi == Memory) 1712 break; 1713 } 1714 1715 postMerge(Size, Lo, Hi); 1716 } 1717} 1718 1719ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const { 1720 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1721 // place naturally. 1722 if (!isAggregateTypeForABI(Ty)) { 1723 // Treat an enum type as its underlying type. 1724 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1725 Ty = EnumTy->getDecl()->getIntegerType(); 1726 1727 return (Ty->isPromotableIntegerType() ? 1728 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1729 } 1730 1731 return ABIArgInfo::getIndirect(0); 1732} 1733 1734bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const { 1735 if (const VectorType *VecTy = Ty->getAs<VectorType>()) { 1736 uint64_t Size = getContext().getTypeSize(VecTy); 1737 unsigned LargestVector = HasAVX ? 256 : 128; 1738 if (Size <= 64 || Size > LargestVector) 1739 return true; 1740 } 1741 1742 return false; 1743} 1744 1745ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty, 1746 unsigned freeIntRegs) const { 1747 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1748 // place naturally. 1749 // 1750 // This assumption is optimistic, as there could be free registers available 1751 // when we need to pass this argument in memory, and LLVM could try to pass 1752 // the argument in the free register. This does not seem to happen currently, 1753 // but this code would be much safer if we could mark the argument with 1754 // 'onstack'. See PR12193. 1755 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) { 1756 // Treat an enum type as its underlying type. 1757 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1758 Ty = EnumTy->getDecl()->getIntegerType(); 1759 1760 return (Ty->isPromotableIntegerType() ? 1761 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1762 } 1763 1764 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 1765 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 1766 1767 // Compute the byval alignment. We specify the alignment of the byval in all 1768 // cases so that the mid-level optimizer knows the alignment of the byval. 1769 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U); 1770 1771 // Attempt to avoid passing indirect results using byval when possible. This 1772 // is important for good codegen. 1773 // 1774 // We do this by coercing the value into a scalar type which the backend can 1775 // handle naturally (i.e., without using byval). 1776 // 1777 // For simplicity, we currently only do this when we have exhausted all of the 1778 // free integer registers. Doing this when there are free integer registers 1779 // would require more care, as we would have to ensure that the coerced value 1780 // did not claim the unused register. That would require either reording the 1781 // arguments to the function (so that any subsequent inreg values came first), 1782 // or only doing this optimization when there were no following arguments that 1783 // might be inreg. 1784 // 1785 // We currently expect it to be rare (particularly in well written code) for 1786 // arguments to be passed on the stack when there are still free integer 1787 // registers available (this would typically imply large structs being passed 1788 // by value), so this seems like a fair tradeoff for now. 1789 // 1790 // We can revisit this if the backend grows support for 'onstack' parameter 1791 // attributes. See PR12193. 1792 if (freeIntRegs == 0) { 1793 uint64_t Size = getContext().getTypeSize(Ty); 1794 1795 // If this type fits in an eightbyte, coerce it into the matching integral 1796 // type, which will end up on the stack (with alignment 8). 1797 if (Align == 8 && Size <= 64) 1798 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 1799 Size)); 1800 } 1801 1802 return ABIArgInfo::getIndirect(Align); 1803} 1804 1805/// GetByteVectorType - The ABI specifies that a value should be passed in an 1806/// full vector XMM/YMM register. Pick an LLVM IR type that will be passed as a 1807/// vector register. 1808llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const { 1809 llvm::Type *IRType = CGT.ConvertType(Ty); 1810 1811 // Wrapper structs that just contain vectors are passed just like vectors, 1812 // strip them off if present. 1813 llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType); 1814 while (STy && STy->getNumElements() == 1) { 1815 IRType = STy->getElementType(0); 1816 STy = dyn_cast<llvm::StructType>(IRType); 1817 } 1818 1819 // If the preferred type is a 16-byte vector, prefer to pass it. 1820 if (llvm::VectorType *VT = dyn_cast<llvm::VectorType>(IRType)){ 1821 llvm::Type *EltTy = VT->getElementType(); 1822 unsigned BitWidth = VT->getBitWidth(); 1823 if ((BitWidth >= 128 && BitWidth <= 256) && 1824 (EltTy->isFloatTy() || EltTy->isDoubleTy() || 1825 EltTy->isIntegerTy(8) || EltTy->isIntegerTy(16) || 1826 EltTy->isIntegerTy(32) || EltTy->isIntegerTy(64) || 1827 EltTy->isIntegerTy(128))) 1828 return VT; 1829 } 1830 1831 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()), 2); 1832} 1833 1834/// BitsContainNoUserData - Return true if the specified [start,end) bit range 1835/// is known to either be off the end of the specified type or being in 1836/// alignment padding. The user type specified is known to be at most 128 bits 1837/// in size, and have passed through X86_64ABIInfo::classify with a successful 1838/// classification that put one of the two halves in the INTEGER class. 1839/// 1840/// It is conservatively correct to return false. 1841static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, 1842 unsigned EndBit, ASTContext &Context) { 1843 // If the bytes being queried are off the end of the type, there is no user 1844 // data hiding here. This handles analysis of builtins, vectors and other 1845 // types that don't contain interesting padding. 1846 unsigned TySize = (unsigned)Context.getTypeSize(Ty); 1847 if (TySize <= StartBit) 1848 return true; 1849 1850 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 1851 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType()); 1852 unsigned NumElts = (unsigned)AT->getSize().getZExtValue(); 1853 1854 // Check each element to see if the element overlaps with the queried range. 1855 for (unsigned i = 0; i != NumElts; ++i) { 1856 // If the element is after the span we care about, then we're done.. 1857 unsigned EltOffset = i*EltSize; 1858 if (EltOffset >= EndBit) break; 1859 1860 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0; 1861 if (!BitsContainNoUserData(AT->getElementType(), EltStart, 1862 EndBit-EltOffset, Context)) 1863 return false; 1864 } 1865 // If it overlaps no elements, then it is safe to process as padding. 1866 return true; 1867 } 1868 1869 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1870 const RecordDecl *RD = RT->getDecl(); 1871 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 1872 1873 // If this is a C++ record, check the bases first. 1874 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1875 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1876 e = CXXRD->bases_end(); i != e; ++i) { 1877 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1878 "Unexpected base class!"); 1879 const CXXRecordDecl *Base = 1880 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1881 1882 // If the base is after the span we care about, ignore it. 1883 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base)); 1884 if (BaseOffset >= EndBit) continue; 1885 1886 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0; 1887 if (!BitsContainNoUserData(i->getType(), BaseStart, 1888 EndBit-BaseOffset, Context)) 1889 return false; 1890 } 1891 } 1892 1893 // Verify that no field has data that overlaps the region of interest. Yes 1894 // this could be sped up a lot by being smarter about queried fields, 1895 // however we're only looking at structs up to 16 bytes, so we don't care 1896 // much. 1897 unsigned idx = 0; 1898 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1899 i != e; ++i, ++idx) { 1900 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx); 1901 1902 // If we found a field after the region we care about, then we're done. 1903 if (FieldOffset >= EndBit) break; 1904 1905 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0; 1906 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset, 1907 Context)) 1908 return false; 1909 } 1910 1911 // If nothing in this record overlapped the area of interest, then we're 1912 // clean. 1913 return true; 1914 } 1915 1916 return false; 1917} 1918 1919/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a 1920/// float member at the specified offset. For example, {int,{float}} has a 1921/// float at offset 4. It is conservatively correct for this routine to return 1922/// false. 1923static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, 1924 const llvm::DataLayout &TD) { 1925 // Base case if we find a float. 1926 if (IROffset == 0 && IRType->isFloatTy()) 1927 return true; 1928 1929 // If this is a struct, recurse into the field at the specified offset. 1930 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 1931 const llvm::StructLayout *SL = TD.getStructLayout(STy); 1932 unsigned Elt = SL->getElementContainingOffset(IROffset); 1933 IROffset -= SL->getElementOffset(Elt); 1934 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD); 1935 } 1936 1937 // If this is an array, recurse into the field at the specified offset. 1938 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 1939 llvm::Type *EltTy = ATy->getElementType(); 1940 unsigned EltSize = TD.getTypeAllocSize(EltTy); 1941 IROffset -= IROffset/EltSize*EltSize; 1942 return ContainsFloatAtOffset(EltTy, IROffset, TD); 1943 } 1944 1945 return false; 1946} 1947 1948 1949/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the 1950/// low 8 bytes of an XMM register, corresponding to the SSE class. 1951llvm::Type *X86_64ABIInfo:: 1952GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1953 QualType SourceTy, unsigned SourceOffset) const { 1954 // The only three choices we have are either double, <2 x float>, or float. We 1955 // pass as float if the last 4 bytes is just padding. This happens for 1956 // structs that contain 3 floats. 1957 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32, 1958 SourceOffset*8+64, getContext())) 1959 return llvm::Type::getFloatTy(getVMContext()); 1960 1961 // We want to pass as <2 x float> if the LLVM IR type contains a float at 1962 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the 1963 // case. 1964 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) && 1965 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout())) 1966 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2); 1967 1968 return llvm::Type::getDoubleTy(getVMContext()); 1969} 1970 1971 1972/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in 1973/// an 8-byte GPR. This means that we either have a scalar or we are talking 1974/// about the high or low part of an up-to-16-byte struct. This routine picks 1975/// the best LLVM IR type to represent this, which may be i64 or may be anything 1976/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*, 1977/// etc). 1978/// 1979/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for 1980/// the source type. IROffset is an offset in bytes into the LLVM IR type that 1981/// the 8-byte value references. PrefType may be null. 1982/// 1983/// SourceTy is the source level type for the entire argument. SourceOffset is 1984/// an offset into this that we're processing (which is always either 0 or 8). 1985/// 1986llvm::Type *X86_64ABIInfo:: 1987GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1988 QualType SourceTy, unsigned SourceOffset) const { 1989 // If we're dealing with an un-offset LLVM IR type, then it means that we're 1990 // returning an 8-byte unit starting with it. See if we can safely use it. 1991 if (IROffset == 0) { 1992 // Pointers and int64's always fill the 8-byte unit. 1993 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) || 1994 IRType->isIntegerTy(64)) 1995 return IRType; 1996 1997 // If we have a 1/2/4-byte integer, we can use it only if the rest of the 1998 // goodness in the source type is just tail padding. This is allowed to 1999 // kick in for struct {double,int} on the int, but not on 2000 // struct{double,int,int} because we wouldn't return the second int. We 2001 // have to do this analysis on the source type because we can't depend on 2002 // unions being lowered a specific way etc. 2003 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) || 2004 IRType->isIntegerTy(32) || 2005 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) { 2006 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 : 2007 cast<llvm::IntegerType>(IRType)->getBitWidth(); 2008 2009 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth, 2010 SourceOffset*8+64, getContext())) 2011 return IRType; 2012 } 2013 } 2014 2015 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 2016 // If this is a struct, recurse into the field at the specified offset. 2017 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy); 2018 if (IROffset < SL->getSizeInBytes()) { 2019 unsigned FieldIdx = SL->getElementContainingOffset(IROffset); 2020 IROffset -= SL->getElementOffset(FieldIdx); 2021 2022 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset, 2023 SourceTy, SourceOffset); 2024 } 2025 } 2026 2027 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 2028 llvm::Type *EltTy = ATy->getElementType(); 2029 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy); 2030 unsigned EltOffset = IROffset/EltSize*EltSize; 2031 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy, 2032 SourceOffset); 2033 } 2034 2035 // Okay, we don't have any better idea of what to pass, so we pass this in an 2036 // integer register that isn't too big to fit the rest of the struct. 2037 unsigned TySizeInBytes = 2038 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity(); 2039 2040 assert(TySizeInBytes != SourceOffset && "Empty field?"); 2041 2042 // It is always safe to classify this as an integer type up to i64 that 2043 // isn't larger than the structure. 2044 return llvm::IntegerType::get(getVMContext(), 2045 std::min(TySizeInBytes-SourceOffset, 8U)*8); 2046} 2047 2048 2049/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally 2050/// be used as elements of a two register pair to pass or return, return a 2051/// first class aggregate to represent them. For example, if the low part of 2052/// a by-value argument should be passed as i32* and the high part as float, 2053/// return {i32*, float}. 2054static llvm::Type * 2055GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, 2056 const llvm::DataLayout &TD) { 2057 // In order to correctly satisfy the ABI, we need to the high part to start 2058 // at offset 8. If the high and low parts we inferred are both 4-byte types 2059 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have 2060 // the second element at offset 8. Check for this: 2061 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo); 2062 unsigned HiAlign = TD.getABITypeAlignment(Hi); 2063 unsigned HiStart = llvm::DataLayout::RoundUpAlignment(LoSize, HiAlign); 2064 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!"); 2065 2066 // To handle this, we have to increase the size of the low part so that the 2067 // second element will start at an 8 byte offset. We can't increase the size 2068 // of the second element because it might make us access off the end of the 2069 // struct. 2070 if (HiStart != 8) { 2071 // There are only two sorts of types the ABI generation code can produce for 2072 // the low part of a pair that aren't 8 bytes in size: float or i8/i16/i32. 2073 // Promote these to a larger type. 2074 if (Lo->isFloatTy()) 2075 Lo = llvm::Type::getDoubleTy(Lo->getContext()); 2076 else { 2077 assert(Lo->isIntegerTy() && "Invalid/unknown lo type"); 2078 Lo = llvm::Type::getInt64Ty(Lo->getContext()); 2079 } 2080 } 2081 2082 llvm::StructType *Result = llvm::StructType::get(Lo, Hi, NULL); 2083 2084 2085 // Verify that the second element is at an 8-byte offset. 2086 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 && 2087 "Invalid x86-64 argument pair!"); 2088 return Result; 2089} 2090 2091ABIArgInfo X86_64ABIInfo:: 2092classifyReturnType(QualType RetTy) const { 2093 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the 2094 // classification algorithm. 2095 X86_64ABIInfo::Class Lo, Hi; 2096 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true); 2097 2098 // Check some invariants. 2099 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2100 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2101 2102 llvm::Type *ResType = 0; 2103 switch (Lo) { 2104 case NoClass: 2105 if (Hi == NoClass) 2106 return ABIArgInfo::getIgnore(); 2107 // If the low part is just padding, it takes no register, leave ResType 2108 // null. 2109 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2110 "Unknown missing lo part"); 2111 break; 2112 2113 case SSEUp: 2114 case X87Up: 2115 llvm_unreachable("Invalid classification for lo word."); 2116 2117 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via 2118 // hidden argument. 2119 case Memory: 2120 return getIndirectReturnResult(RetTy); 2121 2122 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next 2123 // available register of the sequence %rax, %rdx is used. 2124 case Integer: 2125 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2126 2127 // If we have a sign or zero extended integer, make sure to return Extend 2128 // so that the parameter gets the right LLVM IR attributes. 2129 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2130 // Treat an enum type as its underlying type. 2131 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 2132 RetTy = EnumTy->getDecl()->getIntegerType(); 2133 2134 if (RetTy->isIntegralOrEnumerationType() && 2135 RetTy->isPromotableIntegerType()) 2136 return ABIArgInfo::getExtend(); 2137 } 2138 break; 2139 2140 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next 2141 // available SSE register of the sequence %xmm0, %xmm1 is used. 2142 case SSE: 2143 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2144 break; 2145 2146 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is 2147 // returned on the X87 stack in %st0 as 80-bit x87 number. 2148 case X87: 2149 ResType = llvm::Type::getX86_FP80Ty(getVMContext()); 2150 break; 2151 2152 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real 2153 // part of the value is returned in %st0 and the imaginary part in 2154 // %st1. 2155 case ComplexX87: 2156 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification."); 2157 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()), 2158 llvm::Type::getX86_FP80Ty(getVMContext()), 2159 NULL); 2160 break; 2161 } 2162 2163 llvm::Type *HighPart = 0; 2164 switch (Hi) { 2165 // Memory was handled previously and X87 should 2166 // never occur as a hi class. 2167 case Memory: 2168 case X87: 2169 llvm_unreachable("Invalid classification for hi word."); 2170 2171 case ComplexX87: // Previously handled. 2172 case NoClass: 2173 break; 2174 2175 case Integer: 2176 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2177 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2178 return ABIArgInfo::getDirect(HighPart, 8); 2179 break; 2180 case SSE: 2181 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2182 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2183 return ABIArgInfo::getDirect(HighPart, 8); 2184 break; 2185 2186 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte 2187 // is passed in the next available eightbyte chunk if the last used 2188 // vector register. 2189 // 2190 // SSEUP should always be preceded by SSE, just widen. 2191 case SSEUp: 2192 assert(Lo == SSE && "Unexpected SSEUp classification."); 2193 ResType = GetByteVectorType(RetTy); 2194 break; 2195 2196 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is 2197 // returned together with the previous X87 value in %st0. 2198 case X87Up: 2199 // If X87Up is preceded by X87, we don't need to do 2200 // anything. However, in some cases with unions it may not be 2201 // preceded by X87. In such situations we follow gcc and pass the 2202 // extra bits in an SSE reg. 2203 if (Lo != X87) { 2204 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2205 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2206 return ABIArgInfo::getDirect(HighPart, 8); 2207 } 2208 break; 2209 } 2210 2211 // If a high part was specified, merge it together with the low part. It is 2212 // known to pass in the high eightbyte of the result. We do this by forming a 2213 // first class struct aggregate with the high and low part: {low, high} 2214 if (HighPart) 2215 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2216 2217 return ABIArgInfo::getDirect(ResType); 2218} 2219 2220ABIArgInfo X86_64ABIInfo::classifyArgumentType( 2221 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE, 2222 bool isNamedArg) 2223 const 2224{ 2225 X86_64ABIInfo::Class Lo, Hi; 2226 classify(Ty, 0, Lo, Hi, isNamedArg); 2227 2228 // Check some invariants. 2229 // FIXME: Enforce these by construction. 2230 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2231 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2232 2233 neededInt = 0; 2234 neededSSE = 0; 2235 llvm::Type *ResType = 0; 2236 switch (Lo) { 2237 case NoClass: 2238 if (Hi == NoClass) 2239 return ABIArgInfo::getIgnore(); 2240 // If the low part is just padding, it takes no register, leave ResType 2241 // null. 2242 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2243 "Unknown missing lo part"); 2244 break; 2245 2246 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument 2247 // on the stack. 2248 case Memory: 2249 2250 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or 2251 // COMPLEX_X87, it is passed in memory. 2252 case X87: 2253 case ComplexX87: 2254 if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect) 2255 ++neededInt; 2256 return getIndirectResult(Ty, freeIntRegs); 2257 2258 case SSEUp: 2259 case X87Up: 2260 llvm_unreachable("Invalid classification for lo word."); 2261 2262 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next 2263 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8 2264 // and %r9 is used. 2265 case Integer: 2266 ++neededInt; 2267 2268 // Pick an 8-byte type based on the preferred type. 2269 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0); 2270 2271 // If we have a sign or zero extended integer, make sure to return Extend 2272 // so that the parameter gets the right LLVM IR attributes. 2273 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2274 // Treat an enum type as its underlying type. 2275 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2276 Ty = EnumTy->getDecl()->getIntegerType(); 2277 2278 if (Ty->isIntegralOrEnumerationType() && 2279 Ty->isPromotableIntegerType()) 2280 return ABIArgInfo::getExtend(); 2281 } 2282 2283 break; 2284 2285 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next 2286 // available SSE register is used, the registers are taken in the 2287 // order from %xmm0 to %xmm7. 2288 case SSE: { 2289 llvm::Type *IRType = CGT.ConvertType(Ty); 2290 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0); 2291 ++neededSSE; 2292 break; 2293 } 2294 } 2295 2296 llvm::Type *HighPart = 0; 2297 switch (Hi) { 2298 // Memory was handled previously, ComplexX87 and X87 should 2299 // never occur as hi classes, and X87Up must be preceded by X87, 2300 // which is passed in memory. 2301 case Memory: 2302 case X87: 2303 case ComplexX87: 2304 llvm_unreachable("Invalid classification for hi word."); 2305 2306 case NoClass: break; 2307 2308 case Integer: 2309 ++neededInt; 2310 // Pick an 8-byte type based on the preferred type. 2311 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2312 2313 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2314 return ABIArgInfo::getDirect(HighPart, 8); 2315 break; 2316 2317 // X87Up generally doesn't occur here (long double is passed in 2318 // memory), except in situations involving unions. 2319 case X87Up: 2320 case SSE: 2321 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2322 2323 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2324 return ABIArgInfo::getDirect(HighPart, 8); 2325 2326 ++neededSSE; 2327 break; 2328 2329 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the 2330 // eightbyte is passed in the upper half of the last used SSE 2331 // register. This only happens when 128-bit vectors are passed. 2332 case SSEUp: 2333 assert(Lo == SSE && "Unexpected SSEUp classification"); 2334 ResType = GetByteVectorType(Ty); 2335 break; 2336 } 2337 2338 // If a high part was specified, merge it together with the low part. It is 2339 // known to pass in the high eightbyte of the result. We do this by forming a 2340 // first class struct aggregate with the high and low part: {low, high} 2341 if (HighPart) 2342 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2343 2344 return ABIArgInfo::getDirect(ResType); 2345} 2346 2347void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2348 2349 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2350 2351 // Keep track of the number of assigned registers. 2352 unsigned freeIntRegs = 6, freeSSERegs = 8; 2353 2354 // If the return value is indirect, then the hidden argument is consuming one 2355 // integer register. 2356 if (FI.getReturnInfo().isIndirect()) 2357 --freeIntRegs; 2358 2359 bool isVariadic = FI.isVariadic(); 2360 unsigned numRequiredArgs = 0; 2361 if (isVariadic) 2362 numRequiredArgs = FI.getRequiredArgs().getNumRequiredArgs(); 2363 2364 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers 2365 // get assigned (in left-to-right order) for passing as follows... 2366 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2367 it != ie; ++it) { 2368 bool isNamedArg = true; 2369 if (isVariadic) 2370 isNamedArg = (it - FI.arg_begin()) < 2371 static_cast<signed>(numRequiredArgs); 2372 2373 unsigned neededInt, neededSSE; 2374 it->info = classifyArgumentType(it->type, freeIntRegs, neededInt, 2375 neededSSE, isNamedArg); 2376 2377 // AMD64-ABI 3.2.3p3: If there are no registers available for any 2378 // eightbyte of an argument, the whole argument is passed on the 2379 // stack. If registers have already been assigned for some 2380 // eightbytes of such an argument, the assignments get reverted. 2381 if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) { 2382 freeIntRegs -= neededInt; 2383 freeSSERegs -= neededSSE; 2384 } else { 2385 it->info = getIndirectResult(it->type, freeIntRegs); 2386 } 2387 } 2388} 2389 2390static llvm::Value *EmitVAArgFromMemory(llvm::Value *VAListAddr, 2391 QualType Ty, 2392 CodeGenFunction &CGF) { 2393 llvm::Value *overflow_arg_area_p = 2394 CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p"); 2395 llvm::Value *overflow_arg_area = 2396 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area"); 2397 2398 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16 2399 // byte boundary if alignment needed by type exceeds 8 byte boundary. 2400 // It isn't stated explicitly in the standard, but in practice we use 2401 // alignment greater than 16 where necessary. 2402 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8; 2403 if (Align > 8) { 2404 // overflow_arg_area = (overflow_arg_area + align - 1) & -align; 2405 llvm::Value *Offset = 2406 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1); 2407 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset); 2408 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area, 2409 CGF.Int64Ty); 2410 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align); 2411 overflow_arg_area = 2412 CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 2413 overflow_arg_area->getType(), 2414 "overflow_arg_area.align"); 2415 } 2416 2417 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area. 2418 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2419 llvm::Value *Res = 2420 CGF.Builder.CreateBitCast(overflow_arg_area, 2421 llvm::PointerType::getUnqual(LTy)); 2422 2423 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to: 2424 // l->overflow_arg_area + sizeof(type). 2425 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to 2426 // an 8 byte boundary. 2427 2428 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8; 2429 llvm::Value *Offset = 2430 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7); 2431 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset, 2432 "overflow_arg_area.next"); 2433 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p); 2434 2435 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type. 2436 return Res; 2437} 2438 2439llvm::Value *X86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2440 CodeGenFunction &CGF) const { 2441 // Assume that va_list type is correct; should be pointer to LLVM type: 2442 // struct { 2443 // i32 gp_offset; 2444 // i32 fp_offset; 2445 // i8* overflow_arg_area; 2446 // i8* reg_save_area; 2447 // }; 2448 unsigned neededInt, neededSSE; 2449 2450 Ty = CGF.getContext().getCanonicalType(Ty); 2451 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE, 2452 /*isNamedArg*/false); 2453 2454 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed 2455 // in the registers. If not go to step 7. 2456 if (!neededInt && !neededSSE) 2457 return EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2458 2459 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of 2460 // general purpose registers needed to pass type and num_fp to hold 2461 // the number of floating point registers needed. 2462 2463 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into 2464 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or 2465 // l->fp_offset > 304 - num_fp * 16 go to step 7. 2466 // 2467 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of 2468 // register save space). 2469 2470 llvm::Value *InRegs = 0; 2471 llvm::Value *gp_offset_p = 0, *gp_offset = 0; 2472 llvm::Value *fp_offset_p = 0, *fp_offset = 0; 2473 if (neededInt) { 2474 gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p"); 2475 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset"); 2476 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8); 2477 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp"); 2478 } 2479 2480 if (neededSSE) { 2481 fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p"); 2482 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset"); 2483 llvm::Value *FitsInFP = 2484 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16); 2485 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp"); 2486 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP; 2487 } 2488 2489 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 2490 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 2491 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 2492 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 2493 2494 // Emit code to load the value if it was passed in registers. 2495 2496 CGF.EmitBlock(InRegBlock); 2497 2498 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with 2499 // an offset of l->gp_offset and/or l->fp_offset. This may require 2500 // copying to a temporary location in case the parameter is passed 2501 // in different register classes or requires an alignment greater 2502 // than 8 for general purpose registers and 16 for XMM registers. 2503 // 2504 // FIXME: This really results in shameful code when we end up needing to 2505 // collect arguments from different places; often what should result in a 2506 // simple assembling of a structure from scattered addresses has many more 2507 // loads than necessary. Can we clean this up? 2508 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2509 llvm::Value *RegAddr = 2510 CGF.Builder.CreateLoad(CGF.Builder.CreateStructGEP(VAListAddr, 3), 2511 "reg_save_area"); 2512 if (neededInt && neededSSE) { 2513 // FIXME: Cleanup. 2514 assert(AI.isDirect() && "Unexpected ABI info for mixed regs"); 2515 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType()); 2516 llvm::Value *Tmp = CGF.CreateMemTemp(Ty); 2517 Tmp = CGF.Builder.CreateBitCast(Tmp, ST->getPointerTo()); 2518 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs"); 2519 llvm::Type *TyLo = ST->getElementType(0); 2520 llvm::Type *TyHi = ST->getElementType(1); 2521 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) && 2522 "Unexpected ABI info for mixed regs"); 2523 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo); 2524 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi); 2525 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2526 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2527 llvm::Value *RegLoAddr = TyLo->isFloatingPointTy() ? FPAddr : GPAddr; 2528 llvm::Value *RegHiAddr = TyLo->isFloatingPointTy() ? GPAddr : FPAddr; 2529 llvm::Value *V = 2530 CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegLoAddr, PTyLo)); 2531 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2532 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegHiAddr, PTyHi)); 2533 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2534 2535 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2536 llvm::PointerType::getUnqual(LTy)); 2537 } else if (neededInt) { 2538 RegAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2539 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2540 llvm::PointerType::getUnqual(LTy)); 2541 2542 // Copy to a temporary if necessary to ensure the appropriate alignment. 2543 std::pair<CharUnits, CharUnits> SizeAlign = 2544 CGF.getContext().getTypeInfoInChars(Ty); 2545 uint64_t TySize = SizeAlign.first.getQuantity(); 2546 unsigned TyAlign = SizeAlign.second.getQuantity(); 2547 if (TyAlign > 8) { 2548 llvm::Value *Tmp = CGF.CreateMemTemp(Ty); 2549 CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, 8, false); 2550 RegAddr = Tmp; 2551 } 2552 } else if (neededSSE == 1) { 2553 RegAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2554 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2555 llvm::PointerType::getUnqual(LTy)); 2556 } else { 2557 assert(neededSSE == 2 && "Invalid number of needed registers!"); 2558 // SSE registers are spaced 16 bytes apart in the register save 2559 // area, we need to collect the two eightbytes together. 2560 llvm::Value *RegAddrLo = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2561 llvm::Value *RegAddrHi = CGF.Builder.CreateConstGEP1_32(RegAddrLo, 16); 2562 llvm::Type *DoubleTy = CGF.DoubleTy; 2563 llvm::Type *DblPtrTy = 2564 llvm::PointerType::getUnqual(DoubleTy); 2565 llvm::StructType *ST = llvm::StructType::get(DoubleTy, DoubleTy, NULL); 2566 llvm::Value *V, *Tmp = CGF.CreateMemTemp(Ty); 2567 Tmp = CGF.Builder.CreateBitCast(Tmp, ST->getPointerTo()); 2568 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrLo, 2569 DblPtrTy)); 2570 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2571 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrHi, 2572 DblPtrTy)); 2573 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2574 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2575 llvm::PointerType::getUnqual(LTy)); 2576 } 2577 2578 // AMD64-ABI 3.5.7p5: Step 5. Set: 2579 // l->gp_offset = l->gp_offset + num_gp * 8 2580 // l->fp_offset = l->fp_offset + num_fp * 16. 2581 if (neededInt) { 2582 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8); 2583 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset), 2584 gp_offset_p); 2585 } 2586 if (neededSSE) { 2587 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16); 2588 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset), 2589 fp_offset_p); 2590 } 2591 CGF.EmitBranch(ContBlock); 2592 2593 // Emit code to load the value if it was passed in memory. 2594 2595 CGF.EmitBlock(InMemBlock); 2596 llvm::Value *MemAddr = EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2597 2598 // Return the appropriate result. 2599 2600 CGF.EmitBlock(ContBlock); 2601 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(RegAddr->getType(), 2, 2602 "vaarg.addr"); 2603 ResAddr->addIncoming(RegAddr, InRegBlock); 2604 ResAddr->addIncoming(MemAddr, InMemBlock); 2605 return ResAddr; 2606} 2607 2608ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, bool IsReturnType) const { 2609 2610 if (Ty->isVoidType()) 2611 return ABIArgInfo::getIgnore(); 2612 2613 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2614 Ty = EnumTy->getDecl()->getIntegerType(); 2615 2616 uint64_t Size = getContext().getTypeSize(Ty); 2617 2618 if (const RecordType *RT = Ty->getAs<RecordType>()) { 2619 if (IsReturnType) { 2620 if (isRecordReturnIndirect(RT, getCXXABI())) 2621 return ABIArgInfo::getIndirect(0, false); 2622 } else { 2623 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI())) 2624 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 2625 } 2626 2627 if (RT->getDecl()->hasFlexibleArrayMember()) 2628 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2629 2630 // FIXME: mingw-w64-gcc emits 128-bit struct as i128 2631 if (Size == 128 && getTarget().getTriple().getOS() == llvm::Triple::MinGW32) 2632 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2633 Size)); 2634 2635 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is 2636 // not 1, 2, 4, or 8 bytes, must be passed by reference." 2637 if (Size <= 64 && 2638 (Size & (Size - 1)) == 0) 2639 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2640 Size)); 2641 2642 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2643 } 2644 2645 if (Ty->isPromotableIntegerType()) 2646 return ABIArgInfo::getExtend(); 2647 2648 return ABIArgInfo::getDirect(); 2649} 2650 2651void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2652 2653 QualType RetTy = FI.getReturnType(); 2654 FI.getReturnInfo() = classify(RetTy, true); 2655 2656 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2657 it != ie; ++it) 2658 it->info = classify(it->type, false); 2659} 2660 2661llvm::Value *WinX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2662 CodeGenFunction &CGF) const { 2663 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2664 2665 CGBuilderTy &Builder = CGF.Builder; 2666 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 2667 "ap"); 2668 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2669 llvm::Type *PTy = 2670 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2671 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 2672 2673 uint64_t Offset = 2674 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 8); 2675 llvm::Value *NextAddr = 2676 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 2677 "ap.next"); 2678 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2679 2680 return AddrTyped; 2681} 2682 2683namespace { 2684 2685class NaClX86_64ABIInfo : public ABIInfo { 2686 public: 2687 NaClX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2688 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, HasAVX) {} 2689 virtual void computeInfo(CGFunctionInfo &FI) const; 2690 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2691 CodeGenFunction &CGF) const; 2692 private: 2693 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 2694 X86_64ABIInfo NInfo; // Used for everything else. 2695}; 2696 2697class NaClX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 2698 public: 2699 NaClX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2700 : TargetCodeGenInfo(new NaClX86_64ABIInfo(CGT, HasAVX)) {} 2701}; 2702 2703} 2704 2705void NaClX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2706 if (FI.getASTCallingConvention() == CC_PnaclCall) 2707 PInfo.computeInfo(FI); 2708 else 2709 NInfo.computeInfo(FI); 2710} 2711 2712llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2713 CodeGenFunction &CGF) const { 2714 // Always use the native convention; calling pnacl-style varargs functions 2715 // is unuspported. 2716 return NInfo.EmitVAArg(VAListAddr, Ty, CGF); 2717} 2718 2719 2720// PowerPC-32 2721 2722namespace { 2723class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2724public: 2725 PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2726 2727 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2728 // This is recovered from gcc output. 2729 return 1; // r1 is the dedicated stack pointer 2730 } 2731 2732 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2733 llvm::Value *Address) const; 2734}; 2735 2736} 2737 2738bool 2739PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2740 llvm::Value *Address) const { 2741 // This is calculated from the LLVM and GCC tables and verified 2742 // against gcc output. AFAIK all ABIs use the same encoding. 2743 2744 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2745 2746 llvm::IntegerType *i8 = CGF.Int8Ty; 2747 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2748 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2749 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2750 2751 // 0-31: r0-31, the 4-byte general-purpose registers 2752 AssignToArrayRange(Builder, Address, Four8, 0, 31); 2753 2754 // 32-63: fp0-31, the 8-byte floating-point registers 2755 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2756 2757 // 64-76 are various 4-byte special-purpose registers: 2758 // 64: mq 2759 // 65: lr 2760 // 66: ctr 2761 // 67: ap 2762 // 68-75 cr0-7 2763 // 76: xer 2764 AssignToArrayRange(Builder, Address, Four8, 64, 76); 2765 2766 // 77-108: v0-31, the 16-byte vector registers 2767 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 2768 2769 // 109: vrsave 2770 // 110: vscr 2771 // 111: spe_acc 2772 // 112: spefscr 2773 // 113: sfp 2774 AssignToArrayRange(Builder, Address, Four8, 109, 113); 2775 2776 return false; 2777} 2778 2779// PowerPC-64 2780 2781namespace { 2782/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information. 2783class PPC64_SVR4_ABIInfo : public DefaultABIInfo { 2784 2785public: 2786 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 2787 2788 bool isPromotableTypeForABI(QualType Ty) const; 2789 2790 ABIArgInfo classifyReturnType(QualType RetTy) const; 2791 ABIArgInfo classifyArgumentType(QualType Ty) const; 2792 2793 // TODO: We can add more logic to computeInfo to improve performance. 2794 // Example: For aggregate arguments that fit in a register, we could 2795 // use getDirectInReg (as is done below for structs containing a single 2796 // floating-point value) to avoid pushing them to memory on function 2797 // entry. This would require changing the logic in PPCISelLowering 2798 // when lowering the parameters in the caller and args in the callee. 2799 virtual void computeInfo(CGFunctionInfo &FI) const { 2800 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2801 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2802 it != ie; ++it) { 2803 // We rely on the default argument classification for the most part. 2804 // One exception: An aggregate containing a single floating-point 2805 // or vector item must be passed in a register if one is available. 2806 const Type *T = isSingleElementStruct(it->type, getContext()); 2807 if (T) { 2808 const BuiltinType *BT = T->getAs<BuiltinType>(); 2809 if (T->isVectorType() || (BT && BT->isFloatingPoint())) { 2810 QualType QT(T, 0); 2811 it->info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT)); 2812 continue; 2813 } 2814 } 2815 it->info = classifyArgumentType(it->type); 2816 } 2817 } 2818 2819 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, 2820 QualType Ty, 2821 CodeGenFunction &CGF) const; 2822}; 2823 2824class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo { 2825public: 2826 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT) 2827 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT)) {} 2828 2829 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2830 // This is recovered from gcc output. 2831 return 1; // r1 is the dedicated stack pointer 2832 } 2833 2834 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2835 llvm::Value *Address) const; 2836}; 2837 2838class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2839public: 2840 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2841 2842 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2843 // This is recovered from gcc output. 2844 return 1; // r1 is the dedicated stack pointer 2845 } 2846 2847 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2848 llvm::Value *Address) const; 2849}; 2850 2851} 2852 2853// Return true if the ABI requires Ty to be passed sign- or zero- 2854// extended to 64 bits. 2855bool 2856PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const { 2857 // Treat an enum type as its underlying type. 2858 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2859 Ty = EnumTy->getDecl()->getIntegerType(); 2860 2861 // Promotable integer types are required to be promoted by the ABI. 2862 if (Ty->isPromotableIntegerType()) 2863 return true; 2864 2865 // In addition to the usual promotable integer types, we also need to 2866 // extend all 32-bit types, since the ABI requires promotion to 64 bits. 2867 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 2868 switch (BT->getKind()) { 2869 case BuiltinType::Int: 2870 case BuiltinType::UInt: 2871 return true; 2872 default: 2873 break; 2874 } 2875 2876 return false; 2877} 2878 2879ABIArgInfo 2880PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const { 2881 if (Ty->isAnyComplexType()) 2882 return ABIArgInfo::getDirect(); 2883 2884 if (isAggregateTypeForABI(Ty)) { 2885 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 2886 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 2887 2888 return ABIArgInfo::getIndirect(0); 2889 } 2890 2891 return (isPromotableTypeForABI(Ty) ? 2892 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 2893} 2894 2895ABIArgInfo 2896PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const { 2897 if (RetTy->isVoidType()) 2898 return ABIArgInfo::getIgnore(); 2899 2900 if (RetTy->isAnyComplexType()) 2901 return ABIArgInfo::getDirect(); 2902 2903 if (isAggregateTypeForABI(RetTy)) 2904 return ABIArgInfo::getIndirect(0); 2905 2906 return (isPromotableTypeForABI(RetTy) ? 2907 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 2908} 2909 2910// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine. 2911llvm::Value *PPC64_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr, 2912 QualType Ty, 2913 CodeGenFunction &CGF) const { 2914 llvm::Type *BP = CGF.Int8PtrTy; 2915 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2916 2917 CGBuilderTy &Builder = CGF.Builder; 2918 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 2919 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2920 2921 // Update the va_list pointer. The pointer should be bumped by the 2922 // size of the object. We can trust getTypeSize() except for a complex 2923 // type whose base type is smaller than a doubleword. For these, the 2924 // size of the object is 16 bytes; see below for further explanation. 2925 unsigned SizeInBytes = CGF.getContext().getTypeSize(Ty) / 8; 2926 QualType BaseTy; 2927 unsigned CplxBaseSize = 0; 2928 2929 if (const ComplexType *CTy = Ty->getAs<ComplexType>()) { 2930 BaseTy = CTy->getElementType(); 2931 CplxBaseSize = CGF.getContext().getTypeSize(BaseTy) / 8; 2932 if (CplxBaseSize < 8) 2933 SizeInBytes = 16; 2934 } 2935 2936 unsigned Offset = llvm::RoundUpToAlignment(SizeInBytes, 8); 2937 llvm::Value *NextAddr = 2938 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), 2939 "ap.next"); 2940 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2941 2942 // If we have a complex type and the base type is smaller than 8 bytes, 2943 // the ABI calls for the real and imaginary parts to be right-adjusted 2944 // in separate doublewords. However, Clang expects us to produce a 2945 // pointer to a structure with the two parts packed tightly. So generate 2946 // loads of the real and imaginary parts relative to the va_list pointer, 2947 // and store them to a temporary structure. 2948 if (CplxBaseSize && CplxBaseSize < 8) { 2949 llvm::Value *RealAddr = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2950 llvm::Value *ImagAddr = RealAddr; 2951 RealAddr = Builder.CreateAdd(RealAddr, Builder.getInt64(8 - CplxBaseSize)); 2952 ImagAddr = Builder.CreateAdd(ImagAddr, Builder.getInt64(16 - CplxBaseSize)); 2953 llvm::Type *PBaseTy = llvm::PointerType::getUnqual(CGF.ConvertType(BaseTy)); 2954 RealAddr = Builder.CreateIntToPtr(RealAddr, PBaseTy); 2955 ImagAddr = Builder.CreateIntToPtr(ImagAddr, PBaseTy); 2956 llvm::Value *Real = Builder.CreateLoad(RealAddr, false, ".vareal"); 2957 llvm::Value *Imag = Builder.CreateLoad(ImagAddr, false, ".vaimag"); 2958 llvm::Value *Ptr = CGF.CreateTempAlloca(CGT.ConvertTypeForMem(Ty), 2959 "vacplx"); 2960 llvm::Value *RealPtr = Builder.CreateStructGEP(Ptr, 0, ".real"); 2961 llvm::Value *ImagPtr = Builder.CreateStructGEP(Ptr, 1, ".imag"); 2962 Builder.CreateStore(Real, RealPtr, false); 2963 Builder.CreateStore(Imag, ImagPtr, false); 2964 return Ptr; 2965 } 2966 2967 // If the argument is smaller than 8 bytes, it is right-adjusted in 2968 // its doubleword slot. Adjust the pointer to pick it up from the 2969 // correct offset. 2970 if (SizeInBytes < 8) { 2971 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2972 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt64(8 - SizeInBytes)); 2973 Addr = Builder.CreateIntToPtr(AddrAsInt, BP); 2974 } 2975 2976 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2977 return Builder.CreateBitCast(Addr, PTy); 2978} 2979 2980static bool 2981PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2982 llvm::Value *Address) { 2983 // This is calculated from the LLVM and GCC tables and verified 2984 // against gcc output. AFAIK all ABIs use the same encoding. 2985 2986 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2987 2988 llvm::IntegerType *i8 = CGF.Int8Ty; 2989 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2990 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2991 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2992 2993 // 0-31: r0-31, the 8-byte general-purpose registers 2994 AssignToArrayRange(Builder, Address, Eight8, 0, 31); 2995 2996 // 32-63: fp0-31, the 8-byte floating-point registers 2997 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2998 2999 // 64-76 are various 4-byte special-purpose registers: 3000 // 64: mq 3001 // 65: lr 3002 // 66: ctr 3003 // 67: ap 3004 // 68-75 cr0-7 3005 // 76: xer 3006 AssignToArrayRange(Builder, Address, Four8, 64, 76); 3007 3008 // 77-108: v0-31, the 16-byte vector registers 3009 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 3010 3011 // 109: vrsave 3012 // 110: vscr 3013 // 111: spe_acc 3014 // 112: spefscr 3015 // 113: sfp 3016 AssignToArrayRange(Builder, Address, Four8, 109, 113); 3017 3018 return false; 3019} 3020 3021bool 3022PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable( 3023 CodeGen::CodeGenFunction &CGF, 3024 llvm::Value *Address) const { 3025 3026 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 3027} 3028 3029bool 3030PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3031 llvm::Value *Address) const { 3032 3033 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 3034} 3035 3036//===----------------------------------------------------------------------===// 3037// ARM ABI Implementation 3038//===----------------------------------------------------------------------===// 3039 3040namespace { 3041 3042class ARMABIInfo : public ABIInfo { 3043public: 3044 enum ABIKind { 3045 APCS = 0, 3046 AAPCS = 1, 3047 AAPCS_VFP 3048 }; 3049 3050private: 3051 ABIKind Kind; 3052 3053public: 3054 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind) : ABIInfo(CGT), Kind(_Kind) { 3055 setRuntimeCC(); 3056 } 3057 3058 bool isEABI() const { 3059 StringRef Env = getTarget().getTriple().getEnvironmentName(); 3060 return (Env == "gnueabi" || Env == "eabi" || 3061 Env == "android" || Env == "androideabi"); 3062 } 3063 3064 ABIKind getABIKind() const { return Kind; } 3065 3066private: 3067 ABIArgInfo classifyReturnType(QualType RetTy) const; 3068 ABIArgInfo classifyArgumentType(QualType RetTy, int *VFPRegs, 3069 unsigned &AllocatedVFP, 3070 bool &IsHA) const; 3071 bool isIllegalVectorType(QualType Ty) const; 3072 3073 virtual void computeInfo(CGFunctionInfo &FI) const; 3074 3075 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3076 CodeGenFunction &CGF) const; 3077 3078 llvm::CallingConv::ID getLLVMDefaultCC() const; 3079 llvm::CallingConv::ID getABIDefaultCC() const; 3080 void setRuntimeCC(); 3081}; 3082 3083class ARMTargetCodeGenInfo : public TargetCodeGenInfo { 3084public: 3085 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K) 3086 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {} 3087 3088 const ARMABIInfo &getABIInfo() const { 3089 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo()); 3090 } 3091 3092 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 3093 return 13; 3094 } 3095 3096 StringRef getARCRetainAutoreleasedReturnValueMarker() const { 3097 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue"; 3098 } 3099 3100 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3101 llvm::Value *Address) const { 3102 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 3103 3104 // 0-15 are the 16 integer registers. 3105 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15); 3106 return false; 3107 } 3108 3109 unsigned getSizeOfUnwindException() const { 3110 if (getABIInfo().isEABI()) return 88; 3111 return TargetCodeGenInfo::getSizeOfUnwindException(); 3112 } 3113 3114 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 3115 CodeGen::CodeGenModule &CGM) const { 3116 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 3117 if (!FD) 3118 return; 3119 3120 const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>(); 3121 if (!Attr) 3122 return; 3123 3124 const char *Kind; 3125 switch (Attr->getInterrupt()) { 3126 case ARMInterruptAttr::Generic: Kind = ""; break; 3127 case ARMInterruptAttr::IRQ: Kind = "IRQ"; break; 3128 case ARMInterruptAttr::FIQ: Kind = "FIQ"; break; 3129 case ARMInterruptAttr::SWI: Kind = "SWI"; break; 3130 case ARMInterruptAttr::ABORT: Kind = "ABORT"; break; 3131 case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break; 3132 } 3133 3134 llvm::Function *Fn = cast<llvm::Function>(GV); 3135 3136 Fn->addFnAttr("interrupt", Kind); 3137 3138 if (cast<ARMABIInfo>(getABIInfo()).getABIKind() == ARMABIInfo::APCS) 3139 return; 3140 3141 // AAPCS guarantees that sp will be 8-byte aligned on any public interface, 3142 // however this is not necessarily true on taking any interrupt. Instruct 3143 // the backend to perform a realignment as part of the function prologue. 3144 llvm::AttrBuilder B; 3145 B.addStackAlignmentAttr(8); 3146 Fn->addAttributes(llvm::AttributeSet::FunctionIndex, 3147 llvm::AttributeSet::get(CGM.getLLVMContext(), 3148 llvm::AttributeSet::FunctionIndex, 3149 B)); 3150 } 3151 3152}; 3153 3154} 3155 3156void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 3157 // To correctly handle Homogeneous Aggregate, we need to keep track of the 3158 // VFP registers allocated so far. 3159 // C.1.vfp If the argument is a VFP CPRC and there are sufficient consecutive 3160 // VFP registers of the appropriate type unallocated then the argument is 3161 // allocated to the lowest-numbered sequence of such registers. 3162 // C.2.vfp If the argument is a VFP CPRC then any VFP registers that are 3163 // unallocated are marked as unavailable. 3164 unsigned AllocatedVFP = 0; 3165 int VFPRegs[16] = { 0 }; 3166 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 3167 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3168 it != ie; ++it) { 3169 unsigned PreAllocation = AllocatedVFP; 3170 bool IsHA = false; 3171 // 6.1.2.3 There is one VFP co-processor register class using registers 3172 // s0-s15 (d0-d7) for passing arguments. 3173 const unsigned NumVFPs = 16; 3174 it->info = classifyArgumentType(it->type, VFPRegs, AllocatedVFP, IsHA); 3175 // If we do not have enough VFP registers for the HA, any VFP registers 3176 // that are unallocated are marked as unavailable. To achieve this, we add 3177 // padding of (NumVFPs - PreAllocation) floats. 3178 if (IsHA && AllocatedVFP > NumVFPs && PreAllocation < NumVFPs) { 3179 llvm::Type *PaddingTy = llvm::ArrayType::get( 3180 llvm::Type::getFloatTy(getVMContext()), NumVFPs - PreAllocation); 3181 it->info = ABIArgInfo::getExpandWithPadding(false, PaddingTy); 3182 } 3183 } 3184 3185 // Always honor user-specified calling convention. 3186 if (FI.getCallingConvention() != llvm::CallingConv::C) 3187 return; 3188 3189 llvm::CallingConv::ID cc = getRuntimeCC(); 3190 if (cc != llvm::CallingConv::C) 3191 FI.setEffectiveCallingConvention(cc); 3192} 3193 3194/// Return the default calling convention that LLVM will use. 3195llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const { 3196 // The default calling convention that LLVM will infer. 3197 if (getTarget().getTriple().getEnvironmentName()=="gnueabihf") 3198 return llvm::CallingConv::ARM_AAPCS_VFP; 3199 else if (isEABI()) 3200 return llvm::CallingConv::ARM_AAPCS; 3201 else 3202 return llvm::CallingConv::ARM_APCS; 3203} 3204 3205/// Return the calling convention that our ABI would like us to use 3206/// as the C calling convention. 3207llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const { 3208 switch (getABIKind()) { 3209 case APCS: return llvm::CallingConv::ARM_APCS; 3210 case AAPCS: return llvm::CallingConv::ARM_AAPCS; 3211 case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP; 3212 } 3213 llvm_unreachable("bad ABI kind"); 3214} 3215 3216void ARMABIInfo::setRuntimeCC() { 3217 assert(getRuntimeCC() == llvm::CallingConv::C); 3218 3219 // Don't muddy up the IR with a ton of explicit annotations if 3220 // they'd just match what LLVM will infer from the triple. 3221 llvm::CallingConv::ID abiCC = getABIDefaultCC(); 3222 if (abiCC != getLLVMDefaultCC()) 3223 RuntimeCC = abiCC; 3224} 3225 3226/// isHomogeneousAggregate - Return true if a type is an AAPCS-VFP homogeneous 3227/// aggregate. If HAMembers is non-null, the number of base elements 3228/// contained in the type is returned through it; this is used for the 3229/// recursive calls that check aggregate component types. 3230static bool isHomogeneousAggregate(QualType Ty, const Type *&Base, 3231 ASTContext &Context, 3232 uint64_t *HAMembers = 0) { 3233 uint64_t Members = 0; 3234 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 3235 if (!isHomogeneousAggregate(AT->getElementType(), Base, Context, &Members)) 3236 return false; 3237 Members *= AT->getSize().getZExtValue(); 3238 } else if (const RecordType *RT = Ty->getAs<RecordType>()) { 3239 const RecordDecl *RD = RT->getDecl(); 3240 if (RD->hasFlexibleArrayMember()) 3241 return false; 3242 3243 Members = 0; 3244 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3245 i != e; ++i) { 3246 const FieldDecl *FD = *i; 3247 uint64_t FldMembers; 3248 if (!isHomogeneousAggregate(FD->getType(), Base, Context, &FldMembers)) 3249 return false; 3250 3251 Members = (RD->isUnion() ? 3252 std::max(Members, FldMembers) : Members + FldMembers); 3253 } 3254 } else { 3255 Members = 1; 3256 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 3257 Members = 2; 3258 Ty = CT->getElementType(); 3259 } 3260 3261 // Homogeneous aggregates for AAPCS-VFP must have base types of float, 3262 // double, or 64-bit or 128-bit vectors. 3263 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 3264 if (BT->getKind() != BuiltinType::Float && 3265 BT->getKind() != BuiltinType::Double && 3266 BT->getKind() != BuiltinType::LongDouble) 3267 return false; 3268 } else if (const VectorType *VT = Ty->getAs<VectorType>()) { 3269 unsigned VecSize = Context.getTypeSize(VT); 3270 if (VecSize != 64 && VecSize != 128) 3271 return false; 3272 } else { 3273 return false; 3274 } 3275 3276 // The base type must be the same for all members. Vector types of the 3277 // same total size are treated as being equivalent here. 3278 const Type *TyPtr = Ty.getTypePtr(); 3279 if (!Base) 3280 Base = TyPtr; 3281 if (Base != TyPtr && 3282 (!Base->isVectorType() || !TyPtr->isVectorType() || 3283 Context.getTypeSize(Base) != Context.getTypeSize(TyPtr))) 3284 return false; 3285 } 3286 3287 // Homogeneous Aggregates can have at most 4 members of the base type. 3288 if (HAMembers) 3289 *HAMembers = Members; 3290 3291 return (Members > 0 && Members <= 4); 3292} 3293 3294/// markAllocatedVFPs - update VFPRegs according to the alignment and 3295/// number of VFP registers (unit is S register) requested. 3296static void markAllocatedVFPs(int *VFPRegs, unsigned &AllocatedVFP, 3297 unsigned Alignment, 3298 unsigned NumRequired) { 3299 // Early Exit. 3300 if (AllocatedVFP >= 16) 3301 return; 3302 // C.1.vfp If the argument is a VFP CPRC and there are sufficient consecutive 3303 // VFP registers of the appropriate type unallocated then the argument is 3304 // allocated to the lowest-numbered sequence of such registers. 3305 for (unsigned I = 0; I < 16; I += Alignment) { 3306 bool FoundSlot = true; 3307 for (unsigned J = I, JEnd = I + NumRequired; J < JEnd; J++) 3308 if (J >= 16 || VFPRegs[J]) { 3309 FoundSlot = false; 3310 break; 3311 } 3312 if (FoundSlot) { 3313 for (unsigned J = I, JEnd = I + NumRequired; J < JEnd; J++) 3314 VFPRegs[J] = 1; 3315 AllocatedVFP += NumRequired; 3316 return; 3317 } 3318 } 3319 // C.2.vfp If the argument is a VFP CPRC then any VFP registers that are 3320 // unallocated are marked as unavailable. 3321 for (unsigned I = 0; I < 16; I++) 3322 VFPRegs[I] = 1; 3323 AllocatedVFP = 17; // We do not have enough VFP registers. 3324} 3325 3326ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, int *VFPRegs, 3327 unsigned &AllocatedVFP, 3328 bool &IsHA) const { 3329 // We update number of allocated VFPs according to 3330 // 6.1.2.1 The following argument types are VFP CPRCs: 3331 // A single-precision floating-point type (including promoted 3332 // half-precision types); A double-precision floating-point type; 3333 // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate 3334 // with a Base Type of a single- or double-precision floating-point type, 3335 // 64-bit containerized vectors or 128-bit containerized vectors with one 3336 // to four Elements. 3337 3338 // Handle illegal vector types here. 3339 if (isIllegalVectorType(Ty)) { 3340 uint64_t Size = getContext().getTypeSize(Ty); 3341 if (Size <= 32) { 3342 llvm::Type *ResType = 3343 llvm::Type::getInt32Ty(getVMContext()); 3344 return ABIArgInfo::getDirect(ResType); 3345 } 3346 if (Size == 64) { 3347 llvm::Type *ResType = llvm::VectorType::get( 3348 llvm::Type::getInt32Ty(getVMContext()), 2); 3349 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, 2); 3350 return ABIArgInfo::getDirect(ResType); 3351 } 3352 if (Size == 128) { 3353 llvm::Type *ResType = llvm::VectorType::get( 3354 llvm::Type::getInt32Ty(getVMContext()), 4); 3355 markAllocatedVFPs(VFPRegs, AllocatedVFP, 4, 4); 3356 return ABIArgInfo::getDirect(ResType); 3357 } 3358 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3359 } 3360 // Update VFPRegs for legal vector types. 3361 if (const VectorType *VT = Ty->getAs<VectorType>()) { 3362 uint64_t Size = getContext().getTypeSize(VT); 3363 // Size of a legal vector should be power of 2 and above 64. 3364 markAllocatedVFPs(VFPRegs, AllocatedVFP, Size >= 128 ? 4 : 2, Size / 32); 3365 } 3366 // Update VFPRegs for floating point types. 3367 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 3368 if (BT->getKind() == BuiltinType::Half || 3369 BT->getKind() == BuiltinType::Float) 3370 markAllocatedVFPs(VFPRegs, AllocatedVFP, 1, 1); 3371 if (BT->getKind() == BuiltinType::Double || 3372 BT->getKind() == BuiltinType::LongDouble) 3373 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, 2); 3374 } 3375 3376 if (!isAggregateTypeForABI(Ty)) { 3377 // Treat an enum type as its underlying type. 3378 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3379 Ty = EnumTy->getDecl()->getIntegerType(); 3380 3381 return (Ty->isPromotableIntegerType() ? 3382 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3383 } 3384 3385 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 3386 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 3387 3388 // Ignore empty records. 3389 if (isEmptyRecord(getContext(), Ty, true)) 3390 return ABIArgInfo::getIgnore(); 3391 3392 if (getABIKind() == ARMABIInfo::AAPCS_VFP) { 3393 // Homogeneous Aggregates need to be expanded when we can fit the aggregate 3394 // into VFP registers. 3395 const Type *Base = 0; 3396 uint64_t Members = 0; 3397 if (isHomogeneousAggregate(Ty, Base, getContext(), &Members)) { 3398 assert(Base && "Base class should be set for homogeneous aggregate"); 3399 // Base can be a floating-point or a vector. 3400 if (Base->isVectorType()) { 3401 // ElementSize is in number of floats. 3402 unsigned ElementSize = getContext().getTypeSize(Base) == 64 ? 2 : 4; 3403 markAllocatedVFPs(VFPRegs, AllocatedVFP, ElementSize, 3404 Members * ElementSize); 3405 } else if (Base->isSpecificBuiltinType(BuiltinType::Float)) 3406 markAllocatedVFPs(VFPRegs, AllocatedVFP, 1, Members); 3407 else { 3408 assert(Base->isSpecificBuiltinType(BuiltinType::Double) || 3409 Base->isSpecificBuiltinType(BuiltinType::LongDouble)); 3410 markAllocatedVFPs(VFPRegs, AllocatedVFP, 2, Members * 2); 3411 } 3412 IsHA = true; 3413 return ABIArgInfo::getExpand(); 3414 } 3415 } 3416 3417 // Support byval for ARM. 3418 // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at 3419 // most 8-byte. We realign the indirect argument if type alignment is bigger 3420 // than ABI alignment. 3421 uint64_t ABIAlign = 4; 3422 uint64_t TyAlign = getContext().getTypeAlign(Ty) / 8; 3423 if (getABIKind() == ARMABIInfo::AAPCS_VFP || 3424 getABIKind() == ARMABIInfo::AAPCS) 3425 ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 3426 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) { 3427 return ABIArgInfo::getIndirect(0, /*ByVal=*/true, 3428 /*Realign=*/TyAlign > ABIAlign); 3429 } 3430 3431 // Otherwise, pass by coercing to a structure of the appropriate size. 3432 llvm::Type* ElemTy; 3433 unsigned SizeRegs; 3434 // FIXME: Try to match the types of the arguments more accurately where 3435 // we can. 3436 if (getContext().getTypeAlign(Ty) <= 32) { 3437 ElemTy = llvm::Type::getInt32Ty(getVMContext()); 3438 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32; 3439 } else { 3440 ElemTy = llvm::Type::getInt64Ty(getVMContext()); 3441 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64; 3442 } 3443 3444 llvm::Type *STy = 3445 llvm::StructType::get(llvm::ArrayType::get(ElemTy, SizeRegs), NULL); 3446 return ABIArgInfo::getDirect(STy); 3447} 3448 3449static bool isIntegerLikeType(QualType Ty, ASTContext &Context, 3450 llvm::LLVMContext &VMContext) { 3451 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure 3452 // is called integer-like if its size is less than or equal to one word, and 3453 // the offset of each of its addressable sub-fields is zero. 3454 3455 uint64_t Size = Context.getTypeSize(Ty); 3456 3457 // Check that the type fits in a word. 3458 if (Size > 32) 3459 return false; 3460 3461 // FIXME: Handle vector types! 3462 if (Ty->isVectorType()) 3463 return false; 3464 3465 // Float types are never treated as "integer like". 3466 if (Ty->isRealFloatingType()) 3467 return false; 3468 3469 // If this is a builtin or pointer type then it is ok. 3470 if (Ty->getAs<BuiltinType>() || Ty->isPointerType()) 3471 return true; 3472 3473 // Small complex integer types are "integer like". 3474 if (const ComplexType *CT = Ty->getAs<ComplexType>()) 3475 return isIntegerLikeType(CT->getElementType(), Context, VMContext); 3476 3477 // Single element and zero sized arrays should be allowed, by the definition 3478 // above, but they are not. 3479 3480 // Otherwise, it must be a record type. 3481 const RecordType *RT = Ty->getAs<RecordType>(); 3482 if (!RT) return false; 3483 3484 // Ignore records with flexible arrays. 3485 const RecordDecl *RD = RT->getDecl(); 3486 if (RD->hasFlexibleArrayMember()) 3487 return false; 3488 3489 // Check that all sub-fields are at offset 0, and are themselves "integer 3490 // like". 3491 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 3492 3493 bool HadField = false; 3494 unsigned idx = 0; 3495 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3496 i != e; ++i, ++idx) { 3497 const FieldDecl *FD = *i; 3498 3499 // Bit-fields are not addressable, we only need to verify they are "integer 3500 // like". We still have to disallow a subsequent non-bitfield, for example: 3501 // struct { int : 0; int x } 3502 // is non-integer like according to gcc. 3503 if (FD->isBitField()) { 3504 if (!RD->isUnion()) 3505 HadField = true; 3506 3507 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3508 return false; 3509 3510 continue; 3511 } 3512 3513 // Check if this field is at offset 0. 3514 if (Layout.getFieldOffset(idx) != 0) 3515 return false; 3516 3517 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3518 return false; 3519 3520 // Only allow at most one field in a structure. This doesn't match the 3521 // wording above, but follows gcc in situations with a field following an 3522 // empty structure. 3523 if (!RD->isUnion()) { 3524 if (HadField) 3525 return false; 3526 3527 HadField = true; 3528 } 3529 } 3530 3531 return true; 3532} 3533 3534ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy) const { 3535 if (RetTy->isVoidType()) 3536 return ABIArgInfo::getIgnore(); 3537 3538 // Large vector types should be returned via memory. 3539 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) 3540 return ABIArgInfo::getIndirect(0); 3541 3542 if (!isAggregateTypeForABI(RetTy)) { 3543 // Treat an enum type as its underlying type. 3544 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 3545 RetTy = EnumTy->getDecl()->getIntegerType(); 3546 3547 return (RetTy->isPromotableIntegerType() ? 3548 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3549 } 3550 3551 // Structures with either a non-trivial destructor or a non-trivial 3552 // copy constructor are always indirect. 3553 if (isRecordReturnIndirect(RetTy, getCXXABI())) 3554 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3555 3556 // Are we following APCS? 3557 if (getABIKind() == APCS) { 3558 if (isEmptyRecord(getContext(), RetTy, false)) 3559 return ABIArgInfo::getIgnore(); 3560 3561 // Complex types are all returned as packed integers. 3562 // 3563 // FIXME: Consider using 2 x vector types if the back end handles them 3564 // correctly. 3565 if (RetTy->isAnyComplexType()) 3566 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 3567 getContext().getTypeSize(RetTy))); 3568 3569 // Integer like structures are returned in r0. 3570 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) { 3571 // Return in the smallest viable integer type. 3572 uint64_t Size = getContext().getTypeSize(RetTy); 3573 if (Size <= 8) 3574 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3575 if (Size <= 16) 3576 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3577 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3578 } 3579 3580 // Otherwise return in memory. 3581 return ABIArgInfo::getIndirect(0); 3582 } 3583 3584 // Otherwise this is an AAPCS variant. 3585 3586 if (isEmptyRecord(getContext(), RetTy, true)) 3587 return ABIArgInfo::getIgnore(); 3588 3589 // Check for homogeneous aggregates with AAPCS-VFP. 3590 if (getABIKind() == AAPCS_VFP) { 3591 const Type *Base = 0; 3592 if (isHomogeneousAggregate(RetTy, Base, getContext())) { 3593 assert(Base && "Base class should be set for homogeneous aggregate"); 3594 // Homogeneous Aggregates are returned directly. 3595 return ABIArgInfo::getDirect(); 3596 } 3597 } 3598 3599 // Aggregates <= 4 bytes are returned in r0; other aggregates 3600 // are returned indirectly. 3601 uint64_t Size = getContext().getTypeSize(RetTy); 3602 if (Size <= 32) { 3603 // Return in the smallest viable integer type. 3604 if (Size <= 8) 3605 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3606 if (Size <= 16) 3607 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3608 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3609 } 3610 3611 return ABIArgInfo::getIndirect(0); 3612} 3613 3614/// isIllegalVector - check whether Ty is an illegal vector type. 3615bool ARMABIInfo::isIllegalVectorType(QualType Ty) const { 3616 if (const VectorType *VT = Ty->getAs<VectorType>()) { 3617 // Check whether VT is legal. 3618 unsigned NumElements = VT->getNumElements(); 3619 uint64_t Size = getContext().getTypeSize(VT); 3620 // NumElements should be power of 2. 3621 if ((NumElements & (NumElements - 1)) != 0) 3622 return true; 3623 // Size should be greater than 32 bits. 3624 return Size <= 32; 3625 } 3626 return false; 3627} 3628 3629llvm::Value *ARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3630 CodeGenFunction &CGF) const { 3631 llvm::Type *BP = CGF.Int8PtrTy; 3632 llvm::Type *BPP = CGF.Int8PtrPtrTy; 3633 3634 CGBuilderTy &Builder = CGF.Builder; 3635 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 3636 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 3637 3638 if (isEmptyRecord(getContext(), Ty, true)) { 3639 // These are ignored for parameter passing purposes. 3640 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 3641 return Builder.CreateBitCast(Addr, PTy); 3642 } 3643 3644 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8; 3645 uint64_t TyAlign = CGF.getContext().getTypeAlign(Ty) / 8; 3646 bool IsIndirect = false; 3647 3648 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for 3649 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte. 3650 if (getABIKind() == ARMABIInfo::AAPCS_VFP || 3651 getABIKind() == ARMABIInfo::AAPCS) 3652 TyAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 3653 else 3654 TyAlign = 4; 3655 // Use indirect if size of the illegal vector is bigger than 16 bytes. 3656 if (isIllegalVectorType(Ty) && Size > 16) { 3657 IsIndirect = true; 3658 Size = 4; 3659 TyAlign = 4; 3660 } 3661 3662 // Handle address alignment for ABI alignment > 4 bytes. 3663 if (TyAlign > 4) { 3664 assert((TyAlign & (TyAlign - 1)) == 0 && 3665 "Alignment is not power of 2!"); 3666 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int32Ty); 3667 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt32(TyAlign - 1)); 3668 AddrAsInt = Builder.CreateAnd(AddrAsInt, Builder.getInt32(~(TyAlign - 1))); 3669 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align"); 3670 } 3671 3672 uint64_t Offset = 3673 llvm::RoundUpToAlignment(Size, 4); 3674 llvm::Value *NextAddr = 3675 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 3676 "ap.next"); 3677 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 3678 3679 if (IsIndirect) 3680 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP)); 3681 else if (TyAlign < CGF.getContext().getTypeAlign(Ty) / 8) { 3682 // We can't directly cast ap.cur to pointer to a vector type, since ap.cur 3683 // may not be correctly aligned for the vector type. We create an aligned 3684 // temporary space and copy the content over from ap.cur to the temporary 3685 // space. This is necessary if the natural alignment of the type is greater 3686 // than the ABI alignment. 3687 llvm::Type *I8PtrTy = Builder.getInt8PtrTy(); 3688 CharUnits CharSize = getContext().getTypeSizeInChars(Ty); 3689 llvm::Value *AlignedTemp = CGF.CreateTempAlloca(CGF.ConvertType(Ty), 3690 "var.align"); 3691 llvm::Value *Dst = Builder.CreateBitCast(AlignedTemp, I8PtrTy); 3692 llvm::Value *Src = Builder.CreateBitCast(Addr, I8PtrTy); 3693 Builder.CreateMemCpy(Dst, Src, 3694 llvm::ConstantInt::get(CGF.IntPtrTy, CharSize.getQuantity()), 3695 TyAlign, false); 3696 Addr = AlignedTemp; //The content is in aligned location. 3697 } 3698 llvm::Type *PTy = 3699 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 3700 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 3701 3702 return AddrTyped; 3703} 3704 3705namespace { 3706 3707class NaClARMABIInfo : public ABIInfo { 3708 public: 3709 NaClARMABIInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3710 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, Kind) {} 3711 virtual void computeInfo(CGFunctionInfo &FI) const; 3712 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3713 CodeGenFunction &CGF) const; 3714 private: 3715 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 3716 ARMABIInfo NInfo; // Used for everything else. 3717}; 3718 3719class NaClARMTargetCodeGenInfo : public TargetCodeGenInfo { 3720 public: 3721 NaClARMTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3722 : TargetCodeGenInfo(new NaClARMABIInfo(CGT, Kind)) {} 3723}; 3724 3725} 3726 3727void NaClARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 3728 if (FI.getASTCallingConvention() == CC_PnaclCall) 3729 PInfo.computeInfo(FI); 3730 else 3731 static_cast<const ABIInfo&>(NInfo).computeInfo(FI); 3732} 3733 3734llvm::Value *NaClARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3735 CodeGenFunction &CGF) const { 3736 // Always use the native convention; calling pnacl-style varargs functions 3737 // is unsupported. 3738 return static_cast<const ABIInfo&>(NInfo).EmitVAArg(VAListAddr, Ty, CGF); 3739} 3740 3741//===----------------------------------------------------------------------===// 3742// AArch64 ABI Implementation 3743//===----------------------------------------------------------------------===// 3744 3745namespace { 3746 3747class AArch64ABIInfo : public ABIInfo { 3748public: 3749 AArch64ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 3750 3751private: 3752 // The AArch64 PCS is explicit about return types and argument types being 3753 // handled identically, so we don't need to draw a distinction between 3754 // Argument and Return classification. 3755 ABIArgInfo classifyGenericType(QualType Ty, int &FreeIntRegs, 3756 int &FreeVFPRegs) const; 3757 3758 ABIArgInfo tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded, bool IsInt, 3759 llvm::Type *DirectTy = 0) const; 3760 3761 virtual void computeInfo(CGFunctionInfo &FI) const; 3762 3763 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3764 CodeGenFunction &CGF) const; 3765}; 3766 3767class AArch64TargetCodeGenInfo : public TargetCodeGenInfo { 3768public: 3769 AArch64TargetCodeGenInfo(CodeGenTypes &CGT) 3770 :TargetCodeGenInfo(new AArch64ABIInfo(CGT)) {} 3771 3772 const AArch64ABIInfo &getABIInfo() const { 3773 return static_cast<const AArch64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 3774 } 3775 3776 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 3777 return 31; 3778 } 3779 3780 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3781 llvm::Value *Address) const { 3782 // 0-31 are x0-x30 and sp: 8 bytes each 3783 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 3784 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 31); 3785 3786 // 64-95 are v0-v31: 16 bytes each 3787 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 3788 AssignToArrayRange(CGF.Builder, Address, Sixteen8, 64, 95); 3789 3790 return false; 3791 } 3792 3793}; 3794 3795} 3796 3797void AArch64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 3798 int FreeIntRegs = 8, FreeVFPRegs = 8; 3799 3800 FI.getReturnInfo() = classifyGenericType(FI.getReturnType(), 3801 FreeIntRegs, FreeVFPRegs); 3802 3803 FreeIntRegs = FreeVFPRegs = 8; 3804 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3805 it != ie; ++it) { 3806 it->info = classifyGenericType(it->type, FreeIntRegs, FreeVFPRegs); 3807 3808 } 3809} 3810 3811ABIArgInfo 3812AArch64ABIInfo::tryUseRegs(QualType Ty, int &FreeRegs, int RegsNeeded, 3813 bool IsInt, llvm::Type *DirectTy) const { 3814 if (FreeRegs >= RegsNeeded) { 3815 FreeRegs -= RegsNeeded; 3816 return ABIArgInfo::getDirect(DirectTy); 3817 } 3818 3819 llvm::Type *Padding = 0; 3820 3821 // We need padding so that later arguments don't get filled in anyway. That 3822 // wouldn't happen if only ByVal arguments followed in the same category, but 3823 // a large structure will simply seem to be a pointer as far as LLVM is 3824 // concerned. 3825 if (FreeRegs > 0) { 3826 if (IsInt) 3827 Padding = llvm::Type::getInt64Ty(getVMContext()); 3828 else 3829 Padding = llvm::Type::getFloatTy(getVMContext()); 3830 3831 // Either [N x i64] or [N x float]. 3832 Padding = llvm::ArrayType::get(Padding, FreeRegs); 3833 FreeRegs = 0; 3834 } 3835 3836 return ABIArgInfo::getIndirect(getContext().getTypeAlign(Ty) / 8, 3837 /*IsByVal=*/ true, /*Realign=*/ false, 3838 Padding); 3839} 3840 3841 3842ABIArgInfo AArch64ABIInfo::classifyGenericType(QualType Ty, 3843 int &FreeIntRegs, 3844 int &FreeVFPRegs) const { 3845 // Can only occurs for return, but harmless otherwise. 3846 if (Ty->isVoidType()) 3847 return ABIArgInfo::getIgnore(); 3848 3849 // Large vector types should be returned via memory. There's no such concept 3850 // in the ABI, but they'd be over 16 bytes anyway so no matter how they're 3851 // classified they'd go into memory (see B.3). 3852 if (Ty->isVectorType() && getContext().getTypeSize(Ty) > 128) { 3853 if (FreeIntRegs > 0) 3854 --FreeIntRegs; 3855 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3856 } 3857 3858 // All non-aggregate LLVM types have a concrete ABI representation so they can 3859 // be passed directly. After this block we're guaranteed to be in a 3860 // complicated case. 3861 if (!isAggregateTypeForABI(Ty)) { 3862 // Treat an enum type as its underlying type. 3863 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3864 Ty = EnumTy->getDecl()->getIntegerType(); 3865 3866 if (Ty->isFloatingType() || Ty->isVectorType()) 3867 return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ false); 3868 3869 assert(getContext().getTypeSize(Ty) <= 128 && 3870 "unexpectedly large scalar type"); 3871 3872 int RegsNeeded = getContext().getTypeSize(Ty) > 64 ? 2 : 1; 3873 3874 // If the type may need padding registers to ensure "alignment", we must be 3875 // careful when this is accounted for. Increasing the effective size covers 3876 // all cases. 3877 if (getContext().getTypeAlign(Ty) == 128) 3878 RegsNeeded += FreeIntRegs % 2 != 0; 3879 3880 return tryUseRegs(Ty, FreeIntRegs, RegsNeeded, /*IsInt=*/ true); 3881 } 3882 3883 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) { 3884 if (FreeIntRegs > 0 && RAA == CGCXXABI::RAA_Indirect) 3885 --FreeIntRegs; 3886 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 3887 } 3888 3889 if (isEmptyRecord(getContext(), Ty, true)) { 3890 if (!getContext().getLangOpts().CPlusPlus) { 3891 // Empty structs outside C++ mode are a GNU extension, so no ABI can 3892 // possibly tell us what to do. It turns out (I believe) that GCC ignores 3893 // the object for parameter-passsing purposes. 3894 return ABIArgInfo::getIgnore(); 3895 } 3896 3897 // The combination of C++98 9p5 (sizeof(struct) != 0) and the pseudocode 3898 // description of va_arg in the PCS require that an empty struct does 3899 // actually occupy space for parameter-passing. I'm hoping for a 3900 // clarification giving an explicit paragraph to point to in future. 3901 return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ 1, /*IsInt=*/ true, 3902 llvm::Type::getInt8Ty(getVMContext())); 3903 } 3904 3905 // Homogeneous vector aggregates get passed in registers or on the stack. 3906 const Type *Base = 0; 3907 uint64_t NumMembers = 0; 3908 if (isHomogeneousAggregate(Ty, Base, getContext(), &NumMembers)) { 3909 assert(Base && "Base class should be set for homogeneous aggregate"); 3910 // Homogeneous aggregates are passed and returned directly. 3911 return tryUseRegs(Ty, FreeVFPRegs, /*RegsNeeded=*/ NumMembers, 3912 /*IsInt=*/ false); 3913 } 3914 3915 uint64_t Size = getContext().getTypeSize(Ty); 3916 if (Size <= 128) { 3917 // Small structs can use the same direct type whether they're in registers 3918 // or on the stack. 3919 llvm::Type *BaseTy; 3920 unsigned NumBases; 3921 int SizeInRegs = (Size + 63) / 64; 3922 3923 if (getContext().getTypeAlign(Ty) == 128) { 3924 BaseTy = llvm::Type::getIntNTy(getVMContext(), 128); 3925 NumBases = 1; 3926 3927 // If the type may need padding registers to ensure "alignment", we must 3928 // be careful when this is accounted for. Increasing the effective size 3929 // covers all cases. 3930 SizeInRegs += FreeIntRegs % 2 != 0; 3931 } else { 3932 BaseTy = llvm::Type::getInt64Ty(getVMContext()); 3933 NumBases = SizeInRegs; 3934 } 3935 llvm::Type *DirectTy = llvm::ArrayType::get(BaseTy, NumBases); 3936 3937 return tryUseRegs(Ty, FreeIntRegs, /*RegsNeeded=*/ SizeInRegs, 3938 /*IsInt=*/ true, DirectTy); 3939 } 3940 3941 // If the aggregate is > 16 bytes, it's passed and returned indirectly. In 3942 // LLVM terms the return uses an "sret" pointer, but that's handled elsewhere. 3943 --FreeIntRegs; 3944 return ABIArgInfo::getIndirect(0, /* byVal = */ false); 3945} 3946 3947llvm::Value *AArch64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3948 CodeGenFunction &CGF) const { 3949 // The AArch64 va_list type and handling is specified in the Procedure Call 3950 // Standard, section B.4: 3951 // 3952 // struct { 3953 // void *__stack; 3954 // void *__gr_top; 3955 // void *__vr_top; 3956 // int __gr_offs; 3957 // int __vr_offs; 3958 // }; 3959 3960 assert(!CGF.CGM.getDataLayout().isBigEndian() 3961 && "va_arg not implemented for big-endian AArch64"); 3962 3963 int FreeIntRegs = 8, FreeVFPRegs = 8; 3964 Ty = CGF.getContext().getCanonicalType(Ty); 3965 ABIArgInfo AI = classifyGenericType(Ty, FreeIntRegs, FreeVFPRegs); 3966 3967 llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg"); 3968 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 3969 llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack"); 3970 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 3971 3972 llvm::Value *reg_offs_p = 0, *reg_offs = 0; 3973 int reg_top_index; 3974 int RegSize; 3975 if (FreeIntRegs < 8) { 3976 assert(FreeVFPRegs == 8 && "Arguments never split between int & VFP regs"); 3977 // 3 is the field number of __gr_offs 3978 reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 3, "gr_offs_p"); 3979 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs"); 3980 reg_top_index = 1; // field number for __gr_top 3981 RegSize = 8 * (8 - FreeIntRegs); 3982 } else { 3983 assert(FreeVFPRegs < 8 && "Argument must go in VFP or int regs"); 3984 // 4 is the field number of __vr_offs. 3985 reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 4, "vr_offs_p"); 3986 reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs"); 3987 reg_top_index = 2; // field number for __vr_top 3988 RegSize = 16 * (8 - FreeVFPRegs); 3989 } 3990 3991 //======================================= 3992 // Find out where argument was passed 3993 //======================================= 3994 3995 // If reg_offs >= 0 we're already using the stack for this type of 3996 // argument. We don't want to keep updating reg_offs (in case it overflows, 3997 // though anyone passing 2GB of arguments, each at most 16 bytes, deserves 3998 // whatever they get). 3999 llvm::Value *UsingStack = 0; 4000 UsingStack = CGF.Builder.CreateICmpSGE(reg_offs, 4001 llvm::ConstantInt::get(CGF.Int32Ty, 0)); 4002 4003 CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock); 4004 4005 // Otherwise, at least some kind of argument could go in these registers, the 4006 // quesiton is whether this particular type is too big. 4007 CGF.EmitBlock(MaybeRegBlock); 4008 4009 // Integer arguments may need to correct register alignment (for example a 4010 // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we 4011 // align __gr_offs to calculate the potential address. 4012 if (FreeIntRegs < 8 && AI.isDirect() && getContext().getTypeAlign(Ty) > 64) { 4013 int Align = getContext().getTypeAlign(Ty) / 8; 4014 4015 reg_offs = CGF.Builder.CreateAdd(reg_offs, 4016 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1), 4017 "align_regoffs"); 4018 reg_offs = CGF.Builder.CreateAnd(reg_offs, 4019 llvm::ConstantInt::get(CGF.Int32Ty, -Align), 4020 "aligned_regoffs"); 4021 } 4022 4023 // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list. 4024 llvm::Value *NewOffset = 0; 4025 NewOffset = CGF.Builder.CreateAdd(reg_offs, 4026 llvm::ConstantInt::get(CGF.Int32Ty, RegSize), 4027 "new_reg_offs"); 4028 CGF.Builder.CreateStore(NewOffset, reg_offs_p); 4029 4030 // Now we're in a position to decide whether this argument really was in 4031 // registers or not. 4032 llvm::Value *InRegs = 0; 4033 InRegs = CGF.Builder.CreateICmpSLE(NewOffset, 4034 llvm::ConstantInt::get(CGF.Int32Ty, 0), 4035 "inreg"); 4036 4037 CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock); 4038 4039 //======================================= 4040 // Argument was in registers 4041 //======================================= 4042 4043 // Now we emit the code for if the argument was originally passed in 4044 // registers. First start the appropriate block: 4045 CGF.EmitBlock(InRegBlock); 4046 4047 llvm::Value *reg_top_p = 0, *reg_top = 0; 4048 reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index, "reg_top_p"); 4049 reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top"); 4050 llvm::Value *BaseAddr = CGF.Builder.CreateGEP(reg_top, reg_offs); 4051 llvm::Value *RegAddr = 0; 4052 llvm::Type *MemTy = llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty)); 4053 4054 if (!AI.isDirect()) { 4055 // If it's been passed indirectly (actually a struct), whatever we find from 4056 // stored registers or on the stack will actually be a struct **. 4057 MemTy = llvm::PointerType::getUnqual(MemTy); 4058 } 4059 4060 const Type *Base = 0; 4061 uint64_t NumMembers; 4062 if (isHomogeneousAggregate(Ty, Base, getContext(), &NumMembers) 4063 && NumMembers > 1) { 4064 // Homogeneous aggregates passed in registers will have their elements split 4065 // and stored 16-bytes apart regardless of size (they're notionally in qN, 4066 // qN+1, ...). We reload and store into a temporary local variable 4067 // contiguously. 4068 assert(AI.isDirect() && "Homogeneous aggregates should be passed directly"); 4069 llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0)); 4070 llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers); 4071 llvm::Value *Tmp = CGF.CreateTempAlloca(HFATy); 4072 4073 for (unsigned i = 0; i < NumMembers; ++i) { 4074 llvm::Value *BaseOffset = llvm::ConstantInt::get(CGF.Int32Ty, 16 * i); 4075 llvm::Value *LoadAddr = CGF.Builder.CreateGEP(BaseAddr, BaseOffset); 4076 LoadAddr = CGF.Builder.CreateBitCast(LoadAddr, 4077 llvm::PointerType::getUnqual(BaseTy)); 4078 llvm::Value *StoreAddr = CGF.Builder.CreateStructGEP(Tmp, i); 4079 4080 llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr); 4081 CGF.Builder.CreateStore(Elem, StoreAddr); 4082 } 4083 4084 RegAddr = CGF.Builder.CreateBitCast(Tmp, MemTy); 4085 } else { 4086 // Otherwise the object is contiguous in memory 4087 RegAddr = CGF.Builder.CreateBitCast(BaseAddr, MemTy); 4088 } 4089 4090 CGF.EmitBranch(ContBlock); 4091 4092 //======================================= 4093 // Argument was on the stack 4094 //======================================= 4095 CGF.EmitBlock(OnStackBlock); 4096 4097 llvm::Value *stack_p = 0, *OnStackAddr = 0; 4098 stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "stack_p"); 4099 OnStackAddr = CGF.Builder.CreateLoad(stack_p, "stack"); 4100 4101 // Again, stack arguments may need realigmnent. In this case both integer and 4102 // floating-point ones might be affected. 4103 if (AI.isDirect() && getContext().getTypeAlign(Ty) > 64) { 4104 int Align = getContext().getTypeAlign(Ty) / 8; 4105 4106 OnStackAddr = CGF.Builder.CreatePtrToInt(OnStackAddr, CGF.Int64Ty); 4107 4108 OnStackAddr = CGF.Builder.CreateAdd(OnStackAddr, 4109 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1), 4110 "align_stack"); 4111 OnStackAddr = CGF.Builder.CreateAnd(OnStackAddr, 4112 llvm::ConstantInt::get(CGF.Int64Ty, -Align), 4113 "align_stack"); 4114 4115 OnStackAddr = CGF.Builder.CreateIntToPtr(OnStackAddr, CGF.Int8PtrTy); 4116 } 4117 4118 uint64_t StackSize; 4119 if (AI.isDirect()) 4120 StackSize = getContext().getTypeSize(Ty) / 8; 4121 else 4122 StackSize = 8; 4123 4124 // All stack slots are 8 bytes 4125 StackSize = llvm::RoundUpToAlignment(StackSize, 8); 4126 4127 llvm::Value *StackSizeC = llvm::ConstantInt::get(CGF.Int32Ty, StackSize); 4128 llvm::Value *NewStack = CGF.Builder.CreateGEP(OnStackAddr, StackSizeC, 4129 "new_stack"); 4130 4131 // Write the new value of __stack for the next call to va_arg 4132 CGF.Builder.CreateStore(NewStack, stack_p); 4133 4134 OnStackAddr = CGF.Builder.CreateBitCast(OnStackAddr, MemTy); 4135 4136 CGF.EmitBranch(ContBlock); 4137 4138 //======================================= 4139 // Tidy up 4140 //======================================= 4141 CGF.EmitBlock(ContBlock); 4142 4143 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(MemTy, 2, "vaarg.addr"); 4144 ResAddr->addIncoming(RegAddr, InRegBlock); 4145 ResAddr->addIncoming(OnStackAddr, OnStackBlock); 4146 4147 if (AI.isDirect()) 4148 return ResAddr; 4149 4150 return CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"); 4151} 4152 4153//===----------------------------------------------------------------------===// 4154// NVPTX ABI Implementation 4155//===----------------------------------------------------------------------===// 4156 4157namespace { 4158 4159class NVPTXABIInfo : public ABIInfo { 4160public: 4161 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4162 4163 ABIArgInfo classifyReturnType(QualType RetTy) const; 4164 ABIArgInfo classifyArgumentType(QualType Ty) const; 4165 4166 virtual void computeInfo(CGFunctionInfo &FI) const; 4167 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4168 CodeGenFunction &CFG) const; 4169}; 4170 4171class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo { 4172public: 4173 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT) 4174 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {} 4175 4176 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4177 CodeGen::CodeGenModule &M) const; 4178private: 4179 static void addKernelMetadata(llvm::Function *F); 4180}; 4181 4182ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const { 4183 if (RetTy->isVoidType()) 4184 return ABIArgInfo::getIgnore(); 4185 if (isAggregateTypeForABI(RetTy)) 4186 return ABIArgInfo::getIndirect(0); 4187 return ABIArgInfo::getDirect(); 4188} 4189 4190ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const { 4191 if (isAggregateTypeForABI(Ty)) 4192 return ABIArgInfo::getIndirect(0); 4193 4194 return ABIArgInfo::getDirect(); 4195} 4196 4197void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const { 4198 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4199 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4200 it != ie; ++it) 4201 it->info = classifyArgumentType(it->type); 4202 4203 // Always honor user-specified calling convention. 4204 if (FI.getCallingConvention() != llvm::CallingConv::C) 4205 return; 4206 4207 FI.setEffectiveCallingConvention(getRuntimeCC()); 4208} 4209 4210llvm::Value *NVPTXABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4211 CodeGenFunction &CFG) const { 4212 llvm_unreachable("NVPTX does not support varargs"); 4213} 4214 4215void NVPTXTargetCodeGenInfo:: 4216SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4217 CodeGen::CodeGenModule &M) const{ 4218 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4219 if (!FD) return; 4220 4221 llvm::Function *F = cast<llvm::Function>(GV); 4222 4223 // Perform special handling in OpenCL mode 4224 if (M.getLangOpts().OpenCL) { 4225 // Use OpenCL function attributes to check for kernel functions 4226 // By default, all functions are device functions 4227 if (FD->hasAttr<OpenCLKernelAttr>()) { 4228 // OpenCL __kernel functions get kernel metadata 4229 addKernelMetadata(F); 4230 // And kernel functions are not subject to inlining 4231 F->addFnAttr(llvm::Attribute::NoInline); 4232 } 4233 } 4234 4235 // Perform special handling in CUDA mode. 4236 if (M.getLangOpts().CUDA) { 4237 // CUDA __global__ functions get a kernel metadata entry. Since 4238 // __global__ functions cannot be called from the device, we do not 4239 // need to set the noinline attribute. 4240 if (FD->getAttr<CUDAGlobalAttr>()) 4241 addKernelMetadata(F); 4242 } 4243} 4244 4245void NVPTXTargetCodeGenInfo::addKernelMetadata(llvm::Function *F) { 4246 llvm::Module *M = F->getParent(); 4247 llvm::LLVMContext &Ctx = M->getContext(); 4248 4249 // Get "nvvm.annotations" metadata node 4250 llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations"); 4251 4252 // Create !{<func-ref>, metadata !"kernel", i32 1} node 4253 llvm::SmallVector<llvm::Value *, 3> MDVals; 4254 MDVals.push_back(F); 4255 MDVals.push_back(llvm::MDString::get(Ctx, "kernel")); 4256 MDVals.push_back(llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), 1)); 4257 4258 // Append metadata to nvvm.annotations 4259 MD->addOperand(llvm::MDNode::get(Ctx, MDVals)); 4260} 4261 4262} 4263 4264//===----------------------------------------------------------------------===// 4265// SystemZ ABI Implementation 4266//===----------------------------------------------------------------------===// 4267 4268namespace { 4269 4270class SystemZABIInfo : public ABIInfo { 4271public: 4272 SystemZABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4273 4274 bool isPromotableIntegerType(QualType Ty) const; 4275 bool isCompoundType(QualType Ty) const; 4276 bool isFPArgumentType(QualType Ty) const; 4277 4278 ABIArgInfo classifyReturnType(QualType RetTy) const; 4279 ABIArgInfo classifyArgumentType(QualType ArgTy) const; 4280 4281 virtual void computeInfo(CGFunctionInfo &FI) const { 4282 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4283 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4284 it != ie; ++it) 4285 it->info = classifyArgumentType(it->type); 4286 } 4287 4288 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4289 CodeGenFunction &CGF) const; 4290}; 4291 4292class SystemZTargetCodeGenInfo : public TargetCodeGenInfo { 4293public: 4294 SystemZTargetCodeGenInfo(CodeGenTypes &CGT) 4295 : TargetCodeGenInfo(new SystemZABIInfo(CGT)) {} 4296}; 4297 4298} 4299 4300bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const { 4301 // Treat an enum type as its underlying type. 4302 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4303 Ty = EnumTy->getDecl()->getIntegerType(); 4304 4305 // Promotable integer types are required to be promoted by the ABI. 4306 if (Ty->isPromotableIntegerType()) 4307 return true; 4308 4309 // 32-bit values must also be promoted. 4310 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 4311 switch (BT->getKind()) { 4312 case BuiltinType::Int: 4313 case BuiltinType::UInt: 4314 return true; 4315 default: 4316 return false; 4317 } 4318 return false; 4319} 4320 4321bool SystemZABIInfo::isCompoundType(QualType Ty) const { 4322 return Ty->isAnyComplexType() || isAggregateTypeForABI(Ty); 4323} 4324 4325bool SystemZABIInfo::isFPArgumentType(QualType Ty) const { 4326 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 4327 switch (BT->getKind()) { 4328 case BuiltinType::Float: 4329 case BuiltinType::Double: 4330 return true; 4331 default: 4332 return false; 4333 } 4334 4335 if (const RecordType *RT = Ty->getAsStructureType()) { 4336 const RecordDecl *RD = RT->getDecl(); 4337 bool Found = false; 4338 4339 // If this is a C++ record, check the bases first. 4340 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 4341 for (CXXRecordDecl::base_class_const_iterator I = CXXRD->bases_begin(), 4342 E = CXXRD->bases_end(); I != E; ++I) { 4343 QualType Base = I->getType(); 4344 4345 // Empty bases don't affect things either way. 4346 if (isEmptyRecord(getContext(), Base, true)) 4347 continue; 4348 4349 if (Found) 4350 return false; 4351 Found = isFPArgumentType(Base); 4352 if (!Found) 4353 return false; 4354 } 4355 4356 // Check the fields. 4357 for (RecordDecl::field_iterator I = RD->field_begin(), 4358 E = RD->field_end(); I != E; ++I) { 4359 const FieldDecl *FD = *I; 4360 4361 // Empty bitfields don't affect things either way. 4362 // Unlike isSingleElementStruct(), empty structure and array fields 4363 // do count. So do anonymous bitfields that aren't zero-sized. 4364 if (FD->isBitField() && FD->getBitWidthValue(getContext()) == 0) 4365 return true; 4366 4367 // Unlike isSingleElementStruct(), arrays do not count. 4368 // Nested isFPArgumentType structures still do though. 4369 if (Found) 4370 return false; 4371 Found = isFPArgumentType(FD->getType()); 4372 if (!Found) 4373 return false; 4374 } 4375 4376 // Unlike isSingleElementStruct(), trailing padding is allowed. 4377 // An 8-byte aligned struct s { float f; } is passed as a double. 4378 return Found; 4379 } 4380 4381 return false; 4382} 4383 4384llvm::Value *SystemZABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4385 CodeGenFunction &CGF) const { 4386 // Assume that va_list type is correct; should be pointer to LLVM type: 4387 // struct { 4388 // i64 __gpr; 4389 // i64 __fpr; 4390 // i8 *__overflow_arg_area; 4391 // i8 *__reg_save_area; 4392 // }; 4393 4394 // Every argument occupies 8 bytes and is passed by preference in either 4395 // GPRs or FPRs. 4396 Ty = CGF.getContext().getCanonicalType(Ty); 4397 ABIArgInfo AI = classifyArgumentType(Ty); 4398 bool InFPRs = isFPArgumentType(Ty); 4399 4400 llvm::Type *APTy = llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty)); 4401 bool IsIndirect = AI.isIndirect(); 4402 unsigned UnpaddedBitSize; 4403 if (IsIndirect) { 4404 APTy = llvm::PointerType::getUnqual(APTy); 4405 UnpaddedBitSize = 64; 4406 } else 4407 UnpaddedBitSize = getContext().getTypeSize(Ty); 4408 unsigned PaddedBitSize = 64; 4409 assert((UnpaddedBitSize <= PaddedBitSize) && "Invalid argument size."); 4410 4411 unsigned PaddedSize = PaddedBitSize / 8; 4412 unsigned Padding = (PaddedBitSize - UnpaddedBitSize) / 8; 4413 4414 unsigned MaxRegs, RegCountField, RegSaveIndex, RegPadding; 4415 if (InFPRs) { 4416 MaxRegs = 4; // Maximum of 4 FPR arguments 4417 RegCountField = 1; // __fpr 4418 RegSaveIndex = 16; // save offset for f0 4419 RegPadding = 0; // floats are passed in the high bits of an FPR 4420 } else { 4421 MaxRegs = 5; // Maximum of 5 GPR arguments 4422 RegCountField = 0; // __gpr 4423 RegSaveIndex = 2; // save offset for r2 4424 RegPadding = Padding; // values are passed in the low bits of a GPR 4425 } 4426 4427 llvm::Value *RegCountPtr = 4428 CGF.Builder.CreateStructGEP(VAListAddr, RegCountField, "reg_count_ptr"); 4429 llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count"); 4430 llvm::Type *IndexTy = RegCount->getType(); 4431 llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs); 4432 llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV, 4433 "fits_in_regs"); 4434 4435 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 4436 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 4437 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 4438 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 4439 4440 // Emit code to load the value if it was passed in registers. 4441 CGF.EmitBlock(InRegBlock); 4442 4443 // Work out the address of an argument register. 4444 llvm::Value *PaddedSizeV = llvm::ConstantInt::get(IndexTy, PaddedSize); 4445 llvm::Value *ScaledRegCount = 4446 CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count"); 4447 llvm::Value *RegBase = 4448 llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize + RegPadding); 4449 llvm::Value *RegOffset = 4450 CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset"); 4451 llvm::Value *RegSaveAreaPtr = 4452 CGF.Builder.CreateStructGEP(VAListAddr, 3, "reg_save_area_ptr"); 4453 llvm::Value *RegSaveArea = 4454 CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area"); 4455 llvm::Value *RawRegAddr = 4456 CGF.Builder.CreateGEP(RegSaveArea, RegOffset, "raw_reg_addr"); 4457 llvm::Value *RegAddr = 4458 CGF.Builder.CreateBitCast(RawRegAddr, APTy, "reg_addr"); 4459 4460 // Update the register count 4461 llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1); 4462 llvm::Value *NewRegCount = 4463 CGF.Builder.CreateAdd(RegCount, One, "reg_count"); 4464 CGF.Builder.CreateStore(NewRegCount, RegCountPtr); 4465 CGF.EmitBranch(ContBlock); 4466 4467 // Emit code to load the value if it was passed in memory. 4468 CGF.EmitBlock(InMemBlock); 4469 4470 // Work out the address of a stack argument. 4471 llvm::Value *OverflowArgAreaPtr = 4472 CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_ptr"); 4473 llvm::Value *OverflowArgArea = 4474 CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"); 4475 llvm::Value *PaddingV = llvm::ConstantInt::get(IndexTy, Padding); 4476 llvm::Value *RawMemAddr = 4477 CGF.Builder.CreateGEP(OverflowArgArea, PaddingV, "raw_mem_addr"); 4478 llvm::Value *MemAddr = 4479 CGF.Builder.CreateBitCast(RawMemAddr, APTy, "mem_addr"); 4480 4481 // Update overflow_arg_area_ptr pointer 4482 llvm::Value *NewOverflowArgArea = 4483 CGF.Builder.CreateGEP(OverflowArgArea, PaddedSizeV, "overflow_arg_area"); 4484 CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr); 4485 CGF.EmitBranch(ContBlock); 4486 4487 // Return the appropriate result. 4488 CGF.EmitBlock(ContBlock); 4489 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(APTy, 2, "va_arg.addr"); 4490 ResAddr->addIncoming(RegAddr, InRegBlock); 4491 ResAddr->addIncoming(MemAddr, InMemBlock); 4492 4493 if (IsIndirect) 4494 return CGF.Builder.CreateLoad(ResAddr, "indirect_arg"); 4495 4496 return ResAddr; 4497} 4498 4499bool X86_32TargetCodeGenInfo::isStructReturnInRegABI( 4500 const llvm::Triple &Triple, const CodeGenOptions &Opts) { 4501 assert(Triple.getArch() == llvm::Triple::x86); 4502 4503 switch (Opts.getStructReturnConvention()) { 4504 case CodeGenOptions::SRCK_Default: 4505 break; 4506 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return 4507 return false; 4508 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return 4509 return true; 4510 } 4511 4512 if (Triple.isOSDarwin()) 4513 return true; 4514 4515 switch (Triple.getOS()) { 4516 case llvm::Triple::Cygwin: 4517 case llvm::Triple::MinGW32: 4518 case llvm::Triple::AuroraUX: 4519 case llvm::Triple::DragonFly: 4520 case llvm::Triple::FreeBSD: 4521 case llvm::Triple::OpenBSD: 4522 case llvm::Triple::Bitrig: 4523 case llvm::Triple::Win32: 4524 return true; 4525 default: 4526 return false; 4527 } 4528} 4529 4530ABIArgInfo SystemZABIInfo::classifyReturnType(QualType RetTy) const { 4531 if (RetTy->isVoidType()) 4532 return ABIArgInfo::getIgnore(); 4533 if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64) 4534 return ABIArgInfo::getIndirect(0); 4535 return (isPromotableIntegerType(RetTy) ? 4536 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4537} 4538 4539ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const { 4540 // Handle the generic C++ ABI. 4541 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 4542 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 4543 4544 // Integers and enums are extended to full register width. 4545 if (isPromotableIntegerType(Ty)) 4546 return ABIArgInfo::getExtend(); 4547 4548 // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly. 4549 uint64_t Size = getContext().getTypeSize(Ty); 4550 if (Size != 8 && Size != 16 && Size != 32 && Size != 64) 4551 return ABIArgInfo::getIndirect(0); 4552 4553 // Handle small structures. 4554 if (const RecordType *RT = Ty->getAs<RecordType>()) { 4555 // Structures with flexible arrays have variable length, so really 4556 // fail the size test above. 4557 const RecordDecl *RD = RT->getDecl(); 4558 if (RD->hasFlexibleArrayMember()) 4559 return ABIArgInfo::getIndirect(0); 4560 4561 // The structure is passed as an unextended integer, a float, or a double. 4562 llvm::Type *PassTy; 4563 if (isFPArgumentType(Ty)) { 4564 assert(Size == 32 || Size == 64); 4565 if (Size == 32) 4566 PassTy = llvm::Type::getFloatTy(getVMContext()); 4567 else 4568 PassTy = llvm::Type::getDoubleTy(getVMContext()); 4569 } else 4570 PassTy = llvm::IntegerType::get(getVMContext(), Size); 4571 return ABIArgInfo::getDirect(PassTy); 4572 } 4573 4574 // Non-structure compounds are passed indirectly. 4575 if (isCompoundType(Ty)) 4576 return ABIArgInfo::getIndirect(0); 4577 4578 return ABIArgInfo::getDirect(0); 4579} 4580 4581//===----------------------------------------------------------------------===// 4582// MSP430 ABI Implementation 4583//===----------------------------------------------------------------------===// 4584 4585namespace { 4586 4587class MSP430TargetCodeGenInfo : public TargetCodeGenInfo { 4588public: 4589 MSP430TargetCodeGenInfo(CodeGenTypes &CGT) 4590 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 4591 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4592 CodeGen::CodeGenModule &M) const; 4593}; 4594 4595} 4596 4597void MSP430TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4598 llvm::GlobalValue *GV, 4599 CodeGen::CodeGenModule &M) const { 4600 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 4601 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) { 4602 // Handle 'interrupt' attribute: 4603 llvm::Function *F = cast<llvm::Function>(GV); 4604 4605 // Step 1: Set ISR calling convention. 4606 F->setCallingConv(llvm::CallingConv::MSP430_INTR); 4607 4608 // Step 2: Add attributes goodness. 4609 F->addFnAttr(llvm::Attribute::NoInline); 4610 4611 // Step 3: Emit ISR vector alias. 4612 unsigned Num = attr->getNumber() / 2; 4613 new llvm::GlobalAlias(GV->getType(), llvm::Function::ExternalLinkage, 4614 "__isr_" + Twine(Num), 4615 GV, &M.getModule()); 4616 } 4617 } 4618} 4619 4620//===----------------------------------------------------------------------===// 4621// MIPS ABI Implementation. This works for both little-endian and 4622// big-endian variants. 4623//===----------------------------------------------------------------------===// 4624 4625namespace { 4626class MipsABIInfo : public ABIInfo { 4627 bool IsO32; 4628 unsigned MinABIStackAlignInBytes, StackAlignInBytes; 4629 void CoerceToIntArgs(uint64_t TySize, 4630 SmallVectorImpl<llvm::Type *> &ArgList) const; 4631 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const; 4632 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const; 4633 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const; 4634public: 4635 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) : 4636 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8), 4637 StackAlignInBytes(IsO32 ? 8 : 16) {} 4638 4639 ABIArgInfo classifyReturnType(QualType RetTy) const; 4640 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const; 4641 virtual void computeInfo(CGFunctionInfo &FI) const; 4642 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4643 CodeGenFunction &CGF) const; 4644}; 4645 4646class MIPSTargetCodeGenInfo : public TargetCodeGenInfo { 4647 unsigned SizeOfUnwindException; 4648public: 4649 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32) 4650 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)), 4651 SizeOfUnwindException(IsO32 ? 24 : 32) {} 4652 4653 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 4654 return 29; 4655 } 4656 4657 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4658 CodeGen::CodeGenModule &CGM) const { 4659 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4660 if (!FD) return; 4661 llvm::Function *Fn = cast<llvm::Function>(GV); 4662 if (FD->hasAttr<Mips16Attr>()) { 4663 Fn->addFnAttr("mips16"); 4664 } 4665 else if (FD->hasAttr<NoMips16Attr>()) { 4666 Fn->addFnAttr("nomips16"); 4667 } 4668 } 4669 4670 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4671 llvm::Value *Address) const; 4672 4673 unsigned getSizeOfUnwindException() const { 4674 return SizeOfUnwindException; 4675 } 4676}; 4677} 4678 4679void MipsABIInfo::CoerceToIntArgs(uint64_t TySize, 4680 SmallVectorImpl<llvm::Type *> &ArgList) const { 4681 llvm::IntegerType *IntTy = 4682 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 4683 4684 // Add (TySize / MinABIStackAlignInBytes) args of IntTy. 4685 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N) 4686 ArgList.push_back(IntTy); 4687 4688 // If necessary, add one more integer type to ArgList. 4689 unsigned R = TySize % (MinABIStackAlignInBytes * 8); 4690 4691 if (R) 4692 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R)); 4693} 4694 4695// In N32/64, an aligned double precision floating point field is passed in 4696// a register. 4697llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const { 4698 SmallVector<llvm::Type*, 8> ArgList, IntArgList; 4699 4700 if (IsO32) { 4701 CoerceToIntArgs(TySize, ArgList); 4702 return llvm::StructType::get(getVMContext(), ArgList); 4703 } 4704 4705 if (Ty->isComplexType()) 4706 return CGT.ConvertType(Ty); 4707 4708 const RecordType *RT = Ty->getAs<RecordType>(); 4709 4710 // Unions/vectors are passed in integer registers. 4711 if (!RT || !RT->isStructureOrClassType()) { 4712 CoerceToIntArgs(TySize, ArgList); 4713 return llvm::StructType::get(getVMContext(), ArgList); 4714 } 4715 4716 const RecordDecl *RD = RT->getDecl(); 4717 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 4718 assert(!(TySize % 8) && "Size of structure must be multiple of 8."); 4719 4720 uint64_t LastOffset = 0; 4721 unsigned idx = 0; 4722 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64); 4723 4724 // Iterate over fields in the struct/class and check if there are any aligned 4725 // double fields. 4726 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 4727 i != e; ++i, ++idx) { 4728 const QualType Ty = i->getType(); 4729 const BuiltinType *BT = Ty->getAs<BuiltinType>(); 4730 4731 if (!BT || BT->getKind() != BuiltinType::Double) 4732 continue; 4733 4734 uint64_t Offset = Layout.getFieldOffset(idx); 4735 if (Offset % 64) // Ignore doubles that are not aligned. 4736 continue; 4737 4738 // Add ((Offset - LastOffset) / 64) args of type i64. 4739 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j) 4740 ArgList.push_back(I64); 4741 4742 // Add double type. 4743 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext())); 4744 LastOffset = Offset + 64; 4745 } 4746 4747 CoerceToIntArgs(TySize - LastOffset, IntArgList); 4748 ArgList.append(IntArgList.begin(), IntArgList.end()); 4749 4750 return llvm::StructType::get(getVMContext(), ArgList); 4751} 4752 4753llvm::Type *MipsABIInfo::getPaddingType(uint64_t Align, uint64_t Offset) const { 4754 assert((Offset % MinABIStackAlignInBytes) == 0); 4755 4756 if ((Align - 1) & Offset) 4757 return llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 4758 4759 return 0; 4760} 4761 4762ABIArgInfo 4763MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const { 4764 uint64_t OrigOffset = Offset; 4765 uint64_t TySize = getContext().getTypeSize(Ty); 4766 uint64_t Align = getContext().getTypeAlign(Ty) / 8; 4767 4768 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes), 4769 (uint64_t)StackAlignInBytes); 4770 Offset = llvm::RoundUpToAlignment(Offset, Align); 4771 Offset += llvm::RoundUpToAlignment(TySize, Align * 8) / 8; 4772 4773 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) { 4774 // Ignore empty aggregates. 4775 if (TySize == 0) 4776 return ABIArgInfo::getIgnore(); 4777 4778 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) { 4779 Offset = OrigOffset + MinABIStackAlignInBytes; 4780 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 4781 } 4782 4783 // If we have reached here, aggregates are passed directly by coercing to 4784 // another structure type. Padding is inserted if the offset of the 4785 // aggregate is unaligned. 4786 return ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0, 4787 getPaddingType(Align, OrigOffset)); 4788 } 4789 4790 // Treat an enum type as its underlying type. 4791 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4792 Ty = EnumTy->getDecl()->getIntegerType(); 4793 4794 if (Ty->isPromotableIntegerType()) 4795 return ABIArgInfo::getExtend(); 4796 4797 return ABIArgInfo::getDirect(0, 0, 4798 IsO32 ? 0 : getPaddingType(Align, OrigOffset)); 4799} 4800 4801llvm::Type* 4802MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const { 4803 const RecordType *RT = RetTy->getAs<RecordType>(); 4804 SmallVector<llvm::Type*, 8> RTList; 4805 4806 if (RT && RT->isStructureOrClassType()) { 4807 const RecordDecl *RD = RT->getDecl(); 4808 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 4809 unsigned FieldCnt = Layout.getFieldCount(); 4810 4811 // N32/64 returns struct/classes in floating point registers if the 4812 // following conditions are met: 4813 // 1. The size of the struct/class is no larger than 128-bit. 4814 // 2. The struct/class has one or two fields all of which are floating 4815 // point types. 4816 // 3. The offset of the first field is zero (this follows what gcc does). 4817 // 4818 // Any other composite results are returned in integer registers. 4819 // 4820 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) { 4821 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end(); 4822 for (; b != e; ++b) { 4823 const BuiltinType *BT = b->getType()->getAs<BuiltinType>(); 4824 4825 if (!BT || !BT->isFloatingPoint()) 4826 break; 4827 4828 RTList.push_back(CGT.ConvertType(b->getType())); 4829 } 4830 4831 if (b == e) 4832 return llvm::StructType::get(getVMContext(), RTList, 4833 RD->hasAttr<PackedAttr>()); 4834 4835 RTList.clear(); 4836 } 4837 } 4838 4839 CoerceToIntArgs(Size, RTList); 4840 return llvm::StructType::get(getVMContext(), RTList); 4841} 4842 4843ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const { 4844 uint64_t Size = getContext().getTypeSize(RetTy); 4845 4846 if (RetTy->isVoidType() || Size == 0) 4847 return ABIArgInfo::getIgnore(); 4848 4849 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) { 4850 if (isRecordReturnIndirect(RetTy, getCXXABI())) 4851 return ABIArgInfo::getIndirect(0); 4852 4853 if (Size <= 128) { 4854 if (RetTy->isAnyComplexType()) 4855 return ABIArgInfo::getDirect(); 4856 4857 // O32 returns integer vectors in registers. 4858 if (IsO32 && RetTy->isVectorType() && !RetTy->hasFloatingRepresentation()) 4859 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 4860 4861 if (!IsO32) 4862 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 4863 } 4864 4865 return ABIArgInfo::getIndirect(0); 4866 } 4867 4868 // Treat an enum type as its underlying type. 4869 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 4870 RetTy = EnumTy->getDecl()->getIntegerType(); 4871 4872 return (RetTy->isPromotableIntegerType() ? 4873 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4874} 4875 4876void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const { 4877 ABIArgInfo &RetInfo = FI.getReturnInfo(); 4878 RetInfo = classifyReturnType(FI.getReturnType()); 4879 4880 // Check if a pointer to an aggregate is passed as a hidden argument. 4881 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0; 4882 4883 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4884 it != ie; ++it) 4885 it->info = classifyArgumentType(it->type, Offset); 4886} 4887 4888llvm::Value* MipsABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4889 CodeGenFunction &CGF) const { 4890 llvm::Type *BP = CGF.Int8PtrTy; 4891 llvm::Type *BPP = CGF.Int8PtrPtrTy; 4892 4893 CGBuilderTy &Builder = CGF.Builder; 4894 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 4895 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 4896 int64_t TypeAlign = getContext().getTypeAlign(Ty) / 8; 4897 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 4898 llvm::Value *AddrTyped; 4899 unsigned PtrWidth = getTarget().getPointerWidth(0); 4900 llvm::IntegerType *IntTy = (PtrWidth == 32) ? CGF.Int32Ty : CGF.Int64Ty; 4901 4902 if (TypeAlign > MinABIStackAlignInBytes) { 4903 llvm::Value *AddrAsInt = CGF.Builder.CreatePtrToInt(Addr, IntTy); 4904 llvm::Value *Inc = llvm::ConstantInt::get(IntTy, TypeAlign - 1); 4905 llvm::Value *Mask = llvm::ConstantInt::get(IntTy, -TypeAlign); 4906 llvm::Value *Add = CGF.Builder.CreateAdd(AddrAsInt, Inc); 4907 llvm::Value *And = CGF.Builder.CreateAnd(Add, Mask); 4908 AddrTyped = CGF.Builder.CreateIntToPtr(And, PTy); 4909 } 4910 else 4911 AddrTyped = Builder.CreateBitCast(Addr, PTy); 4912 4913 llvm::Value *AlignedAddr = Builder.CreateBitCast(AddrTyped, BP); 4914 TypeAlign = std::max((unsigned)TypeAlign, MinABIStackAlignInBytes); 4915 uint64_t Offset = 4916 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, TypeAlign); 4917 llvm::Value *NextAddr = 4918 Builder.CreateGEP(AlignedAddr, llvm::ConstantInt::get(IntTy, Offset), 4919 "ap.next"); 4920 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 4921 4922 return AddrTyped; 4923} 4924 4925bool 4926MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 4927 llvm::Value *Address) const { 4928 // This information comes from gcc's implementation, which seems to 4929 // as canonical as it gets. 4930 4931 // Everything on MIPS is 4 bytes. Double-precision FP registers 4932 // are aliased to pairs of single-precision FP registers. 4933 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 4934 4935 // 0-31 are the general purpose registers, $0 - $31. 4936 // 32-63 are the floating-point registers, $f0 - $f31. 4937 // 64 and 65 are the multiply/divide registers, $hi and $lo. 4938 // 66 is the (notional, I think) register for signal-handler return. 4939 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65); 4940 4941 // 67-74 are the floating-point status registers, $fcc0 - $fcc7. 4942 // They are one bit wide and ignored here. 4943 4944 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31. 4945 // (coprocessor 1 is the FP unit) 4946 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31. 4947 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31. 4948 // 176-181 are the DSP accumulator registers. 4949 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181); 4950 return false; 4951} 4952 4953//===----------------------------------------------------------------------===// 4954// TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults. 4955// Currently subclassed only to implement custom OpenCL C function attribute 4956// handling. 4957//===----------------------------------------------------------------------===// 4958 4959namespace { 4960 4961class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo { 4962public: 4963 TCETargetCodeGenInfo(CodeGenTypes &CGT) 4964 : DefaultTargetCodeGenInfo(CGT) {} 4965 4966 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 4967 CodeGen::CodeGenModule &M) const; 4968}; 4969 4970void TCETargetCodeGenInfo::SetTargetAttributes(const Decl *D, 4971 llvm::GlobalValue *GV, 4972 CodeGen::CodeGenModule &M) const { 4973 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 4974 if (!FD) return; 4975 4976 llvm::Function *F = cast<llvm::Function>(GV); 4977 4978 if (M.getLangOpts().OpenCL) { 4979 if (FD->hasAttr<OpenCLKernelAttr>()) { 4980 // OpenCL C Kernel functions are not subject to inlining 4981 F->addFnAttr(llvm::Attribute::NoInline); 4982 4983 if (FD->hasAttr<ReqdWorkGroupSizeAttr>()) { 4984 4985 // Convert the reqd_work_group_size() attributes to metadata. 4986 llvm::LLVMContext &Context = F->getContext(); 4987 llvm::NamedMDNode *OpenCLMetadata = 4988 M.getModule().getOrInsertNamedMetadata("opencl.kernel_wg_size_info"); 4989 4990 SmallVector<llvm::Value*, 5> Operands; 4991 Operands.push_back(F); 4992 4993 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4994 llvm::APInt(32, 4995 FD->getAttr<ReqdWorkGroupSizeAttr>()->getXDim()))); 4996 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4997 llvm::APInt(32, 4998 FD->getAttr<ReqdWorkGroupSizeAttr>()->getYDim()))); 4999 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 5000 llvm::APInt(32, 5001 FD->getAttr<ReqdWorkGroupSizeAttr>()->getZDim()))); 5002 5003 // Add a boolean constant operand for "required" (true) or "hint" (false) 5004 // for implementing the work_group_size_hint attr later. Currently 5005 // always true as the hint is not yet implemented. 5006 Operands.push_back(llvm::ConstantInt::getTrue(Context)); 5007 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands)); 5008 } 5009 } 5010 } 5011} 5012 5013} 5014 5015//===----------------------------------------------------------------------===// 5016// Hexagon ABI Implementation 5017//===----------------------------------------------------------------------===// 5018 5019namespace { 5020 5021class HexagonABIInfo : public ABIInfo { 5022 5023 5024public: 5025 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 5026 5027private: 5028 5029 ABIArgInfo classifyReturnType(QualType RetTy) const; 5030 ABIArgInfo classifyArgumentType(QualType RetTy) const; 5031 5032 virtual void computeInfo(CGFunctionInfo &FI) const; 5033 5034 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 5035 CodeGenFunction &CGF) const; 5036}; 5037 5038class HexagonTargetCodeGenInfo : public TargetCodeGenInfo { 5039public: 5040 HexagonTargetCodeGenInfo(CodeGenTypes &CGT) 5041 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {} 5042 5043 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 5044 return 29; 5045 } 5046}; 5047 5048} 5049 5050void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const { 5051 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 5052 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 5053 it != ie; ++it) 5054 it->info = classifyArgumentType(it->type); 5055} 5056 5057ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const { 5058 if (!isAggregateTypeForABI(Ty)) { 5059 // Treat an enum type as its underlying type. 5060 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 5061 Ty = EnumTy->getDecl()->getIntegerType(); 5062 5063 return (Ty->isPromotableIntegerType() ? 5064 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 5065 } 5066 5067 // Ignore empty records. 5068 if (isEmptyRecord(getContext(), Ty, true)) 5069 return ABIArgInfo::getIgnore(); 5070 5071 if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) 5072 return ABIArgInfo::getIndirect(0, RAA == CGCXXABI::RAA_DirectInMemory); 5073 5074 uint64_t Size = getContext().getTypeSize(Ty); 5075 if (Size > 64) 5076 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 5077 // Pass in the smallest viable integer type. 5078 else if (Size > 32) 5079 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 5080 else if (Size > 16) 5081 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 5082 else if (Size > 8) 5083 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 5084 else 5085 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 5086} 5087 5088ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const { 5089 if (RetTy->isVoidType()) 5090 return ABIArgInfo::getIgnore(); 5091 5092 // Large vector types should be returned via memory. 5093 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64) 5094 return ABIArgInfo::getIndirect(0); 5095 5096 if (!isAggregateTypeForABI(RetTy)) { 5097 // Treat an enum type as its underlying type. 5098 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 5099 RetTy = EnumTy->getDecl()->getIntegerType(); 5100 5101 return (RetTy->isPromotableIntegerType() ? 5102 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 5103 } 5104 5105 // Structures with either a non-trivial destructor or a non-trivial 5106 // copy constructor are always indirect. 5107 if (isRecordReturnIndirect(RetTy, getCXXABI())) 5108 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 5109 5110 if (isEmptyRecord(getContext(), RetTy, true)) 5111 return ABIArgInfo::getIgnore(); 5112 5113 // Aggregates <= 8 bytes are returned in r0; other aggregates 5114 // are returned indirectly. 5115 uint64_t Size = getContext().getTypeSize(RetTy); 5116 if (Size <= 64) { 5117 // Return in the smallest viable integer type. 5118 if (Size <= 8) 5119 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 5120 if (Size <= 16) 5121 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 5122 if (Size <= 32) 5123 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 5124 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 5125 } 5126 5127 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 5128} 5129 5130llvm::Value *HexagonABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 5131 CodeGenFunction &CGF) const { 5132 // FIXME: Need to handle alignment 5133 llvm::Type *BPP = CGF.Int8PtrPtrTy; 5134 5135 CGBuilderTy &Builder = CGF.Builder; 5136 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 5137 "ap"); 5138 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 5139 llvm::Type *PTy = 5140 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 5141 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 5142 5143 uint64_t Offset = 5144 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 4); 5145 llvm::Value *NextAddr = 5146 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 5147 "ap.next"); 5148 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 5149 5150 return AddrTyped; 5151} 5152 5153 5154//===----------------------------------------------------------------------===// 5155// SPARC v9 ABI Implementation. 5156// Based on the SPARC Compliance Definition version 2.4.1. 5157// 5158// Function arguments a mapped to a nominal "parameter array" and promoted to 5159// registers depending on their type. Each argument occupies 8 or 16 bytes in 5160// the array, structs larger than 16 bytes are passed indirectly. 5161// 5162// One case requires special care: 5163// 5164// struct mixed { 5165// int i; 5166// float f; 5167// }; 5168// 5169// When a struct mixed is passed by value, it only occupies 8 bytes in the 5170// parameter array, but the int is passed in an integer register, and the float 5171// is passed in a floating point register. This is represented as two arguments 5172// with the LLVM IR inreg attribute: 5173// 5174// declare void f(i32 inreg %i, float inreg %f) 5175// 5176// The code generator will only allocate 4 bytes from the parameter array for 5177// the inreg arguments. All other arguments are allocated a multiple of 8 5178// bytes. 5179// 5180namespace { 5181class SparcV9ABIInfo : public ABIInfo { 5182public: 5183 SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 5184 5185private: 5186 ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const; 5187 virtual void computeInfo(CGFunctionInfo &FI) const; 5188 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 5189 CodeGenFunction &CGF) const; 5190 5191 // Coercion type builder for structs passed in registers. The coercion type 5192 // serves two purposes: 5193 // 5194 // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned' 5195 // in registers. 5196 // 2. Expose aligned floating point elements as first-level elements, so the 5197 // code generator knows to pass them in floating point registers. 5198 // 5199 // We also compute the InReg flag which indicates that the struct contains 5200 // aligned 32-bit floats. 5201 // 5202 struct CoerceBuilder { 5203 llvm::LLVMContext &Context; 5204 const llvm::DataLayout &DL; 5205 SmallVector<llvm::Type*, 8> Elems; 5206 uint64_t Size; 5207 bool InReg; 5208 5209 CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl) 5210 : Context(c), DL(dl), Size(0), InReg(false) {} 5211 5212 // Pad Elems with integers until Size is ToSize. 5213 void pad(uint64_t ToSize) { 5214 assert(ToSize >= Size && "Cannot remove elements"); 5215 if (ToSize == Size) 5216 return; 5217 5218 // Finish the current 64-bit word. 5219 uint64_t Aligned = llvm::RoundUpToAlignment(Size, 64); 5220 if (Aligned > Size && Aligned <= ToSize) { 5221 Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size)); 5222 Size = Aligned; 5223 } 5224 5225 // Add whole 64-bit words. 5226 while (Size + 64 <= ToSize) { 5227 Elems.push_back(llvm::Type::getInt64Ty(Context)); 5228 Size += 64; 5229 } 5230 5231 // Final in-word padding. 5232 if (Size < ToSize) { 5233 Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size)); 5234 Size = ToSize; 5235 } 5236 } 5237 5238 // Add a floating point element at Offset. 5239 void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) { 5240 // Unaligned floats are treated as integers. 5241 if (Offset % Bits) 5242 return; 5243 // The InReg flag is only required if there are any floats < 64 bits. 5244 if (Bits < 64) 5245 InReg = true; 5246 pad(Offset); 5247 Elems.push_back(Ty); 5248 Size = Offset + Bits; 5249 } 5250 5251 // Add a struct type to the coercion type, starting at Offset (in bits). 5252 void addStruct(uint64_t Offset, llvm::StructType *StrTy) { 5253 const llvm::StructLayout *Layout = DL.getStructLayout(StrTy); 5254 for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) { 5255 llvm::Type *ElemTy = StrTy->getElementType(i); 5256 uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i); 5257 switch (ElemTy->getTypeID()) { 5258 case llvm::Type::StructTyID: 5259 addStruct(ElemOffset, cast<llvm::StructType>(ElemTy)); 5260 break; 5261 case llvm::Type::FloatTyID: 5262 addFloat(ElemOffset, ElemTy, 32); 5263 break; 5264 case llvm::Type::DoubleTyID: 5265 addFloat(ElemOffset, ElemTy, 64); 5266 break; 5267 case llvm::Type::FP128TyID: 5268 addFloat(ElemOffset, ElemTy, 128); 5269 break; 5270 case llvm::Type::PointerTyID: 5271 if (ElemOffset % 64 == 0) { 5272 pad(ElemOffset); 5273 Elems.push_back(ElemTy); 5274 Size += 64; 5275 } 5276 break; 5277 default: 5278 break; 5279 } 5280 } 5281 } 5282 5283 // Check if Ty is a usable substitute for the coercion type. 5284 bool isUsableType(llvm::StructType *Ty) const { 5285 if (Ty->getNumElements() != Elems.size()) 5286 return false; 5287 for (unsigned i = 0, e = Elems.size(); i != e; ++i) 5288 if (Elems[i] != Ty->getElementType(i)) 5289 return false; 5290 return true; 5291 } 5292 5293 // Get the coercion type as a literal struct type. 5294 llvm::Type *getType() const { 5295 if (Elems.size() == 1) 5296 return Elems.front(); 5297 else 5298 return llvm::StructType::get(Context, Elems); 5299 } 5300 }; 5301}; 5302} // end anonymous namespace 5303 5304ABIArgInfo 5305SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const { 5306 if (Ty->isVoidType()) 5307 return ABIArgInfo::getIgnore(); 5308 5309 uint64_t Size = getContext().getTypeSize(Ty); 5310 5311 // Anything too big to fit in registers is passed with an explicit indirect 5312 // pointer / sret pointer. 5313 if (Size > SizeLimit) 5314 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 5315 5316 // Treat an enum type as its underlying type. 5317 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 5318 Ty = EnumTy->getDecl()->getIntegerType(); 5319 5320 // Integer types smaller than a register are extended. 5321 if (Size < 64 && Ty->isIntegerType()) 5322 return ABIArgInfo::getExtend(); 5323 5324 // Other non-aggregates go in registers. 5325 if (!isAggregateTypeForABI(Ty)) 5326 return ABIArgInfo::getDirect(); 5327 5328 // This is a small aggregate type that should be passed in registers. 5329 // Build a coercion type from the LLVM struct type. 5330 llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty)); 5331 if (!StrTy) 5332 return ABIArgInfo::getDirect(); 5333 5334 CoerceBuilder CB(getVMContext(), getDataLayout()); 5335 CB.addStruct(0, StrTy); 5336 CB.pad(llvm::RoundUpToAlignment(CB.DL.getTypeSizeInBits(StrTy), 64)); 5337 5338 // Try to use the original type for coercion. 5339 llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType(); 5340 5341 if (CB.InReg) 5342 return ABIArgInfo::getDirectInReg(CoerceTy); 5343 else 5344 return ABIArgInfo::getDirect(CoerceTy); 5345} 5346 5347llvm::Value *SparcV9ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 5348 CodeGenFunction &CGF) const { 5349 ABIArgInfo AI = classifyType(Ty, 16 * 8); 5350 llvm::Type *ArgTy = CGT.ConvertType(Ty); 5351 if (AI.canHaveCoerceToType() && !AI.getCoerceToType()) 5352 AI.setCoerceToType(ArgTy); 5353 5354 llvm::Type *BPP = CGF.Int8PtrPtrTy; 5355 CGBuilderTy &Builder = CGF.Builder; 5356 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 5357 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 5358 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy); 5359 llvm::Value *ArgAddr; 5360 unsigned Stride; 5361 5362 switch (AI.getKind()) { 5363 case ABIArgInfo::Expand: 5364 llvm_unreachable("Unsupported ABI kind for va_arg"); 5365 5366 case ABIArgInfo::Extend: 5367 Stride = 8; 5368 ArgAddr = Builder 5369 .CreateConstGEP1_32(Addr, 8 - getDataLayout().getTypeAllocSize(ArgTy), 5370 "extend"); 5371 break; 5372 5373 case ABIArgInfo::Direct: 5374 Stride = getDataLayout().getTypeAllocSize(AI.getCoerceToType()); 5375 ArgAddr = Addr; 5376 break; 5377 5378 case ABIArgInfo::Indirect: 5379 Stride = 8; 5380 ArgAddr = Builder.CreateBitCast(Addr, 5381 llvm::PointerType::getUnqual(ArgPtrTy), 5382 "indirect"); 5383 ArgAddr = Builder.CreateLoad(ArgAddr, "indirect.arg"); 5384 break; 5385 5386 case ABIArgInfo::Ignore: 5387 return llvm::UndefValue::get(ArgPtrTy); 5388 } 5389 5390 // Update VAList. 5391 Addr = Builder.CreateConstGEP1_32(Addr, Stride, "ap.next"); 5392 Builder.CreateStore(Addr, VAListAddrAsBPP); 5393 5394 return Builder.CreatePointerCast(ArgAddr, ArgPtrTy, "arg.addr"); 5395} 5396 5397void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const { 5398 FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8); 5399 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 5400 it != ie; ++it) 5401 it->info = classifyType(it->type, 16 * 8); 5402} 5403 5404namespace { 5405class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo { 5406public: 5407 SparcV9TargetCodeGenInfo(CodeGenTypes &CGT) 5408 : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {} 5409}; 5410} // end anonymous namespace 5411 5412 5413//===----------------------------------------------------------------------===// 5414// Xcore ABI Implementation 5415//===----------------------------------------------------------------------===// 5416namespace { 5417class XCoreABIInfo : public DefaultABIInfo { 5418public: 5419 XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 5420 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 5421 CodeGenFunction &CGF) const; 5422}; 5423 5424class XcoreTargetCodeGenInfo : public TargetCodeGenInfo { 5425public: 5426 XcoreTargetCodeGenInfo(CodeGenTypes &CGT) 5427 :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {} 5428}; 5429} // end anonymous namespace 5430 5431llvm::Value *XCoreABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 5432 CodeGenFunction &CGF) const { 5433 ABIArgInfo AI = classifyArgumentType(Ty); 5434 CGBuilderTy &Builder = CGF.Builder; 5435 llvm::Type *ArgTy = CGT.ConvertType(Ty); 5436 if (AI.canHaveCoerceToType() && !AI.getCoerceToType()) 5437 AI.setCoerceToType(ArgTy); 5438 5439 // handle the VAList 5440 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, 5441 CGF.Int8PtrPtrTy); 5442 llvm::Value *AP = Builder.CreateLoad(VAListAddrAsBPP); 5443 llvm::Value *APN = Builder.CreateConstGEP1_32(AP, 4); 5444 Builder.CreateStore(APN, VAListAddrAsBPP); 5445 5446 // handle the argument 5447 llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy); 5448 switch (AI.getKind()) { 5449 case ABIArgInfo::Expand: 5450 llvm_unreachable("Unsupported ABI kind for va_arg"); 5451 case ABIArgInfo::Ignore: 5452 return llvm::UndefValue::get(ArgPtrTy); 5453 case ABIArgInfo::Extend: 5454 case ABIArgInfo::Direct: 5455 return Builder.CreatePointerCast(AP, ArgPtrTy); 5456 case ABIArgInfo::Indirect: 5457 llvm::Value *ArgAddr; 5458 ArgAddr = Builder.CreateBitCast(AP, llvm::PointerType::getUnqual(ArgPtrTy)); 5459 ArgAddr = Builder.CreateLoad(ArgAddr); 5460 return Builder.CreatePointerCast(ArgAddr, ArgPtrTy); 5461 } 5462 llvm_unreachable("Unknown ABI kind"); 5463} 5464 5465//===----------------------------------------------------------------------===// 5466// Driver code 5467//===----------------------------------------------------------------------===// 5468 5469const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() { 5470 if (TheTargetCodeGenInfo) 5471 return *TheTargetCodeGenInfo; 5472 5473 const llvm::Triple &Triple = getTarget().getTriple(); 5474 switch (Triple.getArch()) { 5475 default: 5476 return *(TheTargetCodeGenInfo = new DefaultTargetCodeGenInfo(Types)); 5477 5478 case llvm::Triple::le32: 5479 return *(TheTargetCodeGenInfo = new PNaClTargetCodeGenInfo(Types)); 5480 case llvm::Triple::mips: 5481 case llvm::Triple::mipsel: 5482 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, true)); 5483 5484 case llvm::Triple::mips64: 5485 case llvm::Triple::mips64el: 5486 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, false)); 5487 5488 case llvm::Triple::aarch64: 5489 return *(TheTargetCodeGenInfo = new AArch64TargetCodeGenInfo(Types)); 5490 5491 case llvm::Triple::arm: 5492 case llvm::Triple::thumb: 5493 { 5494 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS; 5495 if (strcmp(getTarget().getABI(), "apcs-gnu") == 0) 5496 Kind = ARMABIInfo::APCS; 5497 else if (CodeGenOpts.FloatABI == "hard" || 5498 (CodeGenOpts.FloatABI != "soft" && 5499 Triple.getEnvironment() == llvm::Triple::GNUEABIHF)) 5500 Kind = ARMABIInfo::AAPCS_VFP; 5501 5502 switch (Triple.getOS()) { 5503 case llvm::Triple::NaCl: 5504 return *(TheTargetCodeGenInfo = 5505 new NaClARMTargetCodeGenInfo(Types, Kind)); 5506 default: 5507 return *(TheTargetCodeGenInfo = 5508 new ARMTargetCodeGenInfo(Types, Kind)); 5509 } 5510 } 5511 5512 case llvm::Triple::ppc: 5513 return *(TheTargetCodeGenInfo = new PPC32TargetCodeGenInfo(Types)); 5514 case llvm::Triple::ppc64: 5515 if (Triple.isOSBinFormatELF()) 5516 return *(TheTargetCodeGenInfo = new PPC64_SVR4_TargetCodeGenInfo(Types)); 5517 else 5518 return *(TheTargetCodeGenInfo = new PPC64TargetCodeGenInfo(Types)); 5519 case llvm::Triple::ppc64le: 5520 assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!"); 5521 return *(TheTargetCodeGenInfo = new PPC64_SVR4_TargetCodeGenInfo(Types)); 5522 5523 case llvm::Triple::nvptx: 5524 case llvm::Triple::nvptx64: 5525 return *(TheTargetCodeGenInfo = new NVPTXTargetCodeGenInfo(Types)); 5526 5527 case llvm::Triple::msp430: 5528 return *(TheTargetCodeGenInfo = new MSP430TargetCodeGenInfo(Types)); 5529 5530 case llvm::Triple::systemz: 5531 return *(TheTargetCodeGenInfo = new SystemZTargetCodeGenInfo(Types)); 5532 5533 case llvm::Triple::tce: 5534 return *(TheTargetCodeGenInfo = new TCETargetCodeGenInfo(Types)); 5535 5536 case llvm::Triple::x86: { 5537 bool IsDarwinVectorABI = Triple.isOSDarwin(); 5538 bool IsSmallStructInRegABI = 5539 X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts); 5540 bool IsWin32FloatStructABI = (Triple.getOS() == llvm::Triple::Win32); 5541 5542 if (Triple.getOS() == llvm::Triple::Win32) { 5543 return *(TheTargetCodeGenInfo = 5544 new WinX86_32TargetCodeGenInfo(Types, 5545 IsDarwinVectorABI, IsSmallStructInRegABI, 5546 IsWin32FloatStructABI, 5547 CodeGenOpts.NumRegisterParameters)); 5548 } else { 5549 return *(TheTargetCodeGenInfo = 5550 new X86_32TargetCodeGenInfo(Types, 5551 IsDarwinVectorABI, IsSmallStructInRegABI, 5552 IsWin32FloatStructABI, 5553 CodeGenOpts.NumRegisterParameters)); 5554 } 5555 } 5556 5557 case llvm::Triple::x86_64: { 5558 bool HasAVX = strcmp(getTarget().getABI(), "avx") == 0; 5559 5560 switch (Triple.getOS()) { 5561 case llvm::Triple::Win32: 5562 case llvm::Triple::MinGW32: 5563 case llvm::Triple::Cygwin: 5564 return *(TheTargetCodeGenInfo = new WinX86_64TargetCodeGenInfo(Types)); 5565 case llvm::Triple::NaCl: 5566 return *(TheTargetCodeGenInfo = new NaClX86_64TargetCodeGenInfo(Types, 5567 HasAVX)); 5568 default: 5569 return *(TheTargetCodeGenInfo = new X86_64TargetCodeGenInfo(Types, 5570 HasAVX)); 5571 } 5572 } 5573 case llvm::Triple::hexagon: 5574 return *(TheTargetCodeGenInfo = new HexagonTargetCodeGenInfo(Types)); 5575 case llvm::Triple::sparcv9: 5576 return *(TheTargetCodeGenInfo = new SparcV9TargetCodeGenInfo(Types)); 5577 case llvm::Triple::xcore: 5578 return *(TheTargetCodeGenInfo = new XcoreTargetCodeGenInfo(Types)); 5579 5580 } 5581} 5582