TargetInfo.cpp revision b6932692234eba2472ef85a38434496e9342fd38
1//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// These classes wrap the information about a call or function 11// definition used to handle ABI compliancy. 12// 13//===----------------------------------------------------------------------===// 14 15#include "TargetInfo.h" 16#include "ABIInfo.h" 17#include "CodeGenFunction.h" 18#include "clang/AST/RecordLayout.h" 19#include "clang/Frontend/CodeGenOptions.h" 20#include "llvm/Type.h" 21#include "llvm/DataLayout.h" 22#include "llvm/ADT/Triple.h" 23#include "llvm/Support/raw_ostream.h" 24using namespace clang; 25using namespace CodeGen; 26 27static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, 28 llvm::Value *Array, 29 llvm::Value *Value, 30 unsigned FirstIndex, 31 unsigned LastIndex) { 32 // Alternatively, we could emit this as a loop in the source. 33 for (unsigned I = FirstIndex; I <= LastIndex; ++I) { 34 llvm::Value *Cell = Builder.CreateConstInBoundsGEP1_32(Array, I); 35 Builder.CreateStore(Value, Cell); 36 } 37} 38 39static bool isAggregateTypeForABI(QualType T) { 40 return CodeGenFunction::hasAggregateLLVMType(T) || 41 T->isMemberFunctionPointerType(); 42} 43 44ABIInfo::~ABIInfo() {} 45 46ASTContext &ABIInfo::getContext() const { 47 return CGT.getContext(); 48} 49 50llvm::LLVMContext &ABIInfo::getVMContext() const { 51 return CGT.getLLVMContext(); 52} 53 54const llvm::DataLayout &ABIInfo::getDataLayout() const { 55 return CGT.getDataLayout(); 56} 57 58 59void ABIArgInfo::dump() const { 60 raw_ostream &OS = llvm::errs(); 61 OS << "(ABIArgInfo Kind="; 62 switch (TheKind) { 63 case Direct: 64 OS << "Direct Type="; 65 if (llvm::Type *Ty = getCoerceToType()) 66 Ty->print(OS); 67 else 68 OS << "null"; 69 break; 70 case Extend: 71 OS << "Extend"; 72 break; 73 case Ignore: 74 OS << "Ignore"; 75 break; 76 case Indirect: 77 OS << "Indirect Align=" << getIndirectAlign() 78 << " ByVal=" << getIndirectByVal() 79 << " Realign=" << getIndirectRealign(); 80 break; 81 case Expand: 82 OS << "Expand"; 83 break; 84 } 85 OS << ")\n"; 86} 87 88TargetCodeGenInfo::~TargetCodeGenInfo() { delete Info; } 89 90// If someone can figure out a general rule for this, that would be great. 91// It's probably just doomed to be platform-dependent, though. 92unsigned TargetCodeGenInfo::getSizeOfUnwindException() const { 93 // Verified for: 94 // x86-64 FreeBSD, Linux, Darwin 95 // x86-32 FreeBSD, Linux, Darwin 96 // PowerPC Linux, Darwin 97 // ARM Darwin (*not* EABI) 98 return 32; 99} 100 101bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args, 102 const FunctionNoProtoType *fnType) const { 103 // The following conventions are known to require this to be false: 104 // x86_stdcall 105 // MIPS 106 // For everything else, we just prefer false unless we opt out. 107 return false; 108} 109 110static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays); 111 112/// isEmptyField - Return true iff a the field is "empty", that is it 113/// is an unnamed bit-field or an (array of) empty record(s). 114static bool isEmptyField(ASTContext &Context, const FieldDecl *FD, 115 bool AllowArrays) { 116 if (FD->isUnnamedBitfield()) 117 return true; 118 119 QualType FT = FD->getType(); 120 121 // Constant arrays of empty records count as empty, strip them off. 122 // Constant arrays of zero length always count as empty. 123 if (AllowArrays) 124 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 125 if (AT->getSize() == 0) 126 return true; 127 FT = AT->getElementType(); 128 } 129 130 const RecordType *RT = FT->getAs<RecordType>(); 131 if (!RT) 132 return false; 133 134 // C++ record fields are never empty, at least in the Itanium ABI. 135 // 136 // FIXME: We should use a predicate for whether this behavior is true in the 137 // current ABI. 138 if (isa<CXXRecordDecl>(RT->getDecl())) 139 return false; 140 141 return isEmptyRecord(Context, FT, AllowArrays); 142} 143 144/// isEmptyRecord - Return true iff a structure contains only empty 145/// fields. Note that a structure with a flexible array member is not 146/// considered empty. 147static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) { 148 const RecordType *RT = T->getAs<RecordType>(); 149 if (!RT) 150 return 0; 151 const RecordDecl *RD = RT->getDecl(); 152 if (RD->hasFlexibleArrayMember()) 153 return false; 154 155 // If this is a C++ record, check the bases first. 156 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 157 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 158 e = CXXRD->bases_end(); i != e; ++i) 159 if (!isEmptyRecord(Context, i->getType(), true)) 160 return false; 161 162 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 163 i != e; ++i) 164 if (!isEmptyField(Context, *i, AllowArrays)) 165 return false; 166 return true; 167} 168 169/// hasNonTrivialDestructorOrCopyConstructor - Determine if a type has either 170/// a non-trivial destructor or a non-trivial copy constructor. 171static bool hasNonTrivialDestructorOrCopyConstructor(const RecordType *RT) { 172 const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); 173 if (!RD) 174 return false; 175 176 return !RD->hasTrivialDestructor() || !RD->hasTrivialCopyConstructor(); 177} 178 179/// isRecordWithNonTrivialDestructorOrCopyConstructor - Determine if a type is 180/// a record type with either a non-trivial destructor or a non-trivial copy 181/// constructor. 182static bool isRecordWithNonTrivialDestructorOrCopyConstructor(QualType T) { 183 const RecordType *RT = T->getAs<RecordType>(); 184 if (!RT) 185 return false; 186 187 return hasNonTrivialDestructorOrCopyConstructor(RT); 188} 189 190/// isSingleElementStruct - Determine if a structure is a "single 191/// element struct", i.e. it has exactly one non-empty field or 192/// exactly one field which is itself a single element 193/// struct. Structures with flexible array members are never 194/// considered single element structs. 195/// 196/// \return The field declaration for the single non-empty field, if 197/// it exists. 198static const Type *isSingleElementStruct(QualType T, ASTContext &Context) { 199 const RecordType *RT = T->getAsStructureType(); 200 if (!RT) 201 return 0; 202 203 const RecordDecl *RD = RT->getDecl(); 204 if (RD->hasFlexibleArrayMember()) 205 return 0; 206 207 const Type *Found = 0; 208 209 // If this is a C++ record, check the bases first. 210 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 211 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 212 e = CXXRD->bases_end(); i != e; ++i) { 213 // Ignore empty records. 214 if (isEmptyRecord(Context, i->getType(), true)) 215 continue; 216 217 // If we already found an element then this isn't a single-element struct. 218 if (Found) 219 return 0; 220 221 // If this is non-empty and not a single element struct, the composite 222 // cannot be a single element struct. 223 Found = isSingleElementStruct(i->getType(), Context); 224 if (!Found) 225 return 0; 226 } 227 } 228 229 // Check for single element. 230 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 231 i != e; ++i) { 232 const FieldDecl *FD = *i; 233 QualType FT = FD->getType(); 234 235 // Ignore empty fields. 236 if (isEmptyField(Context, FD, true)) 237 continue; 238 239 // If we already found an element then this isn't a single-element 240 // struct. 241 if (Found) 242 return 0; 243 244 // Treat single element arrays as the element. 245 while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { 246 if (AT->getSize().getZExtValue() != 1) 247 break; 248 FT = AT->getElementType(); 249 } 250 251 if (!isAggregateTypeForABI(FT)) { 252 Found = FT.getTypePtr(); 253 } else { 254 Found = isSingleElementStruct(FT, Context); 255 if (!Found) 256 return 0; 257 } 258 } 259 260 // We don't consider a struct a single-element struct if it has 261 // padding beyond the element type. 262 if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T)) 263 return 0; 264 265 return Found; 266} 267 268static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) { 269 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() && 270 !Ty->isAnyComplexType() && !Ty->isEnumeralType() && 271 !Ty->isBlockPointerType()) 272 return false; 273 274 uint64_t Size = Context.getTypeSize(Ty); 275 return Size == 32 || Size == 64; 276} 277 278/// canExpandIndirectArgument - Test whether an argument type which is to be 279/// passed indirectly (on the stack) would have the equivalent layout if it was 280/// expanded into separate arguments. If so, we prefer to do the latter to avoid 281/// inhibiting optimizations. 282/// 283// FIXME: This predicate is missing many cases, currently it just follows 284// llvm-gcc (checks that all fields are 32-bit or 64-bit primitive types). We 285// should probably make this smarter, or better yet make the LLVM backend 286// capable of handling it. 287static bool canExpandIndirectArgument(QualType Ty, ASTContext &Context) { 288 // We can only expand structure types. 289 const RecordType *RT = Ty->getAs<RecordType>(); 290 if (!RT) 291 return false; 292 293 // We can only expand (C) structures. 294 // 295 // FIXME: This needs to be generalized to handle classes as well. 296 const RecordDecl *RD = RT->getDecl(); 297 if (!RD->isStruct() || isa<CXXRecordDecl>(RD)) 298 return false; 299 300 uint64_t Size = 0; 301 302 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 303 i != e; ++i) { 304 const FieldDecl *FD = *i; 305 306 if (!is32Or64BitBasicType(FD->getType(), Context)) 307 return false; 308 309 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know 310 // how to expand them yet, and the predicate for telling if a bitfield still 311 // counts as "basic" is more complicated than what we were doing previously. 312 if (FD->isBitField()) 313 return false; 314 315 Size += Context.getTypeSize(FD->getType()); 316 } 317 318 // Make sure there are not any holes in the struct. 319 if (Size != Context.getTypeSize(Ty)) 320 return false; 321 322 return true; 323} 324 325namespace { 326/// DefaultABIInfo - The default implementation for ABI specific 327/// details. This implementation provides information which results in 328/// self-consistent and sensible LLVM IR generation, but does not 329/// conform to any particular ABI. 330class DefaultABIInfo : public ABIInfo { 331public: 332 DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 333 334 ABIArgInfo classifyReturnType(QualType RetTy) const; 335 ABIArgInfo classifyArgumentType(QualType RetTy) const; 336 337 virtual void computeInfo(CGFunctionInfo &FI) const { 338 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 339 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 340 it != ie; ++it) 341 it->info = classifyArgumentType(it->type); 342 } 343 344 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 345 CodeGenFunction &CGF) const; 346}; 347 348class DefaultTargetCodeGenInfo : public TargetCodeGenInfo { 349public: 350 DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 351 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 352}; 353 354llvm::Value *DefaultABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 355 CodeGenFunction &CGF) const { 356 return 0; 357} 358 359ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const { 360 if (isAggregateTypeForABI(Ty)) { 361 // Records with non trivial destructors/constructors should not be passed 362 // by value. 363 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 364 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 365 366 return ABIArgInfo::getIndirect(0); 367 } 368 369 // Treat an enum type as its underlying type. 370 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 371 Ty = EnumTy->getDecl()->getIntegerType(); 372 373 return (Ty->isPromotableIntegerType() ? 374 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 375} 376 377ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const { 378 if (RetTy->isVoidType()) 379 return ABIArgInfo::getIgnore(); 380 381 if (isAggregateTypeForABI(RetTy)) 382 return ABIArgInfo::getIndirect(0); 383 384 // Treat an enum type as its underlying type. 385 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 386 RetTy = EnumTy->getDecl()->getIntegerType(); 387 388 return (RetTy->isPromotableIntegerType() ? 389 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 390} 391 392//===----------------------------------------------------------------------===// 393// le32/PNaCl bitcode ABI Implementation 394//===----------------------------------------------------------------------===// 395 396class PNaClABIInfo : public ABIInfo { 397 public: 398 PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 399 400 ABIArgInfo classifyReturnType(QualType RetTy) const; 401 ABIArgInfo classifyArgumentType(QualType RetTy, unsigned &FreeRegs) const; 402 403 virtual void computeInfo(CGFunctionInfo &FI) const; 404 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 405 CodeGenFunction &CGF) const; 406}; 407 408class PNaClTargetCodeGenInfo : public TargetCodeGenInfo { 409 public: 410 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 411 : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {} 412}; 413 414void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const { 415 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 416 417 unsigned FreeRegs = FI.getHasRegParm() ? FI.getRegParm() : 0; 418 419 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 420 it != ie; ++it) 421 it->info = classifyArgumentType(it->type, FreeRegs); 422 } 423 424llvm::Value *PNaClABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 425 CodeGenFunction &CGF) const { 426 return 0; 427} 428 429ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty, 430 unsigned &FreeRegs) const { 431 if (isAggregateTypeForABI(Ty)) { 432 // Records with non trivial destructors/constructors should not be passed 433 // by value. 434 FreeRegs = 0; 435 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 436 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 437 438 return ABIArgInfo::getIndirect(0); 439 } 440 441 // Treat an enum type as its underlying type. 442 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 443 Ty = EnumTy->getDecl()->getIntegerType(); 444 445 ABIArgInfo BaseInfo = (Ty->isPromotableIntegerType() ? 446 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 447 448 // Regparm regs hold 32 bits. 449 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 450 if (SizeInRegs == 0) return BaseInfo; 451 if (SizeInRegs > FreeRegs) { 452 FreeRegs = 0; 453 return BaseInfo; 454 } 455 FreeRegs -= SizeInRegs; 456 return BaseInfo.isDirect() ? 457 ABIArgInfo::getDirectInReg(BaseInfo.getCoerceToType()) : 458 ABIArgInfo::getExtendInReg(BaseInfo.getCoerceToType()); 459} 460 461ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const { 462 if (RetTy->isVoidType()) 463 return ABIArgInfo::getIgnore(); 464 465 if (isAggregateTypeForABI(RetTy)) 466 return ABIArgInfo::getIndirect(0); 467 468 // Treat an enum type as its underlying type. 469 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 470 RetTy = EnumTy->getDecl()->getIntegerType(); 471 472 return (RetTy->isPromotableIntegerType() ? 473 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 474} 475 476/// UseX86_MMXType - Return true if this is an MMX type that should use the 477/// special x86_mmx type. 478bool UseX86_MMXType(llvm::Type *IRType) { 479 // If the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>, use the 480 // special x86_mmx type. 481 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 && 482 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() && 483 IRType->getScalarSizeInBits() != 64; 484} 485 486static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 487 StringRef Constraint, 488 llvm::Type* Ty) { 489 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) 490 return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); 491 return Ty; 492} 493 494//===----------------------------------------------------------------------===// 495// X86-32 ABI Implementation 496//===----------------------------------------------------------------------===// 497 498/// X86_32ABIInfo - The X86-32 ABI information. 499class X86_32ABIInfo : public ABIInfo { 500 enum Class { 501 Integer, 502 Float 503 }; 504 505 static const unsigned MinABIStackAlignInBytes = 4; 506 507 bool IsDarwinVectorABI; 508 bool IsSmallStructInRegABI; 509 bool IsMMXDisabled; 510 bool IsWin32FloatStructABI; 511 unsigned DefaultNumRegisterParameters; 512 513 static bool isRegisterSize(unsigned Size) { 514 return (Size == 8 || Size == 16 || Size == 32 || Size == 64); 515 } 516 517 static bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context, 518 unsigned callingConvention); 519 520 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 521 /// such that the argument will be passed in memory. 522 ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, 523 unsigned &FreeRegs) const; 524 525 /// \brief Return the alignment to use for the given type on the stack. 526 unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const; 527 528 Class classify(QualType Ty) const; 529 ABIArgInfo classifyReturnType(QualType RetTy, 530 unsigned callingConvention) const; 531 ABIArgInfo classifyArgumentType(QualType RetTy, unsigned &FreeRegs, 532 bool IsFastCall) const; 533 bool shouldUseInReg(QualType Ty, unsigned &FreeRegs, 534 bool IsFastCall) const; 535 536public: 537 538 virtual void computeInfo(CGFunctionInfo &FI) const; 539 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 540 CodeGenFunction &CGF) const; 541 542 X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool m, bool w, 543 unsigned r) 544 : ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p), 545 IsMMXDisabled(m), IsWin32FloatStructABI(w), 546 DefaultNumRegisterParameters(r) {} 547}; 548 549class X86_32TargetCodeGenInfo : public TargetCodeGenInfo { 550public: 551 X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, 552 bool d, bool p, bool m, bool w, unsigned r) 553 :TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, m, w, r)) {} 554 555 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 556 CodeGen::CodeGenModule &CGM) const; 557 558 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 559 // Darwin uses different dwarf register numbers for EH. 560 if (CGM.isTargetDarwin()) return 5; 561 562 return 4; 563 } 564 565 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 566 llvm::Value *Address) const; 567 568 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 569 StringRef Constraint, 570 llvm::Type* Ty) const { 571 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 572 } 573 574}; 575 576} 577 578/// shouldReturnTypeInRegister - Determine if the given type should be 579/// passed in a register (for the Darwin ABI). 580bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty, 581 ASTContext &Context, 582 unsigned callingConvention) { 583 uint64_t Size = Context.getTypeSize(Ty); 584 585 // Type must be register sized. 586 if (!isRegisterSize(Size)) 587 return false; 588 589 if (Ty->isVectorType()) { 590 // 64- and 128- bit vectors inside structures are not returned in 591 // registers. 592 if (Size == 64 || Size == 128) 593 return false; 594 595 return true; 596 } 597 598 // If this is a builtin, pointer, enum, complex type, member pointer, or 599 // member function pointer it is ok. 600 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() || 601 Ty->isAnyComplexType() || Ty->isEnumeralType() || 602 Ty->isBlockPointerType() || Ty->isMemberPointerType()) 603 return true; 604 605 // Arrays are treated like records. 606 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) 607 return shouldReturnTypeInRegister(AT->getElementType(), Context, 608 callingConvention); 609 610 // Otherwise, it must be a record type. 611 const RecordType *RT = Ty->getAs<RecordType>(); 612 if (!RT) return false; 613 614 // FIXME: Traverse bases here too. 615 616 // For thiscall conventions, structures will never be returned in 617 // a register. This is for compatibility with the MSVC ABI 618 if (callingConvention == llvm::CallingConv::X86_ThisCall && 619 RT->isStructureType()) { 620 return false; 621 } 622 623 // Structure types are passed in register if all fields would be 624 // passed in a register. 625 for (RecordDecl::field_iterator i = RT->getDecl()->field_begin(), 626 e = RT->getDecl()->field_end(); i != e; ++i) { 627 const FieldDecl *FD = *i; 628 629 // Empty fields are ignored. 630 if (isEmptyField(Context, FD, true)) 631 continue; 632 633 // Check fields recursively. 634 if (!shouldReturnTypeInRegister(FD->getType(), Context, 635 callingConvention)) 636 return false; 637 } 638 return true; 639} 640 641ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy, 642 unsigned callingConvention) const { 643 if (RetTy->isVoidType()) 644 return ABIArgInfo::getIgnore(); 645 646 if (const VectorType *VT = RetTy->getAs<VectorType>()) { 647 // On Darwin, some vectors are returned in registers. 648 if (IsDarwinVectorABI) { 649 uint64_t Size = getContext().getTypeSize(RetTy); 650 651 // 128-bit vectors are a special case; they are returned in 652 // registers and we need to make sure to pick a type the LLVM 653 // backend will like. 654 if (Size == 128) 655 return ABIArgInfo::getDirect(llvm::VectorType::get( 656 llvm::Type::getInt64Ty(getVMContext()), 2)); 657 658 // Always return in register if it fits in a general purpose 659 // register, or if it is 64 bits and has a single element. 660 if ((Size == 8 || Size == 16 || Size == 32) || 661 (Size == 64 && VT->getNumElements() == 1)) 662 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 663 Size)); 664 665 return ABIArgInfo::getIndirect(0); 666 } 667 668 return ABIArgInfo::getDirect(); 669 } 670 671 if (isAggregateTypeForABI(RetTy)) { 672 if (const RecordType *RT = RetTy->getAs<RecordType>()) { 673 // Structures with either a non-trivial destructor or a non-trivial 674 // copy constructor are always indirect. 675 if (hasNonTrivialDestructorOrCopyConstructor(RT)) 676 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 677 678 // Structures with flexible arrays are always indirect. 679 if (RT->getDecl()->hasFlexibleArrayMember()) 680 return ABIArgInfo::getIndirect(0); 681 } 682 683 // If specified, structs and unions are always indirect. 684 if (!IsSmallStructInRegABI && !RetTy->isAnyComplexType()) 685 return ABIArgInfo::getIndirect(0); 686 687 // Small structures which are register sized are generally returned 688 // in a register. 689 if (X86_32ABIInfo::shouldReturnTypeInRegister(RetTy, getContext(), 690 callingConvention)) { 691 uint64_t Size = getContext().getTypeSize(RetTy); 692 693 // As a special-case, if the struct is a "single-element" struct, and 694 // the field is of type "float" or "double", return it in a 695 // floating-point register. (MSVC does not apply this special case.) 696 // We apply a similar transformation for pointer types to improve the 697 // quality of the generated IR. 698 if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) 699 if ((!IsWin32FloatStructABI && SeltTy->isRealFloatingType()) 700 || SeltTy->hasPointerRepresentation()) 701 return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); 702 703 // FIXME: We should be able to narrow this integer in cases with dead 704 // padding. 705 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size)); 706 } 707 708 return ABIArgInfo::getIndirect(0); 709 } 710 711 // Treat an enum type as its underlying type. 712 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 713 RetTy = EnumTy->getDecl()->getIntegerType(); 714 715 return (RetTy->isPromotableIntegerType() ? 716 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 717} 718 719static bool isSSEVectorType(ASTContext &Context, QualType Ty) { 720 return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128; 721} 722 723static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) { 724 const RecordType *RT = Ty->getAs<RecordType>(); 725 if (!RT) 726 return 0; 727 const RecordDecl *RD = RT->getDecl(); 728 729 // If this is a C++ record, check the bases first. 730 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) 731 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 732 e = CXXRD->bases_end(); i != e; ++i) 733 if (!isRecordWithSSEVectorType(Context, i->getType())) 734 return false; 735 736 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 737 i != e; ++i) { 738 QualType FT = i->getType(); 739 740 if (isSSEVectorType(Context, FT)) 741 return true; 742 743 if (isRecordWithSSEVectorType(Context, FT)) 744 return true; 745 } 746 747 return false; 748} 749 750unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty, 751 unsigned Align) const { 752 // Otherwise, if the alignment is less than or equal to the minimum ABI 753 // alignment, just use the default; the backend will handle this. 754 if (Align <= MinABIStackAlignInBytes) 755 return 0; // Use default alignment. 756 757 // On non-Darwin, the stack type alignment is always 4. 758 if (!IsDarwinVectorABI) { 759 // Set explicit alignment, since we may need to realign the top. 760 return MinABIStackAlignInBytes; 761 } 762 763 // Otherwise, if the type contains an SSE vector type, the alignment is 16. 764 if (Align >= 16 && (isSSEVectorType(getContext(), Ty) || 765 isRecordWithSSEVectorType(getContext(), Ty))) 766 return 16; 767 768 return MinABIStackAlignInBytes; 769} 770 771ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal, 772 unsigned &FreeRegs) const { 773 if (!ByVal) { 774 if (FreeRegs) { 775 --FreeRegs; // Non byval indirects just use one pointer. 776 return ABIArgInfo::getIndirectInReg(0, false); 777 } 778 return ABIArgInfo::getIndirect(0, false); 779 } 780 781 // Compute the byval alignment. 782 unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; 783 unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign); 784 if (StackAlign == 0) 785 return ABIArgInfo::getIndirect(4); 786 787 // If the stack alignment is less than the type alignment, realign the 788 // argument. 789 if (StackAlign < TypeAlign) 790 return ABIArgInfo::getIndirect(StackAlign, /*ByVal=*/true, 791 /*Realign=*/true); 792 793 return ABIArgInfo::getIndirect(StackAlign); 794} 795 796X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const { 797 const Type *T = isSingleElementStruct(Ty, getContext()); 798 if (!T) 799 T = Ty.getTypePtr(); 800 801 if (const BuiltinType *BT = T->getAs<BuiltinType>()) { 802 BuiltinType::Kind K = BT->getKind(); 803 if (K == BuiltinType::Float || K == BuiltinType::Double) 804 return Float; 805 } 806 return Integer; 807} 808 809bool X86_32ABIInfo::shouldUseInReg(QualType Ty, unsigned &FreeRegs, 810 bool IsFastCall) const { 811 Class C = classify(Ty); 812 if (C == Float) 813 return false; 814 815 unsigned Size = getContext().getTypeSize(Ty); 816 unsigned SizeInRegs = (Size + 31) / 32; 817 818 if (SizeInRegs == 0) 819 return false; 820 821 if (SizeInRegs > FreeRegs) { 822 FreeRegs = 0; 823 return false; 824 } 825 826 FreeRegs -= SizeInRegs; 827 828 if (IsFastCall) { 829 if (Size > 32) 830 return false; 831 832 if (Ty->isIntegralOrEnumerationType()) 833 return true; 834 835 if (Ty->isPointerType()) 836 return true; 837 838 if (Ty->isReferenceType()) 839 return true; 840 841 return false; 842 } 843 844 return true; 845} 846 847ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, 848 unsigned &FreeRegs, 849 bool IsFastCall) const { 850 // FIXME: Set alignment on indirect arguments. 851 if (isAggregateTypeForABI(Ty)) { 852 // Structures with flexible arrays are always indirect. 853 if (const RecordType *RT = Ty->getAs<RecordType>()) { 854 // Structures with either a non-trivial destructor or a non-trivial 855 // copy constructor are always indirect. 856 if (hasNonTrivialDestructorOrCopyConstructor(RT)) 857 return getIndirectResult(Ty, false, FreeRegs); 858 859 if (RT->getDecl()->hasFlexibleArrayMember()) 860 return getIndirectResult(Ty, true, FreeRegs); 861 } 862 863 // Ignore empty structs/unions. 864 if (isEmptyRecord(getContext(), Ty, true)) 865 return ABIArgInfo::getIgnore(); 866 867 if (shouldUseInReg(Ty, FreeRegs, IsFastCall)) { 868 unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; 869 llvm::LLVMContext &LLVMContext = getVMContext(); 870 llvm::Type *Int32 = llvm::Type::getInt32Ty(LLVMContext); 871 SmallVector<llvm::Type*, 3> Elements; 872 for (unsigned I = 0; I < SizeInRegs; ++I) 873 Elements.push_back(Int32); 874 llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); 875 return ABIArgInfo::getDirectInReg(Result); 876 } 877 878 // Expand small (<= 128-bit) record types when we know that the stack layout 879 // of those arguments will match the struct. This is important because the 880 // LLVM backend isn't smart enough to remove byval, which inhibits many 881 // optimizations. 882 if (getContext().getTypeSize(Ty) <= 4*32 && 883 canExpandIndirectArgument(Ty, getContext())) 884 return ABIArgInfo::getExpand(); 885 886 return getIndirectResult(Ty, true, FreeRegs); 887 } 888 889 if (const VectorType *VT = Ty->getAs<VectorType>()) { 890 // On Darwin, some vectors are passed in memory, we handle this by passing 891 // it as an i8/i16/i32/i64. 892 if (IsDarwinVectorABI) { 893 uint64_t Size = getContext().getTypeSize(Ty); 894 if ((Size == 8 || Size == 16 || Size == 32) || 895 (Size == 64 && VT->getNumElements() == 1)) 896 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 897 Size)); 898 } 899 900 llvm::Type *IRType = CGT.ConvertType(Ty); 901 if (UseX86_MMXType(IRType)) { 902 if (IsMMXDisabled) 903 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 904 64)); 905 ABIArgInfo AAI = ABIArgInfo::getDirect(IRType); 906 AAI.setCoerceToType(llvm::Type::getX86_MMXTy(getVMContext())); 907 return AAI; 908 } 909 910 return ABIArgInfo::getDirect(); 911 } 912 913 914 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 915 Ty = EnumTy->getDecl()->getIntegerType(); 916 917 bool InReg = shouldUseInReg(Ty, FreeRegs, IsFastCall); 918 919 if (Ty->isPromotableIntegerType()) { 920 if (InReg) 921 return ABIArgInfo::getExtendInReg(); 922 return ABIArgInfo::getExtend(); 923 } 924 if (InReg) 925 return ABIArgInfo::getDirectInReg(); 926 return ABIArgInfo::getDirect(); 927} 928 929void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { 930 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), 931 FI.getCallingConvention()); 932 933 unsigned CC = FI.getCallingConvention(); 934 bool IsFastCall = CC == llvm::CallingConv::X86_FastCall; 935 unsigned FreeRegs; 936 if (IsFastCall) 937 FreeRegs = 2; 938 else if (FI.getHasRegParm()) 939 FreeRegs = FI.getRegParm(); 940 else 941 FreeRegs = DefaultNumRegisterParameters; 942 943 // If the return value is indirect, then the hidden argument is consuming one 944 // integer register. 945 if (FI.getReturnInfo().isIndirect() && FreeRegs) { 946 --FreeRegs; 947 ABIArgInfo &Old = FI.getReturnInfo(); 948 Old = ABIArgInfo::getIndirectInReg(Old.getIndirectAlign(), 949 Old.getIndirectByVal(), 950 Old.getIndirectRealign()); 951 } 952 953 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 954 it != ie; ++it) 955 it->info = classifyArgumentType(it->type, FreeRegs, IsFastCall); 956} 957 958llvm::Value *X86_32ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 959 CodeGenFunction &CGF) const { 960 llvm::Type *BPP = CGF.Int8PtrPtrTy; 961 962 CGBuilderTy &Builder = CGF.Builder; 963 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 964 "ap"); 965 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 966 967 // Compute if the address needs to be aligned 968 unsigned Align = CGF.getContext().getTypeAlignInChars(Ty).getQuantity(); 969 Align = getTypeStackAlignInBytes(Ty, Align); 970 Align = std::max(Align, 4U); 971 if (Align > 4) { 972 // addr = (addr + align - 1) & -align; 973 llvm::Value *Offset = 974 llvm::ConstantInt::get(CGF.Int32Ty, Align - 1); 975 Addr = CGF.Builder.CreateGEP(Addr, Offset); 976 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(Addr, 977 CGF.Int32Ty); 978 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int32Ty, -Align); 979 Addr = CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 980 Addr->getType(), 981 "ap.cur.aligned"); 982 } 983 984 llvm::Type *PTy = 985 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 986 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 987 988 uint64_t Offset = 989 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, Align); 990 llvm::Value *NextAddr = 991 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 992 "ap.next"); 993 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 994 995 return AddrTyped; 996} 997 998void X86_32TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 999 llvm::GlobalValue *GV, 1000 CodeGen::CodeGenModule &CGM) const { 1001 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 1002 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { 1003 // Get the LLVM function. 1004 llvm::Function *Fn = cast<llvm::Function>(GV); 1005 1006 // Now add the 'alignstack' attribute with a value of 16. 1007 llvm::AttrBuilder B; 1008 B.addStackAlignmentAttr(16); 1009 Fn->addAttribute(llvm::AttrListPtr::FunctionIndex, 1010 llvm::Attributes::get(CGM.getLLVMContext(), B)); 1011 } 1012 } 1013} 1014 1015bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable( 1016 CodeGen::CodeGenFunction &CGF, 1017 llvm::Value *Address) const { 1018 CodeGen::CGBuilderTy &Builder = CGF.Builder; 1019 1020 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 1021 1022 // 0-7 are the eight integer registers; the order is different 1023 // on Darwin (for EH), but the range is the same. 1024 // 8 is %eip. 1025 AssignToArrayRange(Builder, Address, Four8, 0, 8); 1026 1027 if (CGF.CGM.isTargetDarwin()) { 1028 // 12-16 are st(0..4). Not sure why we stop at 4. 1029 // These have size 16, which is sizeof(long double) on 1030 // platforms with 8-byte alignment for that type. 1031 llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); 1032 AssignToArrayRange(Builder, Address, Sixteen8, 12, 16); 1033 1034 } else { 1035 // 9 is %eflags, which doesn't get a size on Darwin for some 1036 // reason. 1037 Builder.CreateStore(Four8, Builder.CreateConstInBoundsGEP1_32(Address, 9)); 1038 1039 // 11-16 are st(0..5). Not sure why we stop at 5. 1040 // These have size 12, which is sizeof(long double) on 1041 // platforms with 4-byte alignment for that type. 1042 llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12); 1043 AssignToArrayRange(Builder, Address, Twelve8, 11, 16); 1044 } 1045 1046 return false; 1047} 1048 1049//===----------------------------------------------------------------------===// 1050// X86-64 ABI Implementation 1051//===----------------------------------------------------------------------===// 1052 1053 1054namespace { 1055/// X86_64ABIInfo - The X86_64 ABI information. 1056class X86_64ABIInfo : public ABIInfo { 1057 enum Class { 1058 Integer = 0, 1059 SSE, 1060 SSEUp, 1061 X87, 1062 X87Up, 1063 ComplexX87, 1064 NoClass, 1065 Memory 1066 }; 1067 1068 /// merge - Implement the X86_64 ABI merging algorithm. 1069 /// 1070 /// Merge an accumulating classification \arg Accum with a field 1071 /// classification \arg Field. 1072 /// 1073 /// \param Accum - The accumulating classification. This should 1074 /// always be either NoClass or the result of a previous merge 1075 /// call. In addition, this should never be Memory (the caller 1076 /// should just return Memory for the aggregate). 1077 static Class merge(Class Accum, Class Field); 1078 1079 /// postMerge - Implement the X86_64 ABI post merging algorithm. 1080 /// 1081 /// Post merger cleanup, reduces a malformed Hi and Lo pair to 1082 /// final MEMORY or SSE classes when necessary. 1083 /// 1084 /// \param AggregateSize - The size of the current aggregate in 1085 /// the classification process. 1086 /// 1087 /// \param Lo - The classification for the parts of the type 1088 /// residing in the low word of the containing object. 1089 /// 1090 /// \param Hi - The classification for the parts of the type 1091 /// residing in the higher words of the containing object. 1092 /// 1093 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; 1094 1095 /// classify - Determine the x86_64 register classes in which the 1096 /// given type T should be passed. 1097 /// 1098 /// \param Lo - The classification for the parts of the type 1099 /// residing in the low word of the containing object. 1100 /// 1101 /// \param Hi - The classification for the parts of the type 1102 /// residing in the high word of the containing object. 1103 /// 1104 /// \param OffsetBase - The bit offset of this type in the 1105 /// containing object. Some parameters are classified different 1106 /// depending on whether they straddle an eightbyte boundary. 1107 /// 1108 /// If a word is unused its result will be NoClass; if a type should 1109 /// be passed in Memory then at least the classification of \arg Lo 1110 /// will be Memory. 1111 /// 1112 /// The \arg Lo class will be NoClass iff the argument is ignored. 1113 /// 1114 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will 1115 /// also be ComplexX87. 1116 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi) const; 1117 1118 llvm::Type *GetByteVectorType(QualType Ty) const; 1119 llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType, 1120 unsigned IROffset, QualType SourceTy, 1121 unsigned SourceOffset) const; 1122 llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType, 1123 unsigned IROffset, QualType SourceTy, 1124 unsigned SourceOffset) const; 1125 1126 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1127 /// such that the argument will be returned in memory. 1128 ABIArgInfo getIndirectReturnResult(QualType Ty) const; 1129 1130 /// getIndirectResult - Give a source type \arg Ty, return a suitable result 1131 /// such that the argument will be passed in memory. 1132 /// 1133 /// \param freeIntRegs - The number of free integer registers remaining 1134 /// available. 1135 ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const; 1136 1137 ABIArgInfo classifyReturnType(QualType RetTy) const; 1138 1139 ABIArgInfo classifyArgumentType(QualType Ty, 1140 unsigned freeIntRegs, 1141 unsigned &neededInt, 1142 unsigned &neededSSE) const; 1143 1144 bool IsIllegalVectorType(QualType Ty) const; 1145 1146 /// The 0.98 ABI revision clarified a lot of ambiguities, 1147 /// unfortunately in ways that were not always consistent with 1148 /// certain previous compilers. In particular, platforms which 1149 /// required strict binary compatibility with older versions of GCC 1150 /// may need to exempt themselves. 1151 bool honorsRevision0_98() const { 1152 return !getContext().getTargetInfo().getTriple().isOSDarwin(); 1153 } 1154 1155 bool HasAVX; 1156 // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on 1157 // 64-bit hardware. 1158 bool Has64BitPointers; 1159 1160public: 1161 X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool hasavx) : 1162 ABIInfo(CGT), HasAVX(hasavx), 1163 Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) { 1164 } 1165 1166 bool isPassedUsingAVXType(QualType type) const { 1167 unsigned neededInt, neededSSE; 1168 // The freeIntRegs argument doesn't matter here. 1169 ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE); 1170 if (info.isDirect()) { 1171 llvm::Type *ty = info.getCoerceToType(); 1172 if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty)) 1173 return (vectorTy->getBitWidth() > 128); 1174 } 1175 return false; 1176 } 1177 1178 virtual void computeInfo(CGFunctionInfo &FI) const; 1179 1180 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1181 CodeGenFunction &CGF) const; 1182}; 1183 1184/// WinX86_64ABIInfo - The Windows X86_64 ABI information. 1185class WinX86_64ABIInfo : public ABIInfo { 1186 1187 ABIArgInfo classify(QualType Ty) const; 1188 1189public: 1190 WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} 1191 1192 virtual void computeInfo(CGFunctionInfo &FI) const; 1193 1194 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 1195 CodeGenFunction &CGF) const; 1196}; 1197 1198class X86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1199public: 1200 X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 1201 : TargetCodeGenInfo(new X86_64ABIInfo(CGT, HasAVX)) {} 1202 1203 const X86_64ABIInfo &getABIInfo() const { 1204 return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); 1205 } 1206 1207 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1208 return 7; 1209 } 1210 1211 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1212 llvm::Value *Address) const { 1213 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1214 1215 // 0-15 are the 16 integer registers. 1216 // 16 is %rip. 1217 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1218 return false; 1219 } 1220 1221 llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, 1222 StringRef Constraint, 1223 llvm::Type* Ty) const { 1224 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 1225 } 1226 1227 bool isNoProtoCallVariadic(const CallArgList &args, 1228 const FunctionNoProtoType *fnType) const { 1229 // The default CC on x86-64 sets %al to the number of SSA 1230 // registers used, and GCC sets this when calling an unprototyped 1231 // function, so we override the default behavior. However, don't do 1232 // that when AVX types are involved: the ABI explicitly states it is 1233 // undefined, and it doesn't work in practice because of how the ABI 1234 // defines varargs anyway. 1235 if (fnType->getCallConv() == CC_Default || fnType->getCallConv() == CC_C) { 1236 bool HasAVXType = false; 1237 for (CallArgList::const_iterator 1238 it = args.begin(), ie = args.end(); it != ie; ++it) { 1239 if (getABIInfo().isPassedUsingAVXType(it->Ty)) { 1240 HasAVXType = true; 1241 break; 1242 } 1243 } 1244 1245 if (!HasAVXType) 1246 return true; 1247 } 1248 1249 return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType); 1250 } 1251 1252}; 1253 1254class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 1255public: 1256 WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) 1257 : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {} 1258 1259 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 1260 return 7; 1261 } 1262 1263 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 1264 llvm::Value *Address) const { 1265 llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); 1266 1267 // 0-15 are the 16 integer registers. 1268 // 16 is %rip. 1269 AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); 1270 return false; 1271 } 1272}; 1273 1274} 1275 1276void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, 1277 Class &Hi) const { 1278 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done: 1279 // 1280 // (a) If one of the classes is Memory, the whole argument is passed in 1281 // memory. 1282 // 1283 // (b) If X87UP is not preceded by X87, the whole argument is passed in 1284 // memory. 1285 // 1286 // (c) If the size of the aggregate exceeds two eightbytes and the first 1287 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole 1288 // argument is passed in memory. NOTE: This is necessary to keep the 1289 // ABI working for processors that don't support the __m256 type. 1290 // 1291 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE. 1292 // 1293 // Some of these are enforced by the merging logic. Others can arise 1294 // only with unions; for example: 1295 // union { _Complex double; unsigned; } 1296 // 1297 // Note that clauses (b) and (c) were added in 0.98. 1298 // 1299 if (Hi == Memory) 1300 Lo = Memory; 1301 if (Hi == X87Up && Lo != X87 && honorsRevision0_98()) 1302 Lo = Memory; 1303 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) 1304 Lo = Memory; 1305 if (Hi == SSEUp && Lo != SSE) 1306 Hi = SSE; 1307} 1308 1309X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) { 1310 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is 1311 // classified recursively so that always two fields are 1312 // considered. The resulting class is calculated according to 1313 // the classes of the fields in the eightbyte: 1314 // 1315 // (a) If both classes are equal, this is the resulting class. 1316 // 1317 // (b) If one of the classes is NO_CLASS, the resulting class is 1318 // the other class. 1319 // 1320 // (c) If one of the classes is MEMORY, the result is the MEMORY 1321 // class. 1322 // 1323 // (d) If one of the classes is INTEGER, the result is the 1324 // INTEGER. 1325 // 1326 // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class, 1327 // MEMORY is used as class. 1328 // 1329 // (f) Otherwise class SSE is used. 1330 1331 // Accum should never be memory (we should have returned) or 1332 // ComplexX87 (because this cannot be passed in a structure). 1333 assert((Accum != Memory && Accum != ComplexX87) && 1334 "Invalid accumulated classification during merge."); 1335 if (Accum == Field || Field == NoClass) 1336 return Accum; 1337 if (Field == Memory) 1338 return Memory; 1339 if (Accum == NoClass) 1340 return Field; 1341 if (Accum == Integer || Field == Integer) 1342 return Integer; 1343 if (Field == X87 || Field == X87Up || Field == ComplexX87 || 1344 Accum == X87 || Accum == X87Up) 1345 return Memory; 1346 return SSE; 1347} 1348 1349void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, 1350 Class &Lo, Class &Hi) const { 1351 // FIXME: This code can be simplified by introducing a simple value class for 1352 // Class pairs with appropriate constructor methods for the various 1353 // situations. 1354 1355 // FIXME: Some of the split computations are wrong; unaligned vectors 1356 // shouldn't be passed in registers for example, so there is no chance they 1357 // can straddle an eightbyte. Verify & simplify. 1358 1359 Lo = Hi = NoClass; 1360 1361 Class &Current = OffsetBase < 64 ? Lo : Hi; 1362 Current = Memory; 1363 1364 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 1365 BuiltinType::Kind k = BT->getKind(); 1366 1367 if (k == BuiltinType::Void) { 1368 Current = NoClass; 1369 } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) { 1370 Lo = Integer; 1371 Hi = Integer; 1372 } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) { 1373 Current = Integer; 1374 } else if ((k == BuiltinType::Float || k == BuiltinType::Double) || 1375 (k == BuiltinType::LongDouble && 1376 getContext().getTargetInfo().getTriple().getOS() == 1377 llvm::Triple::NativeClient)) { 1378 Current = SSE; 1379 } else if (k == BuiltinType::LongDouble) { 1380 Lo = X87; 1381 Hi = X87Up; 1382 } 1383 // FIXME: _Decimal32 and _Decimal64 are SSE. 1384 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp). 1385 return; 1386 } 1387 1388 if (const EnumType *ET = Ty->getAs<EnumType>()) { 1389 // Classify the underlying integer type. 1390 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi); 1391 return; 1392 } 1393 1394 if (Ty->hasPointerRepresentation()) { 1395 Current = Integer; 1396 return; 1397 } 1398 1399 if (Ty->isMemberPointerType()) { 1400 if (Ty->isMemberFunctionPointerType() && Has64BitPointers) 1401 Lo = Hi = Integer; 1402 else 1403 Current = Integer; 1404 return; 1405 } 1406 1407 if (const VectorType *VT = Ty->getAs<VectorType>()) { 1408 uint64_t Size = getContext().getTypeSize(VT); 1409 if (Size == 32) { 1410 // gcc passes all <4 x char>, <2 x short>, <1 x int>, <1 x 1411 // float> as integer. 1412 Current = Integer; 1413 1414 // If this type crosses an eightbyte boundary, it should be 1415 // split. 1416 uint64_t EB_Real = (OffsetBase) / 64; 1417 uint64_t EB_Imag = (OffsetBase + Size - 1) / 64; 1418 if (EB_Real != EB_Imag) 1419 Hi = Lo; 1420 } else if (Size == 64) { 1421 // gcc passes <1 x double> in memory. :( 1422 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) 1423 return; 1424 1425 // gcc passes <1 x long long> as INTEGER. 1426 if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::LongLong) || 1427 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULongLong) || 1428 VT->getElementType()->isSpecificBuiltinType(BuiltinType::Long) || 1429 VT->getElementType()->isSpecificBuiltinType(BuiltinType::ULong)) 1430 Current = Integer; 1431 else 1432 Current = SSE; 1433 1434 // If this type crosses an eightbyte boundary, it should be 1435 // split. 1436 if (OffsetBase && OffsetBase != 64) 1437 Hi = Lo; 1438 } else if (Size == 128 || (HasAVX && Size == 256)) { 1439 // Arguments of 256-bits are split into four eightbyte chunks. The 1440 // least significant one belongs to class SSE and all the others to class 1441 // SSEUP. The original Lo and Hi design considers that types can't be 1442 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense. 1443 // This design isn't correct for 256-bits, but since there're no cases 1444 // where the upper parts would need to be inspected, avoid adding 1445 // complexity and just consider Hi to match the 64-256 part. 1446 Lo = SSE; 1447 Hi = SSEUp; 1448 } 1449 return; 1450 } 1451 1452 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 1453 QualType ET = getContext().getCanonicalType(CT->getElementType()); 1454 1455 uint64_t Size = getContext().getTypeSize(Ty); 1456 if (ET->isIntegralOrEnumerationType()) { 1457 if (Size <= 64) 1458 Current = Integer; 1459 else if (Size <= 128) 1460 Lo = Hi = Integer; 1461 } else if (ET == getContext().FloatTy) 1462 Current = SSE; 1463 else if (ET == getContext().DoubleTy || 1464 (ET == getContext().LongDoubleTy && 1465 getContext().getTargetInfo().getTriple().getOS() == 1466 llvm::Triple::NativeClient)) 1467 Lo = Hi = SSE; 1468 else if (ET == getContext().LongDoubleTy) 1469 Current = ComplexX87; 1470 1471 // If this complex type crosses an eightbyte boundary then it 1472 // should be split. 1473 uint64_t EB_Real = (OffsetBase) / 64; 1474 uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64; 1475 if (Hi == NoClass && EB_Real != EB_Imag) 1476 Hi = Lo; 1477 1478 return; 1479 } 1480 1481 if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) { 1482 // Arrays are treated like structures. 1483 1484 uint64_t Size = getContext().getTypeSize(Ty); 1485 1486 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1487 // than four eightbytes, ..., it has class MEMORY. 1488 if (Size > 256) 1489 return; 1490 1491 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned 1492 // fields, it has class MEMORY. 1493 // 1494 // Only need to check alignment of array base. 1495 if (OffsetBase % getContext().getTypeAlign(AT->getElementType())) 1496 return; 1497 1498 // Otherwise implement simplified merge. We could be smarter about 1499 // this, but it isn't worth it and would be harder to verify. 1500 Current = NoClass; 1501 uint64_t EltSize = getContext().getTypeSize(AT->getElementType()); 1502 uint64_t ArraySize = AT->getSize().getZExtValue(); 1503 1504 // The only case a 256-bit wide vector could be used is when the array 1505 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1506 // to work for sizes wider than 128, early check and fallback to memory. 1507 if (Size > 128 && EltSize != 256) 1508 return; 1509 1510 for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) { 1511 Class FieldLo, FieldHi; 1512 classify(AT->getElementType(), Offset, FieldLo, FieldHi); 1513 Lo = merge(Lo, FieldLo); 1514 Hi = merge(Hi, FieldHi); 1515 if (Lo == Memory || Hi == Memory) 1516 break; 1517 } 1518 1519 postMerge(Size, Lo, Hi); 1520 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification."); 1521 return; 1522 } 1523 1524 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1525 uint64_t Size = getContext().getTypeSize(Ty); 1526 1527 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger 1528 // than four eightbytes, ..., it has class MEMORY. 1529 if (Size > 256) 1530 return; 1531 1532 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial 1533 // copy constructor or a non-trivial destructor, it is passed by invisible 1534 // reference. 1535 if (hasNonTrivialDestructorOrCopyConstructor(RT)) 1536 return; 1537 1538 const RecordDecl *RD = RT->getDecl(); 1539 1540 // Assume variable sized types are passed in memory. 1541 if (RD->hasFlexibleArrayMember()) 1542 return; 1543 1544 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 1545 1546 // Reset Lo class, this will be recomputed. 1547 Current = NoClass; 1548 1549 // If this is a C++ record, classify the bases first. 1550 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1551 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1552 e = CXXRD->bases_end(); i != e; ++i) { 1553 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1554 "Unexpected base class!"); 1555 const CXXRecordDecl *Base = 1556 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1557 1558 // Classify this field. 1559 // 1560 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a 1561 // single eightbyte, each is classified separately. Each eightbyte gets 1562 // initialized to class NO_CLASS. 1563 Class FieldLo, FieldHi; 1564 uint64_t Offset = 1565 OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base)); 1566 classify(i->getType(), Offset, FieldLo, FieldHi); 1567 Lo = merge(Lo, FieldLo); 1568 Hi = merge(Hi, FieldHi); 1569 if (Lo == Memory || Hi == Memory) 1570 break; 1571 } 1572 } 1573 1574 // Classify the fields one at a time, merging the results. 1575 unsigned idx = 0; 1576 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1577 i != e; ++i, ++idx) { 1578 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1579 bool BitField = i->isBitField(); 1580 1581 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than 1582 // four eightbytes, or it contains unaligned fields, it has class MEMORY. 1583 // 1584 // The only case a 256-bit wide vector could be used is when the struct 1585 // contains a single 256-bit element. Since Lo and Hi logic isn't extended 1586 // to work for sizes wider than 128, early check and fallback to memory. 1587 // 1588 if (Size > 128 && getContext().getTypeSize(i->getType()) != 256) { 1589 Lo = Memory; 1590 return; 1591 } 1592 // Note, skip this test for bit-fields, see below. 1593 if (!BitField && Offset % getContext().getTypeAlign(i->getType())) { 1594 Lo = Memory; 1595 return; 1596 } 1597 1598 // Classify this field. 1599 // 1600 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate 1601 // exceeds a single eightbyte, each is classified 1602 // separately. Each eightbyte gets initialized to class 1603 // NO_CLASS. 1604 Class FieldLo, FieldHi; 1605 1606 // Bit-fields require special handling, they do not force the 1607 // structure to be passed in memory even if unaligned, and 1608 // therefore they can straddle an eightbyte. 1609 if (BitField) { 1610 // Ignore padding bit-fields. 1611 if (i->isUnnamedBitfield()) 1612 continue; 1613 1614 uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx); 1615 uint64_t Size = i->getBitWidthValue(getContext()); 1616 1617 uint64_t EB_Lo = Offset / 64; 1618 uint64_t EB_Hi = (Offset + Size - 1) / 64; 1619 FieldLo = FieldHi = NoClass; 1620 if (EB_Lo) { 1621 assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes."); 1622 FieldLo = NoClass; 1623 FieldHi = Integer; 1624 } else { 1625 FieldLo = Integer; 1626 FieldHi = EB_Hi ? Integer : NoClass; 1627 } 1628 } else 1629 classify(i->getType(), Offset, FieldLo, FieldHi); 1630 Lo = merge(Lo, FieldLo); 1631 Hi = merge(Hi, FieldHi); 1632 if (Lo == Memory || Hi == Memory) 1633 break; 1634 } 1635 1636 postMerge(Size, Lo, Hi); 1637 } 1638} 1639 1640ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const { 1641 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1642 // place naturally. 1643 if (!isAggregateTypeForABI(Ty)) { 1644 // Treat an enum type as its underlying type. 1645 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1646 Ty = EnumTy->getDecl()->getIntegerType(); 1647 1648 return (Ty->isPromotableIntegerType() ? 1649 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1650 } 1651 1652 return ABIArgInfo::getIndirect(0); 1653} 1654 1655bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const { 1656 if (const VectorType *VecTy = Ty->getAs<VectorType>()) { 1657 uint64_t Size = getContext().getTypeSize(VecTy); 1658 unsigned LargestVector = HasAVX ? 256 : 128; 1659 if (Size <= 64 || Size > LargestVector) 1660 return true; 1661 } 1662 1663 return false; 1664} 1665 1666ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty, 1667 unsigned freeIntRegs) const { 1668 // If this is a scalar LLVM value then assume LLVM will pass it in the right 1669 // place naturally. 1670 // 1671 // This assumption is optimistic, as there could be free registers available 1672 // when we need to pass this argument in memory, and LLVM could try to pass 1673 // the argument in the free register. This does not seem to happen currently, 1674 // but this code would be much safer if we could mark the argument with 1675 // 'onstack'. See PR12193. 1676 if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) { 1677 // Treat an enum type as its underlying type. 1678 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 1679 Ty = EnumTy->getDecl()->getIntegerType(); 1680 1681 return (Ty->isPromotableIntegerType() ? 1682 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 1683 } 1684 1685 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 1686 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 1687 1688 // Compute the byval alignment. We specify the alignment of the byval in all 1689 // cases so that the mid-level optimizer knows the alignment of the byval. 1690 unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U); 1691 1692 // Attempt to avoid passing indirect results using byval when possible. This 1693 // is important for good codegen. 1694 // 1695 // We do this by coercing the value into a scalar type which the backend can 1696 // handle naturally (i.e., without using byval). 1697 // 1698 // For simplicity, we currently only do this when we have exhausted all of the 1699 // free integer registers. Doing this when there are free integer registers 1700 // would require more care, as we would have to ensure that the coerced value 1701 // did not claim the unused register. That would require either reording the 1702 // arguments to the function (so that any subsequent inreg values came first), 1703 // or only doing this optimization when there were no following arguments that 1704 // might be inreg. 1705 // 1706 // We currently expect it to be rare (particularly in well written code) for 1707 // arguments to be passed on the stack when there are still free integer 1708 // registers available (this would typically imply large structs being passed 1709 // by value), so this seems like a fair tradeoff for now. 1710 // 1711 // We can revisit this if the backend grows support for 'onstack' parameter 1712 // attributes. See PR12193. 1713 if (freeIntRegs == 0) { 1714 uint64_t Size = getContext().getTypeSize(Ty); 1715 1716 // If this type fits in an eightbyte, coerce it into the matching integral 1717 // type, which will end up on the stack (with alignment 8). 1718 if (Align == 8 && Size <= 64) 1719 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 1720 Size)); 1721 } 1722 1723 return ABIArgInfo::getIndirect(Align); 1724} 1725 1726/// GetByteVectorType - The ABI specifies that a value should be passed in an 1727/// full vector XMM/YMM register. Pick an LLVM IR type that will be passed as a 1728/// vector register. 1729llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const { 1730 llvm::Type *IRType = CGT.ConvertType(Ty); 1731 1732 // Wrapper structs that just contain vectors are passed just like vectors, 1733 // strip them off if present. 1734 llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType); 1735 while (STy && STy->getNumElements() == 1) { 1736 IRType = STy->getElementType(0); 1737 STy = dyn_cast<llvm::StructType>(IRType); 1738 } 1739 1740 // If the preferred type is a 16-byte vector, prefer to pass it. 1741 if (llvm::VectorType *VT = dyn_cast<llvm::VectorType>(IRType)){ 1742 llvm::Type *EltTy = VT->getElementType(); 1743 unsigned BitWidth = VT->getBitWidth(); 1744 if ((BitWidth >= 128 && BitWidth <= 256) && 1745 (EltTy->isFloatTy() || EltTy->isDoubleTy() || 1746 EltTy->isIntegerTy(8) || EltTy->isIntegerTy(16) || 1747 EltTy->isIntegerTy(32) || EltTy->isIntegerTy(64) || 1748 EltTy->isIntegerTy(128))) 1749 return VT; 1750 } 1751 1752 return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()), 2); 1753} 1754 1755/// BitsContainNoUserData - Return true if the specified [start,end) bit range 1756/// is known to either be off the end of the specified type or being in 1757/// alignment padding. The user type specified is known to be at most 128 bits 1758/// in size, and have passed through X86_64ABIInfo::classify with a successful 1759/// classification that put one of the two halves in the INTEGER class. 1760/// 1761/// It is conservatively correct to return false. 1762static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, 1763 unsigned EndBit, ASTContext &Context) { 1764 // If the bytes being queried are off the end of the type, there is no user 1765 // data hiding here. This handles analysis of builtins, vectors and other 1766 // types that don't contain interesting padding. 1767 unsigned TySize = (unsigned)Context.getTypeSize(Ty); 1768 if (TySize <= StartBit) 1769 return true; 1770 1771 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 1772 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType()); 1773 unsigned NumElts = (unsigned)AT->getSize().getZExtValue(); 1774 1775 // Check each element to see if the element overlaps with the queried range. 1776 for (unsigned i = 0; i != NumElts; ++i) { 1777 // If the element is after the span we care about, then we're done.. 1778 unsigned EltOffset = i*EltSize; 1779 if (EltOffset >= EndBit) break; 1780 1781 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0; 1782 if (!BitsContainNoUserData(AT->getElementType(), EltStart, 1783 EndBit-EltOffset, Context)) 1784 return false; 1785 } 1786 // If it overlaps no elements, then it is safe to process as padding. 1787 return true; 1788 } 1789 1790 if (const RecordType *RT = Ty->getAs<RecordType>()) { 1791 const RecordDecl *RD = RT->getDecl(); 1792 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 1793 1794 // If this is a C++ record, check the bases first. 1795 if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { 1796 for (CXXRecordDecl::base_class_const_iterator i = CXXRD->bases_begin(), 1797 e = CXXRD->bases_end(); i != e; ++i) { 1798 assert(!i->isVirtual() && !i->getType()->isDependentType() && 1799 "Unexpected base class!"); 1800 const CXXRecordDecl *Base = 1801 cast<CXXRecordDecl>(i->getType()->getAs<RecordType>()->getDecl()); 1802 1803 // If the base is after the span we care about, ignore it. 1804 unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base)); 1805 if (BaseOffset >= EndBit) continue; 1806 1807 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0; 1808 if (!BitsContainNoUserData(i->getType(), BaseStart, 1809 EndBit-BaseOffset, Context)) 1810 return false; 1811 } 1812 } 1813 1814 // Verify that no field has data that overlaps the region of interest. Yes 1815 // this could be sped up a lot by being smarter about queried fields, 1816 // however we're only looking at structs up to 16 bytes, so we don't care 1817 // much. 1818 unsigned idx = 0; 1819 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 1820 i != e; ++i, ++idx) { 1821 unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx); 1822 1823 // If we found a field after the region we care about, then we're done. 1824 if (FieldOffset >= EndBit) break; 1825 1826 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0; 1827 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset, 1828 Context)) 1829 return false; 1830 } 1831 1832 // If nothing in this record overlapped the area of interest, then we're 1833 // clean. 1834 return true; 1835 } 1836 1837 return false; 1838} 1839 1840/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a 1841/// float member at the specified offset. For example, {int,{float}} has a 1842/// float at offset 4. It is conservatively correct for this routine to return 1843/// false. 1844static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, 1845 const llvm::DataLayout &TD) { 1846 // Base case if we find a float. 1847 if (IROffset == 0 && IRType->isFloatTy()) 1848 return true; 1849 1850 // If this is a struct, recurse into the field at the specified offset. 1851 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 1852 const llvm::StructLayout *SL = TD.getStructLayout(STy); 1853 unsigned Elt = SL->getElementContainingOffset(IROffset); 1854 IROffset -= SL->getElementOffset(Elt); 1855 return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD); 1856 } 1857 1858 // If this is an array, recurse into the field at the specified offset. 1859 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 1860 llvm::Type *EltTy = ATy->getElementType(); 1861 unsigned EltSize = TD.getTypeAllocSize(EltTy); 1862 IROffset -= IROffset/EltSize*EltSize; 1863 return ContainsFloatAtOffset(EltTy, IROffset, TD); 1864 } 1865 1866 return false; 1867} 1868 1869 1870/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the 1871/// low 8 bytes of an XMM register, corresponding to the SSE class. 1872llvm::Type *X86_64ABIInfo:: 1873GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1874 QualType SourceTy, unsigned SourceOffset) const { 1875 // The only three choices we have are either double, <2 x float>, or float. We 1876 // pass as float if the last 4 bytes is just padding. This happens for 1877 // structs that contain 3 floats. 1878 if (BitsContainNoUserData(SourceTy, SourceOffset*8+32, 1879 SourceOffset*8+64, getContext())) 1880 return llvm::Type::getFloatTy(getVMContext()); 1881 1882 // We want to pass as <2 x float> if the LLVM IR type contains a float at 1883 // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the 1884 // case. 1885 if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) && 1886 ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout())) 1887 return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2); 1888 1889 return llvm::Type::getDoubleTy(getVMContext()); 1890} 1891 1892 1893/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in 1894/// an 8-byte GPR. This means that we either have a scalar or we are talking 1895/// about the high or low part of an up-to-16-byte struct. This routine picks 1896/// the best LLVM IR type to represent this, which may be i64 or may be anything 1897/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*, 1898/// etc). 1899/// 1900/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for 1901/// the source type. IROffset is an offset in bytes into the LLVM IR type that 1902/// the 8-byte value references. PrefType may be null. 1903/// 1904/// SourceTy is the source level type for the entire argument. SourceOffset is 1905/// an offset into this that we're processing (which is always either 0 or 8). 1906/// 1907llvm::Type *X86_64ABIInfo:: 1908GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset, 1909 QualType SourceTy, unsigned SourceOffset) const { 1910 // If we're dealing with an un-offset LLVM IR type, then it means that we're 1911 // returning an 8-byte unit starting with it. See if we can safely use it. 1912 if (IROffset == 0) { 1913 // Pointers and int64's always fill the 8-byte unit. 1914 if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) || 1915 IRType->isIntegerTy(64)) 1916 return IRType; 1917 1918 // If we have a 1/2/4-byte integer, we can use it only if the rest of the 1919 // goodness in the source type is just tail padding. This is allowed to 1920 // kick in for struct {double,int} on the int, but not on 1921 // struct{double,int,int} because we wouldn't return the second int. We 1922 // have to do this analysis on the source type because we can't depend on 1923 // unions being lowered a specific way etc. 1924 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) || 1925 IRType->isIntegerTy(32) || 1926 (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) { 1927 unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 : 1928 cast<llvm::IntegerType>(IRType)->getBitWidth(); 1929 1930 if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth, 1931 SourceOffset*8+64, getContext())) 1932 return IRType; 1933 } 1934 } 1935 1936 if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) { 1937 // If this is a struct, recurse into the field at the specified offset. 1938 const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy); 1939 if (IROffset < SL->getSizeInBytes()) { 1940 unsigned FieldIdx = SL->getElementContainingOffset(IROffset); 1941 IROffset -= SL->getElementOffset(FieldIdx); 1942 1943 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset, 1944 SourceTy, SourceOffset); 1945 } 1946 } 1947 1948 if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) { 1949 llvm::Type *EltTy = ATy->getElementType(); 1950 unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy); 1951 unsigned EltOffset = IROffset/EltSize*EltSize; 1952 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy, 1953 SourceOffset); 1954 } 1955 1956 // Okay, we don't have any better idea of what to pass, so we pass this in an 1957 // integer register that isn't too big to fit the rest of the struct. 1958 unsigned TySizeInBytes = 1959 (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity(); 1960 1961 assert(TySizeInBytes != SourceOffset && "Empty field?"); 1962 1963 // It is always safe to classify this as an integer type up to i64 that 1964 // isn't larger than the structure. 1965 return llvm::IntegerType::get(getVMContext(), 1966 std::min(TySizeInBytes-SourceOffset, 8U)*8); 1967} 1968 1969 1970/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally 1971/// be used as elements of a two register pair to pass or return, return a 1972/// first class aggregate to represent them. For example, if the low part of 1973/// a by-value argument should be passed as i32* and the high part as float, 1974/// return {i32*, float}. 1975static llvm::Type * 1976GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, 1977 const llvm::DataLayout &TD) { 1978 // In order to correctly satisfy the ABI, we need to the high part to start 1979 // at offset 8. If the high and low parts we inferred are both 4-byte types 1980 // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have 1981 // the second element at offset 8. Check for this: 1982 unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo); 1983 unsigned HiAlign = TD.getABITypeAlignment(Hi); 1984 unsigned HiStart = llvm::DataLayout::RoundUpAlignment(LoSize, HiAlign); 1985 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!"); 1986 1987 // To handle this, we have to increase the size of the low part so that the 1988 // second element will start at an 8 byte offset. We can't increase the size 1989 // of the second element because it might make us access off the end of the 1990 // struct. 1991 if (HiStart != 8) { 1992 // There are only two sorts of types the ABI generation code can produce for 1993 // the low part of a pair that aren't 8 bytes in size: float or i8/i16/i32. 1994 // Promote these to a larger type. 1995 if (Lo->isFloatTy()) 1996 Lo = llvm::Type::getDoubleTy(Lo->getContext()); 1997 else { 1998 assert(Lo->isIntegerTy() && "Invalid/unknown lo type"); 1999 Lo = llvm::Type::getInt64Ty(Lo->getContext()); 2000 } 2001 } 2002 2003 llvm::StructType *Result = llvm::StructType::get(Lo, Hi, NULL); 2004 2005 2006 // Verify that the second element is at an 8-byte offset. 2007 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 && 2008 "Invalid x86-64 argument pair!"); 2009 return Result; 2010} 2011 2012ABIArgInfo X86_64ABIInfo:: 2013classifyReturnType(QualType RetTy) const { 2014 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the 2015 // classification algorithm. 2016 X86_64ABIInfo::Class Lo, Hi; 2017 classify(RetTy, 0, Lo, Hi); 2018 2019 // Check some invariants. 2020 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2021 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2022 2023 llvm::Type *ResType = 0; 2024 switch (Lo) { 2025 case NoClass: 2026 if (Hi == NoClass) 2027 return ABIArgInfo::getIgnore(); 2028 // If the low part is just padding, it takes no register, leave ResType 2029 // null. 2030 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2031 "Unknown missing lo part"); 2032 break; 2033 2034 case SSEUp: 2035 case X87Up: 2036 llvm_unreachable("Invalid classification for lo word."); 2037 2038 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via 2039 // hidden argument. 2040 case Memory: 2041 return getIndirectReturnResult(RetTy); 2042 2043 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next 2044 // available register of the sequence %rax, %rdx is used. 2045 case Integer: 2046 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2047 2048 // If we have a sign or zero extended integer, make sure to return Extend 2049 // so that the parameter gets the right LLVM IR attributes. 2050 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2051 // Treat an enum type as its underlying type. 2052 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 2053 RetTy = EnumTy->getDecl()->getIntegerType(); 2054 2055 if (RetTy->isIntegralOrEnumerationType() && 2056 RetTy->isPromotableIntegerType()) 2057 return ABIArgInfo::getExtend(); 2058 } 2059 break; 2060 2061 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next 2062 // available SSE register of the sequence %xmm0, %xmm1 is used. 2063 case SSE: 2064 ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0); 2065 break; 2066 2067 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is 2068 // returned on the X87 stack in %st0 as 80-bit x87 number. 2069 case X87: 2070 ResType = llvm::Type::getX86_FP80Ty(getVMContext()); 2071 break; 2072 2073 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real 2074 // part of the value is returned in %st0 and the imaginary part in 2075 // %st1. 2076 case ComplexX87: 2077 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification."); 2078 ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()), 2079 llvm::Type::getX86_FP80Ty(getVMContext()), 2080 NULL); 2081 break; 2082 } 2083 2084 llvm::Type *HighPart = 0; 2085 switch (Hi) { 2086 // Memory was handled previously and X87 should 2087 // never occur as a hi class. 2088 case Memory: 2089 case X87: 2090 llvm_unreachable("Invalid classification for hi word."); 2091 2092 case ComplexX87: // Previously handled. 2093 case NoClass: 2094 break; 2095 2096 case Integer: 2097 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2098 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2099 return ABIArgInfo::getDirect(HighPart, 8); 2100 break; 2101 case SSE: 2102 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2103 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2104 return ABIArgInfo::getDirect(HighPart, 8); 2105 break; 2106 2107 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte 2108 // is passed in the next available eightbyte chunk if the last used 2109 // vector register. 2110 // 2111 // SSEUP should always be preceded by SSE, just widen. 2112 case SSEUp: 2113 assert(Lo == SSE && "Unexpected SSEUp classification."); 2114 ResType = GetByteVectorType(RetTy); 2115 break; 2116 2117 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is 2118 // returned together with the previous X87 value in %st0. 2119 case X87Up: 2120 // If X87Up is preceded by X87, we don't need to do 2121 // anything. However, in some cases with unions it may not be 2122 // preceded by X87. In such situations we follow gcc and pass the 2123 // extra bits in an SSE reg. 2124 if (Lo != X87) { 2125 HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8); 2126 if (Lo == NoClass) // Return HighPart at offset 8 in memory. 2127 return ABIArgInfo::getDirect(HighPart, 8); 2128 } 2129 break; 2130 } 2131 2132 // If a high part was specified, merge it together with the low part. It is 2133 // known to pass in the high eightbyte of the result. We do this by forming a 2134 // first class struct aggregate with the high and low part: {low, high} 2135 if (HighPart) 2136 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2137 2138 return ABIArgInfo::getDirect(ResType); 2139} 2140 2141ABIArgInfo X86_64ABIInfo::classifyArgumentType( 2142 QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE) 2143 const 2144{ 2145 X86_64ABIInfo::Class Lo, Hi; 2146 classify(Ty, 0, Lo, Hi); 2147 2148 // Check some invariants. 2149 // FIXME: Enforce these by construction. 2150 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification."); 2151 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification."); 2152 2153 neededInt = 0; 2154 neededSSE = 0; 2155 llvm::Type *ResType = 0; 2156 switch (Lo) { 2157 case NoClass: 2158 if (Hi == NoClass) 2159 return ABIArgInfo::getIgnore(); 2160 // If the low part is just padding, it takes no register, leave ResType 2161 // null. 2162 assert((Hi == SSE || Hi == Integer || Hi == X87Up) && 2163 "Unknown missing lo part"); 2164 break; 2165 2166 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument 2167 // on the stack. 2168 case Memory: 2169 2170 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or 2171 // COMPLEX_X87, it is passed in memory. 2172 case X87: 2173 case ComplexX87: 2174 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 2175 ++neededInt; 2176 return getIndirectResult(Ty, freeIntRegs); 2177 2178 case SSEUp: 2179 case X87Up: 2180 llvm_unreachable("Invalid classification for lo word."); 2181 2182 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next 2183 // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8 2184 // and %r9 is used. 2185 case Integer: 2186 ++neededInt; 2187 2188 // Pick an 8-byte type based on the preferred type. 2189 ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0); 2190 2191 // If we have a sign or zero extended integer, make sure to return Extend 2192 // so that the parameter gets the right LLVM IR attributes. 2193 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) { 2194 // Treat an enum type as its underlying type. 2195 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2196 Ty = EnumTy->getDecl()->getIntegerType(); 2197 2198 if (Ty->isIntegralOrEnumerationType() && 2199 Ty->isPromotableIntegerType()) 2200 return ABIArgInfo::getExtend(); 2201 } 2202 2203 break; 2204 2205 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next 2206 // available SSE register is used, the registers are taken in the 2207 // order from %xmm0 to %xmm7. 2208 case SSE: { 2209 llvm::Type *IRType = CGT.ConvertType(Ty); 2210 ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0); 2211 ++neededSSE; 2212 break; 2213 } 2214 } 2215 2216 llvm::Type *HighPart = 0; 2217 switch (Hi) { 2218 // Memory was handled previously, ComplexX87 and X87 should 2219 // never occur as hi classes, and X87Up must be preceded by X87, 2220 // which is passed in memory. 2221 case Memory: 2222 case X87: 2223 case ComplexX87: 2224 llvm_unreachable("Invalid classification for hi word."); 2225 2226 case NoClass: break; 2227 2228 case Integer: 2229 ++neededInt; 2230 // Pick an 8-byte type based on the preferred type. 2231 HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2232 2233 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2234 return ABIArgInfo::getDirect(HighPart, 8); 2235 break; 2236 2237 // X87Up generally doesn't occur here (long double is passed in 2238 // memory), except in situations involving unions. 2239 case X87Up: 2240 case SSE: 2241 HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8); 2242 2243 if (Lo == NoClass) // Pass HighPart at offset 8 in memory. 2244 return ABIArgInfo::getDirect(HighPart, 8); 2245 2246 ++neededSSE; 2247 break; 2248 2249 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the 2250 // eightbyte is passed in the upper half of the last used SSE 2251 // register. This only happens when 128-bit vectors are passed. 2252 case SSEUp: 2253 assert(Lo == SSE && "Unexpected SSEUp classification"); 2254 ResType = GetByteVectorType(Ty); 2255 break; 2256 } 2257 2258 // If a high part was specified, merge it together with the low part. It is 2259 // known to pass in the high eightbyte of the result. We do this by forming a 2260 // first class struct aggregate with the high and low part: {low, high} 2261 if (HighPart) 2262 ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout()); 2263 2264 return ABIArgInfo::getDirect(ResType); 2265} 2266 2267void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2268 2269 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2270 2271 // Keep track of the number of assigned registers. 2272 unsigned freeIntRegs = 6, freeSSERegs = 8; 2273 2274 // If the return value is indirect, then the hidden argument is consuming one 2275 // integer register. 2276 if (FI.getReturnInfo().isIndirect()) 2277 --freeIntRegs; 2278 2279 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers 2280 // get assigned (in left-to-right order) for passing as follows... 2281 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2282 it != ie; ++it) { 2283 unsigned neededInt, neededSSE; 2284 it->info = classifyArgumentType(it->type, freeIntRegs, neededInt, 2285 neededSSE); 2286 2287 // AMD64-ABI 3.2.3p3: If there are no registers available for any 2288 // eightbyte of an argument, the whole argument is passed on the 2289 // stack. If registers have already been assigned for some 2290 // eightbytes of such an argument, the assignments get reverted. 2291 if (freeIntRegs >= neededInt && freeSSERegs >= neededSSE) { 2292 freeIntRegs -= neededInt; 2293 freeSSERegs -= neededSSE; 2294 } else { 2295 it->info = getIndirectResult(it->type, freeIntRegs); 2296 } 2297 } 2298} 2299 2300static llvm::Value *EmitVAArgFromMemory(llvm::Value *VAListAddr, 2301 QualType Ty, 2302 CodeGenFunction &CGF) { 2303 llvm::Value *overflow_arg_area_p = 2304 CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p"); 2305 llvm::Value *overflow_arg_area = 2306 CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area"); 2307 2308 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16 2309 // byte boundary if alignment needed by type exceeds 8 byte boundary. 2310 // It isn't stated explicitly in the standard, but in practice we use 2311 // alignment greater than 16 where necessary. 2312 uint64_t Align = CGF.getContext().getTypeAlign(Ty) / 8; 2313 if (Align > 8) { 2314 // overflow_arg_area = (overflow_arg_area + align - 1) & -align; 2315 llvm::Value *Offset = 2316 llvm::ConstantInt::get(CGF.Int64Ty, Align - 1); 2317 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset); 2318 llvm::Value *AsInt = CGF.Builder.CreatePtrToInt(overflow_arg_area, 2319 CGF.Int64Ty); 2320 llvm::Value *Mask = llvm::ConstantInt::get(CGF.Int64Ty, -(uint64_t)Align); 2321 overflow_arg_area = 2322 CGF.Builder.CreateIntToPtr(CGF.Builder.CreateAnd(AsInt, Mask), 2323 overflow_arg_area->getType(), 2324 "overflow_arg_area.align"); 2325 } 2326 2327 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area. 2328 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2329 llvm::Value *Res = 2330 CGF.Builder.CreateBitCast(overflow_arg_area, 2331 llvm::PointerType::getUnqual(LTy)); 2332 2333 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to: 2334 // l->overflow_arg_area + sizeof(type). 2335 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to 2336 // an 8 byte boundary. 2337 2338 uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8; 2339 llvm::Value *Offset = 2340 llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7); 2341 overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset, 2342 "overflow_arg_area.next"); 2343 CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p); 2344 2345 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type. 2346 return Res; 2347} 2348 2349llvm::Value *X86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2350 CodeGenFunction &CGF) const { 2351 // Assume that va_list type is correct; should be pointer to LLVM type: 2352 // struct { 2353 // i32 gp_offset; 2354 // i32 fp_offset; 2355 // i8* overflow_arg_area; 2356 // i8* reg_save_area; 2357 // }; 2358 unsigned neededInt, neededSSE; 2359 2360 Ty = CGF.getContext().getCanonicalType(Ty); 2361 ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE); 2362 2363 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed 2364 // in the registers. If not go to step 7. 2365 if (!neededInt && !neededSSE) 2366 return EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2367 2368 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of 2369 // general purpose registers needed to pass type and num_fp to hold 2370 // the number of floating point registers needed. 2371 2372 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into 2373 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or 2374 // l->fp_offset > 304 - num_fp * 16 go to step 7. 2375 // 2376 // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of 2377 // register save space). 2378 2379 llvm::Value *InRegs = 0; 2380 llvm::Value *gp_offset_p = 0, *gp_offset = 0; 2381 llvm::Value *fp_offset_p = 0, *fp_offset = 0; 2382 if (neededInt) { 2383 gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p"); 2384 gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset"); 2385 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8); 2386 InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp"); 2387 } 2388 2389 if (neededSSE) { 2390 fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p"); 2391 fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset"); 2392 llvm::Value *FitsInFP = 2393 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16); 2394 FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp"); 2395 InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP; 2396 } 2397 2398 llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg"); 2399 llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem"); 2400 llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end"); 2401 CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock); 2402 2403 // Emit code to load the value if it was passed in registers. 2404 2405 CGF.EmitBlock(InRegBlock); 2406 2407 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with 2408 // an offset of l->gp_offset and/or l->fp_offset. This may require 2409 // copying to a temporary location in case the parameter is passed 2410 // in different register classes or requires an alignment greater 2411 // than 8 for general purpose registers and 16 for XMM registers. 2412 // 2413 // FIXME: This really results in shameful code when we end up needing to 2414 // collect arguments from different places; often what should result in a 2415 // simple assembling of a structure from scattered addresses has many more 2416 // loads than necessary. Can we clean this up? 2417 llvm::Type *LTy = CGF.ConvertTypeForMem(Ty); 2418 llvm::Value *RegAddr = 2419 CGF.Builder.CreateLoad(CGF.Builder.CreateStructGEP(VAListAddr, 3), 2420 "reg_save_area"); 2421 if (neededInt && neededSSE) { 2422 // FIXME: Cleanup. 2423 assert(AI.isDirect() && "Unexpected ABI info for mixed regs"); 2424 llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType()); 2425 llvm::Value *Tmp = CGF.CreateTempAlloca(ST); 2426 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs"); 2427 llvm::Type *TyLo = ST->getElementType(0); 2428 llvm::Type *TyHi = ST->getElementType(1); 2429 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) && 2430 "Unexpected ABI info for mixed regs"); 2431 llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo); 2432 llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi); 2433 llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2434 llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2435 llvm::Value *RegLoAddr = TyLo->isFloatingPointTy() ? FPAddr : GPAddr; 2436 llvm::Value *RegHiAddr = TyLo->isFloatingPointTy() ? GPAddr : FPAddr; 2437 llvm::Value *V = 2438 CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegLoAddr, PTyLo)); 2439 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2440 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegHiAddr, PTyHi)); 2441 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2442 2443 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2444 llvm::PointerType::getUnqual(LTy)); 2445 } else if (neededInt) { 2446 RegAddr = CGF.Builder.CreateGEP(RegAddr, gp_offset); 2447 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2448 llvm::PointerType::getUnqual(LTy)); 2449 } else if (neededSSE == 1) { 2450 RegAddr = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2451 RegAddr = CGF.Builder.CreateBitCast(RegAddr, 2452 llvm::PointerType::getUnqual(LTy)); 2453 } else { 2454 assert(neededSSE == 2 && "Invalid number of needed registers!"); 2455 // SSE registers are spaced 16 bytes apart in the register save 2456 // area, we need to collect the two eightbytes together. 2457 llvm::Value *RegAddrLo = CGF.Builder.CreateGEP(RegAddr, fp_offset); 2458 llvm::Value *RegAddrHi = CGF.Builder.CreateConstGEP1_32(RegAddrLo, 16); 2459 llvm::Type *DoubleTy = CGF.DoubleTy; 2460 llvm::Type *DblPtrTy = 2461 llvm::PointerType::getUnqual(DoubleTy); 2462 llvm::StructType *ST = llvm::StructType::get(DoubleTy, 2463 DoubleTy, NULL); 2464 llvm::Value *V, *Tmp = CGF.CreateTempAlloca(ST); 2465 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrLo, 2466 DblPtrTy)); 2467 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0)); 2468 V = CGF.Builder.CreateLoad(CGF.Builder.CreateBitCast(RegAddrHi, 2469 DblPtrTy)); 2470 CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1)); 2471 RegAddr = CGF.Builder.CreateBitCast(Tmp, 2472 llvm::PointerType::getUnqual(LTy)); 2473 } 2474 2475 // AMD64-ABI 3.5.7p5: Step 5. Set: 2476 // l->gp_offset = l->gp_offset + num_gp * 8 2477 // l->fp_offset = l->fp_offset + num_fp * 16. 2478 if (neededInt) { 2479 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8); 2480 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset), 2481 gp_offset_p); 2482 } 2483 if (neededSSE) { 2484 llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16); 2485 CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset), 2486 fp_offset_p); 2487 } 2488 CGF.EmitBranch(ContBlock); 2489 2490 // Emit code to load the value if it was passed in memory. 2491 2492 CGF.EmitBlock(InMemBlock); 2493 llvm::Value *MemAddr = EmitVAArgFromMemory(VAListAddr, Ty, CGF); 2494 2495 // Return the appropriate result. 2496 2497 CGF.EmitBlock(ContBlock); 2498 llvm::PHINode *ResAddr = CGF.Builder.CreatePHI(RegAddr->getType(), 2, 2499 "vaarg.addr"); 2500 ResAddr->addIncoming(RegAddr, InRegBlock); 2501 ResAddr->addIncoming(MemAddr, InMemBlock); 2502 return ResAddr; 2503} 2504 2505ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty) const { 2506 2507 if (Ty->isVoidType()) 2508 return ABIArgInfo::getIgnore(); 2509 2510 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 2511 Ty = EnumTy->getDecl()->getIntegerType(); 2512 2513 uint64_t Size = getContext().getTypeSize(Ty); 2514 2515 if (const RecordType *RT = Ty->getAs<RecordType>()) { 2516 if (hasNonTrivialDestructorOrCopyConstructor(RT) || 2517 RT->getDecl()->hasFlexibleArrayMember()) 2518 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2519 2520 // FIXME: mingw-w64-gcc emits 128-bit struct as i128 2521 if (Size == 128 && 2522 getContext().getTargetInfo().getTriple().getOS() 2523 == llvm::Triple::MinGW32) 2524 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2525 Size)); 2526 2527 // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is 2528 // not 1, 2, 4, or 8 bytes, must be passed by reference." 2529 if (Size <= 64 && 2530 (Size & (Size - 1)) == 0) 2531 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 2532 Size)); 2533 2534 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 2535 } 2536 2537 if (Ty->isPromotableIntegerType()) 2538 return ABIArgInfo::getExtend(); 2539 2540 return ABIArgInfo::getDirect(); 2541} 2542 2543void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2544 2545 QualType RetTy = FI.getReturnType(); 2546 FI.getReturnInfo() = classify(RetTy); 2547 2548 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2549 it != ie; ++it) 2550 it->info = classify(it->type); 2551} 2552 2553llvm::Value *WinX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2554 CodeGenFunction &CGF) const { 2555 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2556 2557 CGBuilderTy &Builder = CGF.Builder; 2558 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 2559 "ap"); 2560 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2561 llvm::Type *PTy = 2562 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2563 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 2564 2565 uint64_t Offset = 2566 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 8); 2567 llvm::Value *NextAddr = 2568 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 2569 "ap.next"); 2570 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2571 2572 return AddrTyped; 2573} 2574 2575namespace { 2576 2577class NaClX86_64ABIInfo : public ABIInfo { 2578 public: 2579 NaClX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2580 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, HasAVX) {} 2581 virtual void computeInfo(CGFunctionInfo &FI) const; 2582 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2583 CodeGenFunction &CGF) const; 2584 private: 2585 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 2586 X86_64ABIInfo NInfo; // Used for everything else. 2587}; 2588 2589class NaClX86_64TargetCodeGenInfo : public TargetCodeGenInfo { 2590 public: 2591 NaClX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool HasAVX) 2592 : TargetCodeGenInfo(new NaClX86_64ABIInfo(CGT, HasAVX)) {} 2593}; 2594 2595} 2596 2597void NaClX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const { 2598 if (FI.getASTCallingConvention() == CC_PnaclCall) 2599 PInfo.computeInfo(FI); 2600 else 2601 NInfo.computeInfo(FI); 2602} 2603 2604llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2605 CodeGenFunction &CGF) const { 2606 // Always use the native convention; calling pnacl-style varargs functions 2607 // is unuspported. 2608 return NInfo.EmitVAArg(VAListAddr, Ty, CGF); 2609} 2610 2611 2612// PowerPC-32 2613 2614namespace { 2615class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2616public: 2617 PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2618 2619 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2620 // This is recovered from gcc output. 2621 return 1; // r1 is the dedicated stack pointer 2622 } 2623 2624 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2625 llvm::Value *Address) const; 2626}; 2627 2628} 2629 2630bool 2631PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2632 llvm::Value *Address) const { 2633 // This is calculated from the LLVM and GCC tables and verified 2634 // against gcc output. AFAIK all ABIs use the same encoding. 2635 2636 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2637 2638 llvm::IntegerType *i8 = CGF.Int8Ty; 2639 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2640 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2641 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2642 2643 // 0-31: r0-31, the 4-byte general-purpose registers 2644 AssignToArrayRange(Builder, Address, Four8, 0, 31); 2645 2646 // 32-63: fp0-31, the 8-byte floating-point registers 2647 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2648 2649 // 64-76 are various 4-byte special-purpose registers: 2650 // 64: mq 2651 // 65: lr 2652 // 66: ctr 2653 // 67: ap 2654 // 68-75 cr0-7 2655 // 76: xer 2656 AssignToArrayRange(Builder, Address, Four8, 64, 76); 2657 2658 // 77-108: v0-31, the 16-byte vector registers 2659 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 2660 2661 // 109: vrsave 2662 // 110: vscr 2663 // 111: spe_acc 2664 // 112: spefscr 2665 // 113: sfp 2666 AssignToArrayRange(Builder, Address, Four8, 109, 113); 2667 2668 return false; 2669} 2670 2671// PowerPC-64 2672 2673namespace { 2674/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information. 2675class PPC64_SVR4_ABIInfo : public DefaultABIInfo { 2676 2677public: 2678 PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {} 2679 2680 // TODO: We can add more logic to computeInfo to improve performance. 2681 // Example: For aggregate arguments that fit in a register, we could 2682 // use getDirectInReg (as is done below for structs containing a single 2683 // floating-point value) to avoid pushing them to memory on function 2684 // entry. This would require changing the logic in PPCISelLowering 2685 // when lowering the parameters in the caller and args in the callee. 2686 virtual void computeInfo(CGFunctionInfo &FI) const { 2687 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2688 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2689 it != ie; ++it) { 2690 // We rely on the default argument classification for the most part. 2691 // One exception: An aggregate containing a single floating-point 2692 // item must be passed in a register if one is available. 2693 const Type *T = isSingleElementStruct(it->type, getContext()); 2694 if (T) { 2695 const BuiltinType *BT = T->getAs<BuiltinType>(); 2696 if (BT && BT->isFloatingPoint()) { 2697 QualType QT(T, 0); 2698 it->info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT)); 2699 continue; 2700 } 2701 } 2702 it->info = classifyArgumentType(it->type); 2703 } 2704 } 2705 2706 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, 2707 QualType Ty, 2708 CodeGenFunction &CGF) const; 2709}; 2710 2711class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo { 2712public: 2713 PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT) 2714 : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT)) {} 2715 2716 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2717 // This is recovered from gcc output. 2718 return 1; // r1 is the dedicated stack pointer 2719 } 2720 2721 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2722 llvm::Value *Address) const; 2723}; 2724 2725class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo { 2726public: 2727 PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {} 2728 2729 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2730 // This is recovered from gcc output. 2731 return 1; // r1 is the dedicated stack pointer 2732 } 2733 2734 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2735 llvm::Value *Address) const; 2736}; 2737 2738} 2739 2740// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine. 2741llvm::Value *PPC64_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr, 2742 QualType Ty, 2743 CodeGenFunction &CGF) const { 2744 llvm::Type *BP = CGF.Int8PtrTy; 2745 llvm::Type *BPP = CGF.Int8PtrPtrTy; 2746 2747 CGBuilderTy &Builder = CGF.Builder; 2748 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 2749 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 2750 2751 // Handle address alignment for type alignment > 64 bits. Although 2752 // long double normally requires 16-byte alignment, this is not the 2753 // case when it is passed as an argument; so handle that special case. 2754 const BuiltinType *BT = Ty->getAs<BuiltinType>(); 2755 unsigned TyAlign = CGF.getContext().getTypeAlign(Ty) / 8; 2756 2757 if (TyAlign > 8 && (!BT || !BT->isFloatingPoint())) { 2758 assert((TyAlign & (TyAlign - 1)) == 0 && 2759 "Alignment is not power of 2!"); 2760 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2761 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt64(TyAlign - 1)); 2762 AddrAsInt = Builder.CreateAnd(AddrAsInt, Builder.getInt64(~(TyAlign - 1))); 2763 Addr = Builder.CreateIntToPtr(AddrAsInt, BP); 2764 } 2765 2766 // Update the va_list pointer. 2767 unsigned SizeInBytes = CGF.getContext().getTypeSize(Ty) / 8; 2768 unsigned Offset = llvm::RoundUpToAlignment(SizeInBytes, 8); 2769 llvm::Value *NextAddr = 2770 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int64Ty, Offset), 2771 "ap.next"); 2772 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 2773 2774 // If the argument is smaller than 8 bytes, it is right-adjusted in 2775 // its doubleword slot. Adjust the pointer to pick it up from the 2776 // correct offset. 2777 if (SizeInBytes < 8) { 2778 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int64Ty); 2779 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt64(8 - SizeInBytes)); 2780 Addr = Builder.CreateIntToPtr(AddrAsInt, BP); 2781 } 2782 2783 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 2784 return Builder.CreateBitCast(Addr, PTy); 2785} 2786 2787static bool 2788PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2789 llvm::Value *Address) { 2790 // This is calculated from the LLVM and GCC tables and verified 2791 // against gcc output. AFAIK all ABIs use the same encoding. 2792 2793 CodeGen::CGBuilderTy &Builder = CGF.Builder; 2794 2795 llvm::IntegerType *i8 = CGF.Int8Ty; 2796 llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4); 2797 llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8); 2798 llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16); 2799 2800 // 0-31: r0-31, the 8-byte general-purpose registers 2801 AssignToArrayRange(Builder, Address, Eight8, 0, 31); 2802 2803 // 32-63: fp0-31, the 8-byte floating-point registers 2804 AssignToArrayRange(Builder, Address, Eight8, 32, 63); 2805 2806 // 64-76 are various 4-byte special-purpose registers: 2807 // 64: mq 2808 // 65: lr 2809 // 66: ctr 2810 // 67: ap 2811 // 68-75 cr0-7 2812 // 76: xer 2813 AssignToArrayRange(Builder, Address, Four8, 64, 76); 2814 2815 // 77-108: v0-31, the 16-byte vector registers 2816 AssignToArrayRange(Builder, Address, Sixteen8, 77, 108); 2817 2818 // 109: vrsave 2819 // 110: vscr 2820 // 111: spe_acc 2821 // 112: spefscr 2822 // 113: sfp 2823 AssignToArrayRange(Builder, Address, Four8, 109, 113); 2824 2825 return false; 2826} 2827 2828bool 2829PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable( 2830 CodeGen::CodeGenFunction &CGF, 2831 llvm::Value *Address) const { 2832 2833 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 2834} 2835 2836bool 2837PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2838 llvm::Value *Address) const { 2839 2840 return PPC64_initDwarfEHRegSizeTable(CGF, Address); 2841} 2842 2843//===----------------------------------------------------------------------===// 2844// ARM ABI Implementation 2845//===----------------------------------------------------------------------===// 2846 2847namespace { 2848 2849class ARMABIInfo : public ABIInfo { 2850public: 2851 enum ABIKind { 2852 APCS = 0, 2853 AAPCS = 1, 2854 AAPCS_VFP 2855 }; 2856 2857private: 2858 ABIKind Kind; 2859 2860public: 2861 ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind) : ABIInfo(CGT), Kind(_Kind) {} 2862 2863 bool isEABI() const { 2864 StringRef Env = 2865 getContext().getTargetInfo().getTriple().getEnvironmentName(); 2866 return (Env == "gnueabi" || Env == "eabi" || 2867 Env == "android" || Env == "androideabi"); 2868 } 2869 2870private: 2871 ABIKind getABIKind() const { return Kind; } 2872 2873 ABIArgInfo classifyReturnType(QualType RetTy) const; 2874 ABIArgInfo classifyArgumentType(QualType RetTy) const; 2875 bool isIllegalVectorType(QualType Ty) const; 2876 2877 virtual void computeInfo(CGFunctionInfo &FI) const; 2878 2879 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 2880 CodeGenFunction &CGF) const; 2881}; 2882 2883class ARMTargetCodeGenInfo : public TargetCodeGenInfo { 2884public: 2885 ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K) 2886 :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {} 2887 2888 const ARMABIInfo &getABIInfo() const { 2889 return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo()); 2890 } 2891 2892 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 2893 return 13; 2894 } 2895 2896 StringRef getARCRetainAutoreleasedReturnValueMarker() const { 2897 return "mov\tr7, r7\t\t@ marker for objc_retainAutoreleaseReturnValue"; 2898 } 2899 2900 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 2901 llvm::Value *Address) const { 2902 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 2903 2904 // 0-15 are the 16 integer registers. 2905 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15); 2906 return false; 2907 } 2908 2909 unsigned getSizeOfUnwindException() const { 2910 if (getABIInfo().isEABI()) return 88; 2911 return TargetCodeGenInfo::getSizeOfUnwindException(); 2912 } 2913}; 2914 2915} 2916 2917void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 2918 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 2919 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 2920 it != ie; ++it) 2921 it->info = classifyArgumentType(it->type); 2922 2923 // Always honor user-specified calling convention. 2924 if (FI.getCallingConvention() != llvm::CallingConv::C) 2925 return; 2926 2927 // Calling convention as default by an ABI. 2928 llvm::CallingConv::ID DefaultCC; 2929 if (isEABI()) 2930 DefaultCC = llvm::CallingConv::ARM_AAPCS; 2931 else 2932 DefaultCC = llvm::CallingConv::ARM_APCS; 2933 2934 // If user did not ask for specific calling convention explicitly (e.g. via 2935 // pcs attribute), set effective calling convention if it's different than ABI 2936 // default. 2937 switch (getABIKind()) { 2938 case APCS: 2939 if (DefaultCC != llvm::CallingConv::ARM_APCS) 2940 FI.setEffectiveCallingConvention(llvm::CallingConv::ARM_APCS); 2941 break; 2942 case AAPCS: 2943 if (DefaultCC != llvm::CallingConv::ARM_AAPCS) 2944 FI.setEffectiveCallingConvention(llvm::CallingConv::ARM_AAPCS); 2945 break; 2946 case AAPCS_VFP: 2947 if (DefaultCC != llvm::CallingConv::ARM_AAPCS_VFP) 2948 FI.setEffectiveCallingConvention(llvm::CallingConv::ARM_AAPCS_VFP); 2949 break; 2950 } 2951} 2952 2953/// isHomogeneousAggregate - Return true if a type is an AAPCS-VFP homogeneous 2954/// aggregate. If HAMembers is non-null, the number of base elements 2955/// contained in the type is returned through it; this is used for the 2956/// recursive calls that check aggregate component types. 2957static bool isHomogeneousAggregate(QualType Ty, const Type *&Base, 2958 ASTContext &Context, 2959 uint64_t *HAMembers = 0) { 2960 uint64_t Members = 0; 2961 if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) { 2962 if (!isHomogeneousAggregate(AT->getElementType(), Base, Context, &Members)) 2963 return false; 2964 Members *= AT->getSize().getZExtValue(); 2965 } else if (const RecordType *RT = Ty->getAs<RecordType>()) { 2966 const RecordDecl *RD = RT->getDecl(); 2967 if (RD->hasFlexibleArrayMember()) 2968 return false; 2969 2970 Members = 0; 2971 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 2972 i != e; ++i) { 2973 const FieldDecl *FD = *i; 2974 uint64_t FldMembers; 2975 if (!isHomogeneousAggregate(FD->getType(), Base, Context, &FldMembers)) 2976 return false; 2977 2978 Members = (RD->isUnion() ? 2979 std::max(Members, FldMembers) : Members + FldMembers); 2980 } 2981 } else { 2982 Members = 1; 2983 if (const ComplexType *CT = Ty->getAs<ComplexType>()) { 2984 Members = 2; 2985 Ty = CT->getElementType(); 2986 } 2987 2988 // Homogeneous aggregates for AAPCS-VFP must have base types of float, 2989 // double, or 64-bit or 128-bit vectors. 2990 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { 2991 if (BT->getKind() != BuiltinType::Float && 2992 BT->getKind() != BuiltinType::Double && 2993 BT->getKind() != BuiltinType::LongDouble) 2994 return false; 2995 } else if (const VectorType *VT = Ty->getAs<VectorType>()) { 2996 unsigned VecSize = Context.getTypeSize(VT); 2997 if (VecSize != 64 && VecSize != 128) 2998 return false; 2999 } else { 3000 return false; 3001 } 3002 3003 // The base type must be the same for all members. Vector types of the 3004 // same total size are treated as being equivalent here. 3005 const Type *TyPtr = Ty.getTypePtr(); 3006 if (!Base) 3007 Base = TyPtr; 3008 if (Base != TyPtr && 3009 (!Base->isVectorType() || !TyPtr->isVectorType() || 3010 Context.getTypeSize(Base) != Context.getTypeSize(TyPtr))) 3011 return false; 3012 } 3013 3014 // Homogeneous Aggregates can have at most 4 members of the base type. 3015 if (HAMembers) 3016 *HAMembers = Members; 3017 3018 return (Members > 0 && Members <= 4); 3019} 3020 3021ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty) const { 3022 // Handle illegal vector types here. 3023 if (isIllegalVectorType(Ty)) { 3024 uint64_t Size = getContext().getTypeSize(Ty); 3025 if (Size <= 32) { 3026 llvm::Type *ResType = 3027 llvm::Type::getInt32Ty(getVMContext()); 3028 return ABIArgInfo::getDirect(ResType); 3029 } 3030 if (Size == 64) { 3031 llvm::Type *ResType = llvm::VectorType::get( 3032 llvm::Type::getInt32Ty(getVMContext()), 2); 3033 return ABIArgInfo::getDirect(ResType); 3034 } 3035 if (Size == 128) { 3036 llvm::Type *ResType = llvm::VectorType::get( 3037 llvm::Type::getInt32Ty(getVMContext()), 4); 3038 return ABIArgInfo::getDirect(ResType); 3039 } 3040 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3041 } 3042 3043 if (!isAggregateTypeForABI(Ty)) { 3044 // Treat an enum type as its underlying type. 3045 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3046 Ty = EnumTy->getDecl()->getIntegerType(); 3047 3048 return (Ty->isPromotableIntegerType() ? 3049 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3050 } 3051 3052 // Ignore empty records. 3053 if (isEmptyRecord(getContext(), Ty, true)) 3054 return ABIArgInfo::getIgnore(); 3055 3056 // Structures with either a non-trivial destructor or a non-trivial 3057 // copy constructor are always indirect. 3058 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 3059 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3060 3061 if (getABIKind() == ARMABIInfo::AAPCS_VFP) { 3062 // Homogeneous Aggregates need to be expanded. 3063 const Type *Base = 0; 3064 if (isHomogeneousAggregate(Ty, Base, getContext())) { 3065 assert(Base && "Base class should be set for homogeneous aggregate"); 3066 return ABIArgInfo::getExpand(); 3067 } 3068 } 3069 3070 // Support byval for ARM. 3071 if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64) || 3072 getContext().getTypeAlign(Ty) > 64) { 3073 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 3074 } 3075 3076 // Otherwise, pass by coercing to a structure of the appropriate size. 3077 llvm::Type* ElemTy; 3078 unsigned SizeRegs; 3079 // FIXME: Try to match the types of the arguments more accurately where 3080 // we can. 3081 if (getContext().getTypeAlign(Ty) <= 32) { 3082 ElemTy = llvm::Type::getInt32Ty(getVMContext()); 3083 SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32; 3084 } else { 3085 ElemTy = llvm::Type::getInt64Ty(getVMContext()); 3086 SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64; 3087 } 3088 3089 llvm::Type *STy = 3090 llvm::StructType::get(llvm::ArrayType::get(ElemTy, SizeRegs), NULL); 3091 return ABIArgInfo::getDirect(STy); 3092} 3093 3094static bool isIntegerLikeType(QualType Ty, ASTContext &Context, 3095 llvm::LLVMContext &VMContext) { 3096 // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure 3097 // is called integer-like if its size is less than or equal to one word, and 3098 // the offset of each of its addressable sub-fields is zero. 3099 3100 uint64_t Size = Context.getTypeSize(Ty); 3101 3102 // Check that the type fits in a word. 3103 if (Size > 32) 3104 return false; 3105 3106 // FIXME: Handle vector types! 3107 if (Ty->isVectorType()) 3108 return false; 3109 3110 // Float types are never treated as "integer like". 3111 if (Ty->isRealFloatingType()) 3112 return false; 3113 3114 // If this is a builtin or pointer type then it is ok. 3115 if (Ty->getAs<BuiltinType>() || Ty->isPointerType()) 3116 return true; 3117 3118 // Small complex integer types are "integer like". 3119 if (const ComplexType *CT = Ty->getAs<ComplexType>()) 3120 return isIntegerLikeType(CT->getElementType(), Context, VMContext); 3121 3122 // Single element and zero sized arrays should be allowed, by the definition 3123 // above, but they are not. 3124 3125 // Otherwise, it must be a record type. 3126 const RecordType *RT = Ty->getAs<RecordType>(); 3127 if (!RT) return false; 3128 3129 // Ignore records with flexible arrays. 3130 const RecordDecl *RD = RT->getDecl(); 3131 if (RD->hasFlexibleArrayMember()) 3132 return false; 3133 3134 // Check that all sub-fields are at offset 0, and are themselves "integer 3135 // like". 3136 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD); 3137 3138 bool HadField = false; 3139 unsigned idx = 0; 3140 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3141 i != e; ++i, ++idx) { 3142 const FieldDecl *FD = *i; 3143 3144 // Bit-fields are not addressable, we only need to verify they are "integer 3145 // like". We still have to disallow a subsequent non-bitfield, for example: 3146 // struct { int : 0; int x } 3147 // is non-integer like according to gcc. 3148 if (FD->isBitField()) { 3149 if (!RD->isUnion()) 3150 HadField = true; 3151 3152 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3153 return false; 3154 3155 continue; 3156 } 3157 3158 // Check if this field is at offset 0. 3159 if (Layout.getFieldOffset(idx) != 0) 3160 return false; 3161 3162 if (!isIntegerLikeType(FD->getType(), Context, VMContext)) 3163 return false; 3164 3165 // Only allow at most one field in a structure. This doesn't match the 3166 // wording above, but follows gcc in situations with a field following an 3167 // empty structure. 3168 if (!RD->isUnion()) { 3169 if (HadField) 3170 return false; 3171 3172 HadField = true; 3173 } 3174 } 3175 3176 return true; 3177} 3178 3179ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy) const { 3180 if (RetTy->isVoidType()) 3181 return ABIArgInfo::getIgnore(); 3182 3183 // Large vector types should be returned via memory. 3184 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) 3185 return ABIArgInfo::getIndirect(0); 3186 3187 if (!isAggregateTypeForABI(RetTy)) { 3188 // Treat an enum type as its underlying type. 3189 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 3190 RetTy = EnumTy->getDecl()->getIntegerType(); 3191 3192 return (RetTy->isPromotableIntegerType() ? 3193 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3194 } 3195 3196 // Structures with either a non-trivial destructor or a non-trivial 3197 // copy constructor are always indirect. 3198 if (isRecordWithNonTrivialDestructorOrCopyConstructor(RetTy)) 3199 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3200 3201 // Are we following APCS? 3202 if (getABIKind() == APCS) { 3203 if (isEmptyRecord(getContext(), RetTy, false)) 3204 return ABIArgInfo::getIgnore(); 3205 3206 // Complex types are all returned as packed integers. 3207 // 3208 // FIXME: Consider using 2 x vector types if the back end handles them 3209 // correctly. 3210 if (RetTy->isAnyComplexType()) 3211 return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 3212 getContext().getTypeSize(RetTy))); 3213 3214 // Integer like structures are returned in r0. 3215 if (isIntegerLikeType(RetTy, getContext(), getVMContext())) { 3216 // Return in the smallest viable integer type. 3217 uint64_t Size = getContext().getTypeSize(RetTy); 3218 if (Size <= 8) 3219 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3220 if (Size <= 16) 3221 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3222 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3223 } 3224 3225 // Otherwise return in memory. 3226 return ABIArgInfo::getIndirect(0); 3227 } 3228 3229 // Otherwise this is an AAPCS variant. 3230 3231 if (isEmptyRecord(getContext(), RetTy, true)) 3232 return ABIArgInfo::getIgnore(); 3233 3234 // Check for homogeneous aggregates with AAPCS-VFP. 3235 if (getABIKind() == AAPCS_VFP) { 3236 const Type *Base = 0; 3237 if (isHomogeneousAggregate(RetTy, Base, getContext())) { 3238 assert(Base && "Base class should be set for homogeneous aggregate"); 3239 // Homogeneous Aggregates are returned directly. 3240 return ABIArgInfo::getDirect(); 3241 } 3242 } 3243 3244 // Aggregates <= 4 bytes are returned in r0; other aggregates 3245 // are returned indirectly. 3246 uint64_t Size = getContext().getTypeSize(RetTy); 3247 if (Size <= 32) { 3248 // Return in the smallest viable integer type. 3249 if (Size <= 8) 3250 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 3251 if (Size <= 16) 3252 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 3253 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 3254 } 3255 3256 return ABIArgInfo::getIndirect(0); 3257} 3258 3259/// isIllegalVector - check whether Ty is an illegal vector type. 3260bool ARMABIInfo::isIllegalVectorType(QualType Ty) const { 3261 if (const VectorType *VT = Ty->getAs<VectorType>()) { 3262 // Check whether VT is legal. 3263 unsigned NumElements = VT->getNumElements(); 3264 uint64_t Size = getContext().getTypeSize(VT); 3265 // NumElements should be power of 2. 3266 if ((NumElements & (NumElements - 1)) != 0) 3267 return true; 3268 // Size should be greater than 32 bits. 3269 return Size <= 32; 3270 } 3271 return false; 3272} 3273 3274llvm::Value *ARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3275 CodeGenFunction &CGF) const { 3276 llvm::Type *BP = CGF.Int8PtrTy; 3277 llvm::Type *BPP = CGF.Int8PtrPtrTy; 3278 3279 CGBuilderTy &Builder = CGF.Builder; 3280 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 3281 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 3282 3283 uint64_t Size = CGF.getContext().getTypeSize(Ty) / 8; 3284 uint64_t TyAlign = CGF.getContext().getTypeAlign(Ty) / 8; 3285 bool IsIndirect = false; 3286 3287 // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for 3288 // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte. 3289 if (getABIKind() == ARMABIInfo::AAPCS_VFP || 3290 getABIKind() == ARMABIInfo::AAPCS) 3291 TyAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); 3292 else 3293 TyAlign = 4; 3294 // Use indirect if size of the illegal vector is bigger than 16 bytes. 3295 if (isIllegalVectorType(Ty) && Size > 16) { 3296 IsIndirect = true; 3297 Size = 4; 3298 TyAlign = 4; 3299 } 3300 3301 // Handle address alignment for ABI alignment > 4 bytes. 3302 if (TyAlign > 4) { 3303 assert((TyAlign & (TyAlign - 1)) == 0 && 3304 "Alignment is not power of 2!"); 3305 llvm::Value *AddrAsInt = Builder.CreatePtrToInt(Addr, CGF.Int32Ty); 3306 AddrAsInt = Builder.CreateAdd(AddrAsInt, Builder.getInt32(TyAlign - 1)); 3307 AddrAsInt = Builder.CreateAnd(AddrAsInt, Builder.getInt32(~(TyAlign - 1))); 3308 Addr = Builder.CreateIntToPtr(AddrAsInt, BP, "ap.align"); 3309 } 3310 3311 uint64_t Offset = 3312 llvm::RoundUpToAlignment(Size, 4); 3313 llvm::Value *NextAddr = 3314 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 3315 "ap.next"); 3316 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 3317 3318 if (IsIndirect) 3319 Addr = Builder.CreateLoad(Builder.CreateBitCast(Addr, BPP)); 3320 else if (TyAlign < CGF.getContext().getTypeAlign(Ty) / 8) { 3321 // We can't directly cast ap.cur to pointer to a vector type, since ap.cur 3322 // may not be correctly aligned for the vector type. We create an aligned 3323 // temporary space and copy the content over from ap.cur to the temporary 3324 // space. This is necessary if the natural alignment of the type is greater 3325 // than the ABI alignment. 3326 llvm::Type *I8PtrTy = Builder.getInt8PtrTy(); 3327 CharUnits CharSize = getContext().getTypeSizeInChars(Ty); 3328 llvm::Value *AlignedTemp = CGF.CreateTempAlloca(CGF.ConvertType(Ty), 3329 "var.align"); 3330 llvm::Value *Dst = Builder.CreateBitCast(AlignedTemp, I8PtrTy); 3331 llvm::Value *Src = Builder.CreateBitCast(Addr, I8PtrTy); 3332 Builder.CreateMemCpy(Dst, Src, 3333 llvm::ConstantInt::get(CGF.IntPtrTy, CharSize.getQuantity()), 3334 TyAlign, false); 3335 Addr = AlignedTemp; //The content is in aligned location. 3336 } 3337 llvm::Type *PTy = 3338 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 3339 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 3340 3341 return AddrTyped; 3342} 3343 3344namespace { 3345 3346class NaClARMABIInfo : public ABIInfo { 3347 public: 3348 NaClARMABIInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3349 : ABIInfo(CGT), PInfo(CGT), NInfo(CGT, Kind) {} 3350 virtual void computeInfo(CGFunctionInfo &FI) const; 3351 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3352 CodeGenFunction &CGF) const; 3353 private: 3354 PNaClABIInfo PInfo; // Used for generating calls with pnaclcall callingconv. 3355 ARMABIInfo NInfo; // Used for everything else. 3356}; 3357 3358class NaClARMTargetCodeGenInfo : public TargetCodeGenInfo { 3359 public: 3360 NaClARMTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, ARMABIInfo::ABIKind Kind) 3361 : TargetCodeGenInfo(new NaClARMABIInfo(CGT, Kind)) {} 3362}; 3363 3364} 3365 3366void NaClARMABIInfo::computeInfo(CGFunctionInfo &FI) const { 3367 if (FI.getASTCallingConvention() == CC_PnaclCall) 3368 PInfo.computeInfo(FI); 3369 else 3370 static_cast<const ABIInfo&>(NInfo).computeInfo(FI); 3371} 3372 3373llvm::Value *NaClARMABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3374 CodeGenFunction &CGF) const { 3375 // Always use the native convention; calling pnacl-style varargs functions 3376 // is unsupported. 3377 return static_cast<const ABIInfo&>(NInfo).EmitVAArg(VAListAddr, Ty, CGF); 3378} 3379 3380//===----------------------------------------------------------------------===// 3381// NVPTX ABI Implementation 3382//===----------------------------------------------------------------------===// 3383 3384namespace { 3385 3386class NVPTXABIInfo : public ABIInfo { 3387public: 3388 NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 3389 3390 ABIArgInfo classifyReturnType(QualType RetTy) const; 3391 ABIArgInfo classifyArgumentType(QualType Ty) const; 3392 3393 virtual void computeInfo(CGFunctionInfo &FI) const; 3394 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3395 CodeGenFunction &CFG) const; 3396}; 3397 3398class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo { 3399public: 3400 NVPTXTargetCodeGenInfo(CodeGenTypes &CGT) 3401 : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {} 3402 3403 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 3404 CodeGen::CodeGenModule &M) const; 3405}; 3406 3407ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const { 3408 if (RetTy->isVoidType()) 3409 return ABIArgInfo::getIgnore(); 3410 if (isAggregateTypeForABI(RetTy)) 3411 return ABIArgInfo::getIndirect(0); 3412 return ABIArgInfo::getDirect(); 3413} 3414 3415ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const { 3416 if (isAggregateTypeForABI(Ty)) 3417 return ABIArgInfo::getIndirect(0); 3418 3419 return ABIArgInfo::getDirect(); 3420} 3421 3422void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const { 3423 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 3424 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3425 it != ie; ++it) 3426 it->info = classifyArgumentType(it->type); 3427 3428 // Always honor user-specified calling convention. 3429 if (FI.getCallingConvention() != llvm::CallingConv::C) 3430 return; 3431 3432 // Calling convention as default by an ABI. 3433 // We're still using the PTX_Kernel/PTX_Device calling conventions here, 3434 // but we should switch to NVVM metadata later on. 3435 llvm::CallingConv::ID DefaultCC; 3436 const LangOptions &LangOpts = getContext().getLangOpts(); 3437 if (LangOpts.OpenCL || LangOpts.CUDA) { 3438 // If we are in OpenCL or CUDA mode, then default to device functions 3439 DefaultCC = llvm::CallingConv::PTX_Device; 3440 } else { 3441 // If we are in standard C/C++ mode, use the triple to decide on the default 3442 StringRef Env = 3443 getContext().getTargetInfo().getTriple().getEnvironmentName(); 3444 if (Env == "device") 3445 DefaultCC = llvm::CallingConv::PTX_Device; 3446 else 3447 DefaultCC = llvm::CallingConv::PTX_Kernel; 3448 } 3449 FI.setEffectiveCallingConvention(DefaultCC); 3450 3451} 3452 3453llvm::Value *NVPTXABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3454 CodeGenFunction &CFG) const { 3455 llvm_unreachable("NVPTX does not support varargs"); 3456} 3457 3458void NVPTXTargetCodeGenInfo:: 3459SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 3460 CodeGen::CodeGenModule &M) const{ 3461 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 3462 if (!FD) return; 3463 3464 llvm::Function *F = cast<llvm::Function>(GV); 3465 3466 // Perform special handling in OpenCL mode 3467 if (M.getLangOpts().OpenCL) { 3468 // Use OpenCL function attributes to set proper calling conventions 3469 // By default, all functions are device functions 3470 if (FD->hasAttr<OpenCLKernelAttr>()) { 3471 // OpenCL __kernel functions get a kernel calling convention 3472 F->setCallingConv(llvm::CallingConv::PTX_Kernel); 3473 // And kernel functions are not subject to inlining 3474 F->addFnAttr(llvm::Attributes::NoInline); 3475 } 3476 } 3477 3478 // Perform special handling in CUDA mode. 3479 if (M.getLangOpts().CUDA) { 3480 // CUDA __global__ functions get a kernel calling convention. Since 3481 // __global__ functions cannot be called from the device, we do not 3482 // need to set the noinline attribute. 3483 if (FD->getAttr<CUDAGlobalAttr>()) 3484 F->setCallingConv(llvm::CallingConv::PTX_Kernel); 3485 } 3486} 3487 3488} 3489 3490//===----------------------------------------------------------------------===// 3491// MBlaze ABI Implementation 3492//===----------------------------------------------------------------------===// 3493 3494namespace { 3495 3496class MBlazeABIInfo : public ABIInfo { 3497public: 3498 MBlazeABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 3499 3500 bool isPromotableIntegerType(QualType Ty) const; 3501 3502 ABIArgInfo classifyReturnType(QualType RetTy) const; 3503 ABIArgInfo classifyArgumentType(QualType RetTy) const; 3504 3505 virtual void computeInfo(CGFunctionInfo &FI) const { 3506 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 3507 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3508 it != ie; ++it) 3509 it->info = classifyArgumentType(it->type); 3510 } 3511 3512 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3513 CodeGenFunction &CGF) const; 3514}; 3515 3516class MBlazeTargetCodeGenInfo : public TargetCodeGenInfo { 3517public: 3518 MBlazeTargetCodeGenInfo(CodeGenTypes &CGT) 3519 : TargetCodeGenInfo(new MBlazeABIInfo(CGT)) {} 3520 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 3521 CodeGen::CodeGenModule &M) const; 3522}; 3523 3524} 3525 3526bool MBlazeABIInfo::isPromotableIntegerType(QualType Ty) const { 3527 // MBlaze ABI requires all 8 and 16 bit quantities to be extended. 3528 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) 3529 switch (BT->getKind()) { 3530 case BuiltinType::Bool: 3531 case BuiltinType::Char_S: 3532 case BuiltinType::Char_U: 3533 case BuiltinType::SChar: 3534 case BuiltinType::UChar: 3535 case BuiltinType::Short: 3536 case BuiltinType::UShort: 3537 return true; 3538 default: 3539 return false; 3540 } 3541 return false; 3542} 3543 3544llvm::Value *MBlazeABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3545 CodeGenFunction &CGF) const { 3546 // FIXME: Implement 3547 return 0; 3548} 3549 3550 3551ABIArgInfo MBlazeABIInfo::classifyReturnType(QualType RetTy) const { 3552 if (RetTy->isVoidType()) 3553 return ABIArgInfo::getIgnore(); 3554 if (isAggregateTypeForABI(RetTy)) 3555 return ABIArgInfo::getIndirect(0); 3556 3557 return (isPromotableIntegerType(RetTy) ? 3558 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3559} 3560 3561ABIArgInfo MBlazeABIInfo::classifyArgumentType(QualType Ty) const { 3562 if (isAggregateTypeForABI(Ty)) 3563 return ABIArgInfo::getIndirect(0); 3564 3565 return (isPromotableIntegerType(Ty) ? 3566 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3567} 3568 3569void MBlazeTargetCodeGenInfo::SetTargetAttributes(const Decl *D, 3570 llvm::GlobalValue *GV, 3571 CodeGen::CodeGenModule &M) 3572 const { 3573 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 3574 if (!FD) return; 3575 3576 llvm::CallingConv::ID CC = llvm::CallingConv::C; 3577 if (FD->hasAttr<MBlazeInterruptHandlerAttr>()) 3578 CC = llvm::CallingConv::MBLAZE_INTR; 3579 else if (FD->hasAttr<MBlazeSaveVolatilesAttr>()) 3580 CC = llvm::CallingConv::MBLAZE_SVOL; 3581 3582 if (CC != llvm::CallingConv::C) { 3583 // Handle 'interrupt_handler' attribute: 3584 llvm::Function *F = cast<llvm::Function>(GV); 3585 3586 // Step 1: Set ISR calling convention. 3587 F->setCallingConv(CC); 3588 3589 // Step 2: Add attributes goodness. 3590 F->addFnAttr(llvm::Attributes::NoInline); 3591 } 3592 3593 // Step 3: Emit _interrupt_handler alias. 3594 if (CC == llvm::CallingConv::MBLAZE_INTR) 3595 new llvm::GlobalAlias(GV->getType(), llvm::Function::ExternalLinkage, 3596 "_interrupt_handler", GV, &M.getModule()); 3597} 3598 3599 3600//===----------------------------------------------------------------------===// 3601// MSP430 ABI Implementation 3602//===----------------------------------------------------------------------===// 3603 3604namespace { 3605 3606class MSP430TargetCodeGenInfo : public TargetCodeGenInfo { 3607public: 3608 MSP430TargetCodeGenInfo(CodeGenTypes &CGT) 3609 : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {} 3610 void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 3611 CodeGen::CodeGenModule &M) const; 3612}; 3613 3614} 3615 3616void MSP430TargetCodeGenInfo::SetTargetAttributes(const Decl *D, 3617 llvm::GlobalValue *GV, 3618 CodeGen::CodeGenModule &M) const { 3619 if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) { 3620 if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) { 3621 // Handle 'interrupt' attribute: 3622 llvm::Function *F = cast<llvm::Function>(GV); 3623 3624 // Step 1: Set ISR calling convention. 3625 F->setCallingConv(llvm::CallingConv::MSP430_INTR); 3626 3627 // Step 2: Add attributes goodness. 3628 F->addFnAttr(llvm::Attributes::NoInline); 3629 3630 // Step 3: Emit ISR vector alias. 3631 unsigned Num = attr->getNumber() + 0xffe0; 3632 new llvm::GlobalAlias(GV->getType(), llvm::Function::ExternalLinkage, 3633 "vector_" + Twine::utohexstr(Num), 3634 GV, &M.getModule()); 3635 } 3636 } 3637} 3638 3639//===----------------------------------------------------------------------===// 3640// MIPS ABI Implementation. This works for both little-endian and 3641// big-endian variants. 3642//===----------------------------------------------------------------------===// 3643 3644namespace { 3645class MipsABIInfo : public ABIInfo { 3646 bool IsO32; 3647 unsigned MinABIStackAlignInBytes, StackAlignInBytes; 3648 void CoerceToIntArgs(uint64_t TySize, 3649 SmallVector<llvm::Type*, 8> &ArgList) const; 3650 llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const; 3651 llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const; 3652 llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const; 3653public: 3654 MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) : 3655 ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8), 3656 StackAlignInBytes(IsO32 ? 8 : 16) {} 3657 3658 ABIArgInfo classifyReturnType(QualType RetTy) const; 3659 ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const; 3660 virtual void computeInfo(CGFunctionInfo &FI) const; 3661 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3662 CodeGenFunction &CGF) const; 3663}; 3664 3665class MIPSTargetCodeGenInfo : public TargetCodeGenInfo { 3666 unsigned SizeOfUnwindException; 3667public: 3668 MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32) 3669 : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)), 3670 SizeOfUnwindException(IsO32 ? 24 : 32) {} 3671 3672 int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const { 3673 return 29; 3674 } 3675 3676 bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3677 llvm::Value *Address) const; 3678 3679 unsigned getSizeOfUnwindException() const { 3680 return SizeOfUnwindException; 3681 } 3682}; 3683} 3684 3685void MipsABIInfo::CoerceToIntArgs(uint64_t TySize, 3686 SmallVector<llvm::Type*, 8> &ArgList) const { 3687 llvm::IntegerType *IntTy = 3688 llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 3689 3690 // Add (TySize / MinABIStackAlignInBytes) args of IntTy. 3691 for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N) 3692 ArgList.push_back(IntTy); 3693 3694 // If necessary, add one more integer type to ArgList. 3695 unsigned R = TySize % (MinABIStackAlignInBytes * 8); 3696 3697 if (R) 3698 ArgList.push_back(llvm::IntegerType::get(getVMContext(), R)); 3699} 3700 3701// In N32/64, an aligned double precision floating point field is passed in 3702// a register. 3703llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const { 3704 SmallVector<llvm::Type*, 8> ArgList, IntArgList; 3705 3706 if (IsO32) { 3707 CoerceToIntArgs(TySize, ArgList); 3708 return llvm::StructType::get(getVMContext(), ArgList); 3709 } 3710 3711 if (Ty->isComplexType()) 3712 return CGT.ConvertType(Ty); 3713 3714 const RecordType *RT = Ty->getAs<RecordType>(); 3715 3716 // Unions/vectors are passed in integer registers. 3717 if (!RT || !RT->isStructureOrClassType()) { 3718 CoerceToIntArgs(TySize, ArgList); 3719 return llvm::StructType::get(getVMContext(), ArgList); 3720 } 3721 3722 const RecordDecl *RD = RT->getDecl(); 3723 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 3724 assert(!(TySize % 8) && "Size of structure must be multiple of 8."); 3725 3726 uint64_t LastOffset = 0; 3727 unsigned idx = 0; 3728 llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64); 3729 3730 // Iterate over fields in the struct/class and check if there are any aligned 3731 // double fields. 3732 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end(); 3733 i != e; ++i, ++idx) { 3734 const QualType Ty = i->getType(); 3735 const BuiltinType *BT = Ty->getAs<BuiltinType>(); 3736 3737 if (!BT || BT->getKind() != BuiltinType::Double) 3738 continue; 3739 3740 uint64_t Offset = Layout.getFieldOffset(idx); 3741 if (Offset % 64) // Ignore doubles that are not aligned. 3742 continue; 3743 3744 // Add ((Offset - LastOffset) / 64) args of type i64. 3745 for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j) 3746 ArgList.push_back(I64); 3747 3748 // Add double type. 3749 ArgList.push_back(llvm::Type::getDoubleTy(getVMContext())); 3750 LastOffset = Offset + 64; 3751 } 3752 3753 CoerceToIntArgs(TySize - LastOffset, IntArgList); 3754 ArgList.append(IntArgList.begin(), IntArgList.end()); 3755 3756 return llvm::StructType::get(getVMContext(), ArgList); 3757} 3758 3759llvm::Type *MipsABIInfo::getPaddingType(uint64_t Align, uint64_t Offset) const { 3760 assert((Offset % MinABIStackAlignInBytes) == 0); 3761 3762 if ((Align - 1) & Offset) 3763 return llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8); 3764 3765 return 0; 3766} 3767 3768ABIArgInfo 3769MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const { 3770 uint64_t OrigOffset = Offset; 3771 uint64_t TySize = getContext().getTypeSize(Ty); 3772 uint64_t Align = getContext().getTypeAlign(Ty) / 8; 3773 3774 Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes), 3775 (uint64_t)StackAlignInBytes); 3776 Offset = llvm::RoundUpToAlignment(Offset, Align); 3777 Offset += llvm::RoundUpToAlignment(TySize, Align * 8) / 8; 3778 3779 if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) { 3780 // Ignore empty aggregates. 3781 if (TySize == 0) 3782 return ABIArgInfo::getIgnore(); 3783 3784 // Records with non trivial destructors/constructors should not be passed 3785 // by value. 3786 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) { 3787 Offset = OrigOffset + MinABIStackAlignInBytes; 3788 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 3789 } 3790 3791 // If we have reached here, aggregates are passed directly by coercing to 3792 // another structure type. Padding is inserted if the offset of the 3793 // aggregate is unaligned. 3794 return ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0, 3795 getPaddingType(Align, OrigOffset)); 3796 } 3797 3798 // Treat an enum type as its underlying type. 3799 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 3800 Ty = EnumTy->getDecl()->getIntegerType(); 3801 3802 if (Ty->isPromotableIntegerType()) 3803 return ABIArgInfo::getExtend(); 3804 3805 return ABIArgInfo::getDirect(0, 0, getPaddingType(Align, OrigOffset)); 3806} 3807 3808llvm::Type* 3809MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const { 3810 const RecordType *RT = RetTy->getAs<RecordType>(); 3811 SmallVector<llvm::Type*, 8> RTList; 3812 3813 if (RT && RT->isStructureOrClassType()) { 3814 const RecordDecl *RD = RT->getDecl(); 3815 const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD); 3816 unsigned FieldCnt = Layout.getFieldCount(); 3817 3818 // N32/64 returns struct/classes in floating point registers if the 3819 // following conditions are met: 3820 // 1. The size of the struct/class is no larger than 128-bit. 3821 // 2. The struct/class has one or two fields all of which are floating 3822 // point types. 3823 // 3. The offset of the first field is zero (this follows what gcc does). 3824 // 3825 // Any other composite results are returned in integer registers. 3826 // 3827 if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) { 3828 RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end(); 3829 for (; b != e; ++b) { 3830 const BuiltinType *BT = b->getType()->getAs<BuiltinType>(); 3831 3832 if (!BT || !BT->isFloatingPoint()) 3833 break; 3834 3835 RTList.push_back(CGT.ConvertType(b->getType())); 3836 } 3837 3838 if (b == e) 3839 return llvm::StructType::get(getVMContext(), RTList, 3840 RD->hasAttr<PackedAttr>()); 3841 3842 RTList.clear(); 3843 } 3844 } 3845 3846 CoerceToIntArgs(Size, RTList); 3847 return llvm::StructType::get(getVMContext(), RTList); 3848} 3849 3850ABIArgInfo MipsABIInfo::classifyReturnType(QualType RetTy) const { 3851 uint64_t Size = getContext().getTypeSize(RetTy); 3852 3853 if (RetTy->isVoidType() || Size == 0) 3854 return ABIArgInfo::getIgnore(); 3855 3856 if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) { 3857 if (Size <= 128) { 3858 if (RetTy->isAnyComplexType()) 3859 return ABIArgInfo::getDirect(); 3860 3861 // O32 returns integer vectors in registers. 3862 if (IsO32 && RetTy->isVectorType() && !RetTy->hasFloatingRepresentation()) 3863 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 3864 3865 if (!IsO32 && !isRecordWithNonTrivialDestructorOrCopyConstructor(RetTy)) 3866 return ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size)); 3867 } 3868 3869 return ABIArgInfo::getIndirect(0); 3870 } 3871 3872 // Treat an enum type as its underlying type. 3873 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 3874 RetTy = EnumTy->getDecl()->getIntegerType(); 3875 3876 return (RetTy->isPromotableIntegerType() ? 3877 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 3878} 3879 3880void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const { 3881 ABIArgInfo &RetInfo = FI.getReturnInfo(); 3882 RetInfo = classifyReturnType(FI.getReturnType()); 3883 3884 // Check if a pointer to an aggregate is passed as a hidden argument. 3885 uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0; 3886 3887 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 3888 it != ie; ++it) 3889 it->info = classifyArgumentType(it->type, Offset); 3890} 3891 3892llvm::Value* MipsABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 3893 CodeGenFunction &CGF) const { 3894 llvm::Type *BP = CGF.Int8PtrTy; 3895 llvm::Type *BPP = CGF.Int8PtrPtrTy; 3896 3897 CGBuilderTy &Builder = CGF.Builder; 3898 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, "ap"); 3899 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 3900 int64_t TypeAlign = getContext().getTypeAlign(Ty) / 8; 3901 llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 3902 llvm::Value *AddrTyped; 3903 unsigned PtrWidth = getContext().getTargetInfo().getPointerWidth(0); 3904 llvm::IntegerType *IntTy = (PtrWidth == 32) ? CGF.Int32Ty : CGF.Int64Ty; 3905 3906 if (TypeAlign > MinABIStackAlignInBytes) { 3907 llvm::Value *AddrAsInt = CGF.Builder.CreatePtrToInt(Addr, IntTy); 3908 llvm::Value *Inc = llvm::ConstantInt::get(IntTy, TypeAlign - 1); 3909 llvm::Value *Mask = llvm::ConstantInt::get(IntTy, -TypeAlign); 3910 llvm::Value *Add = CGF.Builder.CreateAdd(AddrAsInt, Inc); 3911 llvm::Value *And = CGF.Builder.CreateAnd(Add, Mask); 3912 AddrTyped = CGF.Builder.CreateIntToPtr(And, PTy); 3913 } 3914 else 3915 AddrTyped = Builder.CreateBitCast(Addr, PTy); 3916 3917 llvm::Value *AlignedAddr = Builder.CreateBitCast(AddrTyped, BP); 3918 TypeAlign = std::max((unsigned)TypeAlign, MinABIStackAlignInBytes); 3919 uint64_t Offset = 3920 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, TypeAlign); 3921 llvm::Value *NextAddr = 3922 Builder.CreateGEP(AlignedAddr, llvm::ConstantInt::get(IntTy, Offset), 3923 "ap.next"); 3924 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 3925 3926 return AddrTyped; 3927} 3928 3929bool 3930MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, 3931 llvm::Value *Address) const { 3932 // This information comes from gcc's implementation, which seems to 3933 // as canonical as it gets. 3934 3935 // Everything on MIPS is 4 bytes. Double-precision FP registers 3936 // are aliased to pairs of single-precision FP registers. 3937 llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); 3938 3939 // 0-31 are the general purpose registers, $0 - $31. 3940 // 32-63 are the floating-point registers, $f0 - $f31. 3941 // 64 and 65 are the multiply/divide registers, $hi and $lo. 3942 // 66 is the (notional, I think) register for signal-handler return. 3943 AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65); 3944 3945 // 67-74 are the floating-point status registers, $fcc0 - $fcc7. 3946 // They are one bit wide and ignored here. 3947 3948 // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31. 3949 // (coprocessor 1 is the FP unit) 3950 // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31. 3951 // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31. 3952 // 176-181 are the DSP accumulator registers. 3953 AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181); 3954 return false; 3955} 3956 3957//===----------------------------------------------------------------------===// 3958// TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults. 3959// Currently subclassed only to implement custom OpenCL C function attribute 3960// handling. 3961//===----------------------------------------------------------------------===// 3962 3963namespace { 3964 3965class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo { 3966public: 3967 TCETargetCodeGenInfo(CodeGenTypes &CGT) 3968 : DefaultTargetCodeGenInfo(CGT) {} 3969 3970 virtual void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV, 3971 CodeGen::CodeGenModule &M) const; 3972}; 3973 3974void TCETargetCodeGenInfo::SetTargetAttributes(const Decl *D, 3975 llvm::GlobalValue *GV, 3976 CodeGen::CodeGenModule &M) const { 3977 const FunctionDecl *FD = dyn_cast<FunctionDecl>(D); 3978 if (!FD) return; 3979 3980 llvm::Function *F = cast<llvm::Function>(GV); 3981 3982 if (M.getLangOpts().OpenCL) { 3983 if (FD->hasAttr<OpenCLKernelAttr>()) { 3984 // OpenCL C Kernel functions are not subject to inlining 3985 F->addFnAttr(llvm::Attributes::NoInline); 3986 3987 if (FD->hasAttr<ReqdWorkGroupSizeAttr>()) { 3988 3989 // Convert the reqd_work_group_size() attributes to metadata. 3990 llvm::LLVMContext &Context = F->getContext(); 3991 llvm::NamedMDNode *OpenCLMetadata = 3992 M.getModule().getOrInsertNamedMetadata("opencl.kernel_wg_size_info"); 3993 3994 SmallVector<llvm::Value*, 5> Operands; 3995 Operands.push_back(F); 3996 3997 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 3998 llvm::APInt(32, 3999 FD->getAttr<ReqdWorkGroupSizeAttr>()->getXDim()))); 4000 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4001 llvm::APInt(32, 4002 FD->getAttr<ReqdWorkGroupSizeAttr>()->getYDim()))); 4003 Operands.push_back(llvm::Constant::getIntegerValue(M.Int32Ty, 4004 llvm::APInt(32, 4005 FD->getAttr<ReqdWorkGroupSizeAttr>()->getZDim()))); 4006 4007 // Add a boolean constant operand for "required" (true) or "hint" (false) 4008 // for implementing the work_group_size_hint attr later. Currently 4009 // always true as the hint is not yet implemented. 4010 Operands.push_back(llvm::ConstantInt::getTrue(Context)); 4011 OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands)); 4012 } 4013 } 4014 } 4015} 4016 4017} 4018 4019//===----------------------------------------------------------------------===// 4020// Hexagon ABI Implementation 4021//===----------------------------------------------------------------------===// 4022 4023namespace { 4024 4025class HexagonABIInfo : public ABIInfo { 4026 4027 4028public: 4029 HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} 4030 4031private: 4032 4033 ABIArgInfo classifyReturnType(QualType RetTy) const; 4034 ABIArgInfo classifyArgumentType(QualType RetTy) const; 4035 4036 virtual void computeInfo(CGFunctionInfo &FI) const; 4037 4038 virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4039 CodeGenFunction &CGF) const; 4040}; 4041 4042class HexagonTargetCodeGenInfo : public TargetCodeGenInfo { 4043public: 4044 HexagonTargetCodeGenInfo(CodeGenTypes &CGT) 4045 :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {} 4046 4047 int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const { 4048 return 29; 4049 } 4050}; 4051 4052} 4053 4054void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const { 4055 FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); 4056 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end(); 4057 it != ie; ++it) 4058 it->info = classifyArgumentType(it->type); 4059} 4060 4061ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const { 4062 if (!isAggregateTypeForABI(Ty)) { 4063 // Treat an enum type as its underlying type. 4064 if (const EnumType *EnumTy = Ty->getAs<EnumType>()) 4065 Ty = EnumTy->getDecl()->getIntegerType(); 4066 4067 return (Ty->isPromotableIntegerType() ? 4068 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4069 } 4070 4071 // Ignore empty records. 4072 if (isEmptyRecord(getContext(), Ty, true)) 4073 return ABIArgInfo::getIgnore(); 4074 4075 // Structures with either a non-trivial destructor or a non-trivial 4076 // copy constructor are always indirect. 4077 if (isRecordWithNonTrivialDestructorOrCopyConstructor(Ty)) 4078 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 4079 4080 uint64_t Size = getContext().getTypeSize(Ty); 4081 if (Size > 64) 4082 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 4083 // Pass in the smallest viable integer type. 4084 else if (Size > 32) 4085 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 4086 else if (Size > 16) 4087 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 4088 else if (Size > 8) 4089 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 4090 else 4091 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 4092} 4093 4094ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const { 4095 if (RetTy->isVoidType()) 4096 return ABIArgInfo::getIgnore(); 4097 4098 // Large vector types should be returned via memory. 4099 if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64) 4100 return ABIArgInfo::getIndirect(0); 4101 4102 if (!isAggregateTypeForABI(RetTy)) { 4103 // Treat an enum type as its underlying type. 4104 if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) 4105 RetTy = EnumTy->getDecl()->getIntegerType(); 4106 4107 return (RetTy->isPromotableIntegerType() ? 4108 ABIArgInfo::getExtend() : ABIArgInfo::getDirect()); 4109 } 4110 4111 // Structures with either a non-trivial destructor or a non-trivial 4112 // copy constructor are always indirect. 4113 if (isRecordWithNonTrivialDestructorOrCopyConstructor(RetTy)) 4114 return ABIArgInfo::getIndirect(0, /*ByVal=*/false); 4115 4116 if (isEmptyRecord(getContext(), RetTy, true)) 4117 return ABIArgInfo::getIgnore(); 4118 4119 // Aggregates <= 8 bytes are returned in r0; other aggregates 4120 // are returned indirectly. 4121 uint64_t Size = getContext().getTypeSize(RetTy); 4122 if (Size <= 64) { 4123 // Return in the smallest viable integer type. 4124 if (Size <= 8) 4125 return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); 4126 if (Size <= 16) 4127 return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); 4128 if (Size <= 32) 4129 return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); 4130 return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); 4131 } 4132 4133 return ABIArgInfo::getIndirect(0, /*ByVal=*/true); 4134} 4135 4136llvm::Value *HexagonABIInfo::EmitVAArg(llvm::Value *VAListAddr, QualType Ty, 4137 CodeGenFunction &CGF) const { 4138 // FIXME: Need to handle alignment 4139 llvm::Type *BPP = CGF.Int8PtrPtrTy; 4140 4141 CGBuilderTy &Builder = CGF.Builder; 4142 llvm::Value *VAListAddrAsBPP = Builder.CreateBitCast(VAListAddr, BPP, 4143 "ap"); 4144 llvm::Value *Addr = Builder.CreateLoad(VAListAddrAsBPP, "ap.cur"); 4145 llvm::Type *PTy = 4146 llvm::PointerType::getUnqual(CGF.ConvertType(Ty)); 4147 llvm::Value *AddrTyped = Builder.CreateBitCast(Addr, PTy); 4148 4149 uint64_t Offset = 4150 llvm::RoundUpToAlignment(CGF.getContext().getTypeSize(Ty) / 8, 4); 4151 llvm::Value *NextAddr = 4152 Builder.CreateGEP(Addr, llvm::ConstantInt::get(CGF.Int32Ty, Offset), 4153 "ap.next"); 4154 Builder.CreateStore(NextAddr, VAListAddrAsBPP); 4155 4156 return AddrTyped; 4157} 4158 4159 4160const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() { 4161 if (TheTargetCodeGenInfo) 4162 return *TheTargetCodeGenInfo; 4163 4164 const llvm::Triple &Triple = getContext().getTargetInfo().getTriple(); 4165 switch (Triple.getArch()) { 4166 default: 4167 return *(TheTargetCodeGenInfo = new DefaultTargetCodeGenInfo(Types)); 4168 4169 case llvm::Triple::le32: 4170 return *(TheTargetCodeGenInfo = new PNaClTargetCodeGenInfo(Types)); 4171 case llvm::Triple::mips: 4172 case llvm::Triple::mipsel: 4173 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, true)); 4174 4175 case llvm::Triple::mips64: 4176 case llvm::Triple::mips64el: 4177 return *(TheTargetCodeGenInfo = new MIPSTargetCodeGenInfo(Types, false)); 4178 4179 case llvm::Triple::arm: 4180 case llvm::Triple::thumb: 4181 { 4182 ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS; 4183 4184 if (strcmp(getContext().getTargetInfo().getABI(), "apcs-gnu") == 0) 4185 Kind = ARMABIInfo::APCS; 4186 else if (CodeGenOpts.FloatABI == "hard") 4187 Kind = ARMABIInfo::AAPCS_VFP; 4188 4189 switch (Triple.getOS()) { 4190 case llvm::Triple::NativeClient: 4191 return *(TheTargetCodeGenInfo = 4192 new NaClARMTargetCodeGenInfo(Types, Kind)); 4193 default: 4194 return *(TheTargetCodeGenInfo = 4195 new ARMTargetCodeGenInfo(Types, Kind)); 4196 } 4197 } 4198 4199 case llvm::Triple::ppc: 4200 return *(TheTargetCodeGenInfo = new PPC32TargetCodeGenInfo(Types)); 4201 case llvm::Triple::ppc64: 4202 if (Triple.isOSBinFormatELF()) 4203 return *(TheTargetCodeGenInfo = new PPC64_SVR4_TargetCodeGenInfo(Types)); 4204 else 4205 return *(TheTargetCodeGenInfo = new PPC64TargetCodeGenInfo(Types)); 4206 4207 case llvm::Triple::nvptx: 4208 case llvm::Triple::nvptx64: 4209 return *(TheTargetCodeGenInfo = new NVPTXTargetCodeGenInfo(Types)); 4210 4211 case llvm::Triple::mblaze: 4212 return *(TheTargetCodeGenInfo = new MBlazeTargetCodeGenInfo(Types)); 4213 4214 case llvm::Triple::msp430: 4215 return *(TheTargetCodeGenInfo = new MSP430TargetCodeGenInfo(Types)); 4216 4217 case llvm::Triple::tce: 4218 return *(TheTargetCodeGenInfo = new TCETargetCodeGenInfo(Types)); 4219 4220 case llvm::Triple::x86: { 4221 bool DisableMMX = strcmp(getContext().getTargetInfo().getABI(), "no-mmx") == 0; 4222 4223 if (Triple.isOSDarwin()) 4224 return *(TheTargetCodeGenInfo = 4225 new X86_32TargetCodeGenInfo(Types, true, true, DisableMMX, false, 4226 CodeGenOpts.NumRegisterParameters)); 4227 4228 switch (Triple.getOS()) { 4229 case llvm::Triple::Cygwin: 4230 case llvm::Triple::MinGW32: 4231 case llvm::Triple::AuroraUX: 4232 case llvm::Triple::DragonFly: 4233 case llvm::Triple::FreeBSD: 4234 case llvm::Triple::OpenBSD: 4235 case llvm::Triple::Bitrig: 4236 return *(TheTargetCodeGenInfo = 4237 new X86_32TargetCodeGenInfo(Types, false, true, DisableMMX, 4238 false, 4239 CodeGenOpts.NumRegisterParameters)); 4240 4241 case llvm::Triple::Win32: 4242 return *(TheTargetCodeGenInfo = 4243 new X86_32TargetCodeGenInfo(Types, false, true, DisableMMX, true, 4244 CodeGenOpts.NumRegisterParameters)); 4245 4246 default: 4247 return *(TheTargetCodeGenInfo = 4248 new X86_32TargetCodeGenInfo(Types, false, false, DisableMMX, 4249 false, 4250 CodeGenOpts.NumRegisterParameters)); 4251 } 4252 } 4253 4254 case llvm::Triple::x86_64: { 4255 bool HasAVX = strcmp(getContext().getTargetInfo().getABI(), "avx") == 0; 4256 4257 switch (Triple.getOS()) { 4258 case llvm::Triple::Win32: 4259 case llvm::Triple::MinGW32: 4260 case llvm::Triple::Cygwin: 4261 return *(TheTargetCodeGenInfo = new WinX86_64TargetCodeGenInfo(Types)); 4262 case llvm::Triple::NativeClient: 4263 return *(TheTargetCodeGenInfo = new NaClX86_64TargetCodeGenInfo(Types, HasAVX)); 4264 default: 4265 return *(TheTargetCodeGenInfo = new X86_64TargetCodeGenInfo(Types, 4266 HasAVX)); 4267 } 4268 } 4269 case llvm::Triple::hexagon: 4270 return *(TheTargetCodeGenInfo = new HexagonTargetCodeGenInfo(Types)); 4271 } 4272} 4273