i386 revision 515d8d71521740a084d422b7bb7941ed5f3ee837
1%mask {s} 1 2%mask {w} 1 3%mask {w1} 1 4dnl floating point reg suffix 5%mask {D} 1 6%mask {imm8} 8 7%mask {imms8} 8 8%mask {imm16} 16 9%mask {reg} 3 10%mask {reg16} 3 11%mask {tttn} 4 12%mask {gg} 2 13%mask {mod} 2 14%mask {moda} 2 15%mask {MOD} 2 16%mask {r_m} 3 17dnl like {r_m} but referencing byte register 18%mask {8r_m} 3 19dnl like {r_m} but referencing 16-bit register 20%mask {16r_m} 3 21%mask {disp8} 8 22dnl imm really is 8/16/32 bit depending on the situation. 23%mask {imm} 8 24%mask {imms} 8 25%mask {rel} 32 26%mask {abs} 32 27%mask {absval} 32 28%mask {sel} 16 29%mask {imm32} 32 30%mask {ccc} 3 31%mask {ddd} 3 32%mask {sreg3} 3 33%mask {sreg2} 2 34%mask {mmxreg} 3 35%mask {mmxreg2} 3 36%mask {R_M} 3 37%mask {0g} 2 38%mask {GG} 2 39%mask {gG} 2 40%mask {Mod} 2 41%mask {xmmreg} 3 42%mask {R_m} 3 43%mask {mmreg} 3 44%mask {xmmreg1} 3 45%mask {xmmreg2} 3 46%mask {predpd} 8 47%mask {predps} 8 48%mask {predsd} 8 49%mask {predss} 8 50%mask {freg} 3 51%mask {fmod} 2 52%mask {fr_m} 3 53%prefix {R} 54%prefix {RE} 55%suffix {W} 56%suffix {w0} 57%synonym {xmmreg1} {xmmreg} 58%synonym {xmmreg2} {xmmreg} 59 60%% 61ifdef(`i386', 62`00110111:aaa 6311010101,00001010:aad 6411010100,00001010:aam 6500111111:aas 66')dnl 670001010{w},{imm}:adc {imm}{w},{ax}{w} 681000000{w},{mod}010{r_m},{imm}:adc{w} {imm}{w},{mod}{r_m}{w} 691000001{w},{mod}010{r_m},{imms8}:adc{w} {imms8},{mod}{r_m} 700001000{w},{mod}{reg}{r_m}:adc {reg}{w},{mod}{r_m} 710001001{w},{mod}{reg}{r_m}:adc {mod}{r_m},{reg}{w} 720000010{w},{imm}:add {imm}{w},{ax}{w} 731000000{w},{mod}000{r_m},{imm}:add{w} {imm}{w},{mod}{r_m}{w} 7410000011,{mod}000{r_m},{imms8}:add{w0} {imms8},{mod}{r_m} 750000000{w},{mod}{reg}{r_m}:add {reg}{w},{mod}{r_m} 760000001{w},{mod}{reg}{r_m}:add {mod}{r_m},{reg}{w} 7711110010,00001111,01011000,{Mod}{xmmreg}{R_m}:addsd {Mod}{R_m},{xmmreg} 7811110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg} 7901100110,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubpd {Mod}{R_m},{xmmreg} 8011110010,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubps {Mod}{R_m},{xmmreg} 810010010{w},{imm}:and {imm}{w},{ax}{w} 821000000{w},{mod}100{r_m},{imm}:and{w} {imm}{w},{mod}{r_m}{w} 831000001{w},{mod}100{r_m},{imms}:and{w} {imms},{mod}{r_m} 840010000{w},{mod}{reg}{r_m}:and {reg}{w},{mod}{r_m}{w} 850010001{w},{mod}{reg}{r_m}:and {mod}{r_m}{w},{reg}{w} 8601100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg} 8700001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 8801100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg} 8900001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 90ifdef(`i386', 91`01100011,{mod}{reg16}{r_m}:arpl {reg16},{mod}{r_m} 9201100010,{moda}{reg}{r_m}:bound {reg},{moda}{r_m} 93')dnl 9400001111,10111100,{mod}{reg}{r_m}:bsf {reg},{mod}{r_m} 9500001111,10111101,{mod}{reg}{r_m}:bsr {reg},{mod}{r_m} 9600001111,11001{reg}:bswap {reg} 9700001111,10100011,{mod}{reg}{r_m}:bt {reg},{mod}{r_m} 9800001111,10111010,{mod}100{r_m},{imm8}:bt {imm8},{mod}{r_m} 9900001111,10111011,{mod}{reg}{r_m}:btc {reg},{mod}{r_m} 10000001111,10111010,{mod}111{r_m},{imm8}:btc {imm8},{mod}{r_m} 10100001111,10110011,{mod}{reg}{r_m}:btr {reg},{mod}{r_m} 10200001111,10111010,{mod}110{r_m},{imm8}:btr {imm8},{mod}{r_m} 10300001111,10101011,{mod}{reg}{r_m}:bts {reg},{mod}{r_m} 10400001111,10111010,{mod}101{r_m},{imm8}:bts {imm8},{mod}{r_m} 10511101000,{rel}:call {rel} 10611111111,{mod}010{r_m}:call *{mod}{r_m} 107ifdef(`i386', 108`10011010,{absval},{sel}:lcall {sel},{absval} 109')dnl 11011111111,{mod}011{r_m}:lcall *{mod}{r_m} 111# SPECIAL 10011000:[{rex.w}?cltq:{dpfx}?cbtw:cwtl] 11210011000:INVALID 113# SPECIAL 10011001:[{rew.w}?cqto:{dpfx}?cltd:cwtd] 11410011001:INVALID 11511111000:clc 11611111100:cld 11700001111,10101110,{mod}111{r_m}:clflush {mod}{r_m} 11811111010:cli 11900001111,00000101:syscall 12000001111,00000110:clts 12100001111,00000111:sysret 12200001111,00110100:sysenter 12300001111,00110101:sysexit 12411110101:cmc 12500001111,0100{tttn},{mod}{reg}{r_m}:cmov{tttn} {mod}{r_m},{reg} 1260011110{w},{imm}:cmp {imm}{w},{ax}{w} 1271000000{w},{mod}111{r_m},{imm}:cmp{w} {imm}{w},{mod}{r_m}{w} 12810000011,{mod}111{r_m},{imms8}:cmp{w0} {imms8},{mod}{r_m} 1290011100{w},{mod}{reg}{r_m}:cmp {reg}{w},{mod}{r_m}{w} 1300011101{w},{mod}{reg}{r_m}:cmp {mod}{r_m}{w},{reg}{w} 13101100110,00001111,11000010,{Mod}{xmmreg}{R_m},{predpd}:cmpl{predpd} {Mod}{R_m},{xmmreg} 132ifdef(`ASSEMBLER', 133`01100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg 134}')dnl 13500001111,11000010,{Mod}{xmmreg}{R_m},{predps}:cmpl{predps} {Mod}{R_m},{xmmreg} 136ifdef(`ASSEMBLER', 137`00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg} 138')dnl 1391010011{w}:{RE}cmps{w} {es_di},{ds_si} 14011110010,00001111,11000010,{Mod}{xmmreg}{R_m},{predsd}:cmpl{predsd} {Mod}{R_m},{xmmreg} 141ifdef(`ASSEMBLER', 142`11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg} 143')dnl 14411110011,00001111,11000010,{Mod}{xmmreg}{R_m},{predss}:cmpl{predss} {Mod}{R_m},{xmmreg} 145ifdef(`ASSEMBLER', 146`11110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg} 147')dnl 14800001111,1011000{w},{mod}{reg}{r_m}:cmpxchg{w} {reg},{mod}{r_m} 149# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m} 15000001111,10100010:cpuid 15111110011,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtdq2pd {Mod}{R_m},{xmmreg} 15200001111,01011011,{Mod}{xmmreg}{R_m}:cvtdq2ps {Mod}{R_m},{xmmreg} 15311110010,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtpd2dq {Mod}{R_m},{xmmreg} 15401100110,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtpd2ps {Mod}{R_m},{xmmreg} 15501100110,00001111,01011011,{Mod}{xmmreg}{R_m}:cvtps2dq {Mod}{R_m},{xmmreg} 15600001111,01011010,{Mod}{xmmreg}{R_m}:cvtps2pd {Mod}{R_m},{xmmreg} 15711110010,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtsd2ss {Mod}{R_m},{xmmreg} 15811110011,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtss2sd {Mod}{R_m},{xmmreg} 15901100110,00001111,11100110,{Mod}{xmmreg}{R_m}:cvttpd2dq {Mod}{R_m},{xmmreg} 16011110011,00001111,01011011,{Mod}{mmxreg}{R_m}:cvttps2dq {Mod}{R_m},{mmxreg} 161ifdef(`i386', 162`00100111:daa 16300101111:das 164')dnl 1651111111{w},{mod}001{r_m}:dec{w} {mod}{r_m}{w} 166ifdef(`i386', 167`01001{reg}:dec {reg} 168')dnl 1691111011{w},{mod}110{r_m}:div{w} {mod}{r_m}{w} 17001100110,00001111,01011110,{Mod}{xmmreg}{R_m}:divpd {Mod}{R_m},{xmmreg} 17100001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg} 17211110010,00001111,01011110,{Mod}{xmmreg}{R_m}:divsd {Mod}{R_m},{xmmreg} 17311110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg} 17400001111,01110111:emms 17511001000,{imm16},{imm8}:enter {imm16},{imm8} 17611011001,11010000:fnop 17711011001,11100000:fchs 17811011001,11100001:fabs 17911011001,11100100:ftst 18011011001,11100101:fxam 18111011001,11101000:fld1 18211011001,11101001:fldl2t 18311011001,11101010:fldl2e 18411011001,11101011:fldpi 18511011001,11101100:fldlg2 18611011001,11101101:fldln2 18711011001,11101110:fldz 18811011001,11110000:f2xm1 18911011001,11110001:fyl2x 19011011001,11110010:fptan 19111011001,11110011:fpatan 19211011001,11110100:fxtract 19311011001,11110101:fprem1 19411011001,11110110:fdecstp 19511011001,11110111:fincstp 19611011001,11111000:fprem 19711011001,11111001:fyl2xp1 19811011001,11111010:fsqrt 19911011001,11111011:fsincos 20011011001,11111100:frndint 20111011001,11111101:fscale 20211011001,11111110:fsin 20311011001,11111111:fcos 204# ORDER 20511011000,11000{freg}:fadd {freg},%st 20611011100,11000{freg}:fadd %st,{freg} 20711011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m} 208# ORDER END 209# ORDER 21011011000,11001{freg}:fmul {freg},%st 21111011100,11001{freg}:fmul %st,{freg} 21211011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m} 213# ORDER END 214# ORDER 21511011000,11100{freg}:fsub {freg},%st 21611011100,11100{freg}:fsub %st,{freg} 21711011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m} 218# ORDER END 219# ORDER 22011011000,11101{freg}:fsubr {freg},%st 22111011100,11101{freg}:fsubr %st,{freg} 22211011{D}00,{mod}101{r_m}:fsubr{D} {mod}{r_m} 223# ORDER END 224# ORDER 22511011101,11010{freg}:fst {freg} 22611011{D}01,{mod}010{r_m}:fst{D} {mod}{r_m} 227# ORDER END 228# ORDER 22911011101,11011{freg}:fstp {freg} 23011011{D}01,{mod}011{r_m}:fstp{D} {mod}{r_m} 231# ORDER END 23211011001,{mod}100{r_m}:fldenv {mod}{r_m} 23311011001,{mod}101{r_m}:fldcw {mod}{r_m} 23411011001,{mod}110{r_m}:fnstenv {mod}{r_m} 23511011001,{mod}111{r_m}:fnstcw {mod}{r_m} 23611011001,11001{freg}:fxch {freg} 237# ORDER 23811011110,11000{freg}:faddp %st,{freg} 239ifdef(`ASSEMBLER', 240`11011110,11000001:faddp 241')dnl 242# ORDER 24311011010,11000{freg}:fcmovb {freg},%st 24411011{w1}10,{mod}000{r_m}:fiadd{w1} {mod}{r_m} 245# ORDER END 246# ORDER 24711011010,11001{freg}:fcmove {freg},%st 24811011110,11001{freg}:fmulp %st,{freg} 24911011{w1}10,{mod}001{r_m}:fimul{w1} {mod}{r_m} 250# ORDER END 251# ORDER 25211011110,11100{freg}:fsubp %st,{freg} 25311011{w1}10,{mod}100{r_m}:fisub{w1} {mod}{r_m} 254# ORDER END 255# ORDER 25611011110,11101{freg}:fsubrp %st,{freg} 25711011{w1}10,{mod}101{r_m}:fisubr{w1} {mod}{r_m} 258# ORDER END 259# ORDER 26011011111,11100000:fnstsw %ax 26111011111,{mod}100{r_m}:fbld {mod}{r_m} 262# ORDER END 263# ORDER 26411011111,11110{freg}:fcomip {freg},%st 26511011111,{mod}110{r_m}:fbstp {mod}{r_m} 266# ORDER END 26711011001,11100000:fchs 268# ORDER 26910011011,11011011,11100010:fclex 27010011011,11011011,11100011:finit 27110011011:fwait 272# END ORDER 27311011011,11100010:fnclex 27411011010,11000{freg}:fcmovb {freg},%st 27511011010,11001{freg}:fcmove {freg},%st 27611011010,11010{freg}:fcmovbe {freg},%st 27711011010,11011{freg}:fcmovu {freg},%st 27811011011,11000{freg}:fcmovnb {freg},%st 27911011011,11001{freg}:fcmovne {freg},%st 28011011011,11010{freg}:fcmovnbe {freg},%st 28111011011,11011{freg}:fcmovnu {freg},%st 282# ORDER 28311011000,11010{freg}:fcom {freg} 284ifdef(`ASSEMBLER', 285`11011000,11010001:fcom 286')dnl 28711011{D}00,{mod}010{r_m}:fcom{D} {mod}{r_m} 288# END ORDER 289# ORDER 29011011000,11011{freg}:fcomp {freg} 291ifdef(`ASSEMBLER', 292`11011000,11011001:fcomp 293')dnl 29411011{D}00,{mod}011{r_m}:fcomp{D} {mod}{r_m} 295# END ORDER 29611011110,11011001:fcompp 29711011011,11110{freg}:fcomi {freg},%st 29811011111,11110{freg}:fcomip {freg},%st 29911011011,11101{freg}:fucomi {freg},%st 30011011111,11101{freg}:fucomip {freg},%st 30111011001,11111111:fcos 30211011001,11110110:fdecstp 303# ORDER 30411011000,11110{freg}:fdiv {freg},%st 30511011100,11110{freg}:fdiv %st,{freg} 30611011{D}00,{mod}110{r_m}:fdiv{D} {mod}{r_m} 307# END ORDER 30811011010,{mod}110{r_m}:fidivl {mod}{r_m} 309# ORDER 31011011110,11110{freg}:fdivp %st,{freg} 31111011110,{mod}110{r_m}:fidiv {mod}{r_m} 312# END ORDER 31311011110,11111{freg}:fdivrp %st,{freg} 314ifdef(`ASSEMBLER', 315`11011110,11111001:fdivp 316')dnl 317# ORDER 31811011000,11111{freg}:fdivr {freg},%st 31911011100,11111{freg}:fdivr %st,{freg} 32011011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m} 321# END ORDER 32211011010,{mod}111{r_m}:fidivrl {mod}{r_m} 32311011110,{mod}111{r_m}:fidivr {mod}{r_m} 32411011110,11110{freg}:fdivrp %st,{freg} 325ifdef(`ASSEMBLER', 326`11011110,11110001:fdivrp 327')dnl 32811011101,11000{freg}:ffree {freg} 32911011010,11010{freg}:fcmovbe {freg} 33011011{w1}10,{mod}010{r_m}:ficom{w1} {mod}{r_m} 33111011010,11011{freg}:fcmovu {freg} 33211011{w1}10,{mod}011{r_m}:ficomp{w1} {mod}{r_m} 33311011111,{mod}000{r_m}:fild {mod}{r_m} 33411011011,{mod}000{r_m}:fildl {mod}{r_m} 33511011111,{mod}101{r_m}:fildll {mod}{r_m} 33611011001,11110111:fincstp 33711011011,11100011:fninit 33811011{w1}11,{mod}010{r_m}:fist{w1} {mod}{r_m} 33911011{w1}11,{mod}011{r_m}:fistp{w1} {mod}{r_m} 34011011111,{mod}111{r_m}:fistpll {mod}{r_m} 34111011{w1}11,{mod}001{r_m}:fisttp{w1} {mod}{r_m} 34211011101,{mod}001{r_m}:fisttpll {mod}{r_m} 34311011011,{mod}101{r_m}:fldt {mod}{r_m} 34411011011,{mod}111{r_m}:fstpt {mod}{r_m} 345# ORDER 34611011001,11000{freg}:fld {freg} 34711011{D}01,{mod}000{r_m}:fld{D} {mod}{r_m} 348# ORDER END 349# ORDER 35011011101,11100{freg}:fucom {freg} 35111011101,{mod}100{r_m}:frstor {mod}{r_m} 352# ORDER END 35311011101,11101{freg}:fucomp {freg} 35411011101,{mod}110{r_m}:fnsave {mod}{r_m} 35511011101,{mod}111{r_m}:fnstsw {mod}{r_m} 356# 357# 358# 35911110100:hlt 3601111011{w},{mod}111{r_m}:idiv{w} {mod}{r_m}{w} 3611111011{w},{mod}101{r_m}:imul{w} {mod}{r_m}{w} 36200001111,10101111,{mod}{reg}{r_m}:imul {reg},{mod}{r_m} 363011010{s}1,{mod}{reg}{r_m},{imm}:imul {imm}{s},{mod}{r_m},{reg} 3641110010{w},{imm8}:in {imm8},{ax}{w} 3651110110{w}:in {dx},{ax}{w} 3661111111{w},{mod}000{r_m}:inc{w} {mod}{r_m}{w} 36701000{reg}:inc {reg} 3680110110{w}:{R}ins{w} {dx},{es_di} 36911001101,{imm8}:int {imm8} 37011001100:int3 37111001110:into 37200001111,00001000:invd 373# ORDER 37400001111,00000001,11111000:swapgs 37500001111,00000001,{mod}111{r_m}:invlpg {mod}{r_m} 376# ORDER END 37711001111:iret{W} 3780111{tttn},{disp8}:j{tttn} {disp8} 37900001111,1000{tttn},{rel}:j{tttn} {rel} 38000001111,1001{tttn},{mod}000{8r_m}:set{tttn} {mod}{8r_m} 381# SPECIAL 11100011,{disp8}:[{dpfx}?jcxz:jecxz] {disp8} 38211100011,{disp8}:INVALID {disp8} 38311101011,{disp8}:jmp {disp8} 38411101001,{rel}:jmp {rel} 38511111111,{mod}100{r_m}:jmp *{mod}{r_m} 38611101010,{absval},{sel}:ljmp {sel},{absval} 38711111111,{mod}101{r_m}:ljmp *{mod}{r_m} 38810011111:lahf 38900001111,00000010,{mod}{reg}{16r_m}:lar {mod}{16r_m},{reg} 39011000101,{mod}{reg}{r_m}:lds {mod}{r_m},{reg} 39110001101,{mod}{reg}{r_m}:lea {mod}{r_m},{reg} 39211001001:leave 39311000100,{mod}{reg}{r_m}:les {mod}{r_m},{reg} 39400001111,10110100,{mod}{reg}{r_m}:lfs {mod}{r_m},{reg} 39500001111,00000001,{mod}010{r_m}:lgdt{w0} {mod}{r_m} 39600001111,10110101,{mod}{reg}{r_m}:lgs {mod}{r_m},{reg} 39700001111,00000001,{mod}011{r_m}:lidt{w0} {mod}{r_m} 39800001111,00000000,{mod}010{16r_m}:lldt {mod}{16r_m} 39900001111,00000001,{mod}110{16r_m}:lmsw {mod}{16r_m} 40011110000:lock 4011010110{w}:{R}lods {ds_si},{ax}{w} 40211100010,{disp8}:loop {disp8} 40311100001,{disp8}:loope {disp8} 40411100000,{disp8}:loopne {disp8} 40500001111,00000011,{mod}{reg}{16r_m}:lsl {mod}{16r_m},{reg} 40600001111,10110010,{mod}{reg}{r_m}:lss {mod}{r_m},{reg} 40700001111,00000000,{mod}011{16r_m}:ltr {mod}{16r_m} 4081000100{w},{mod}{reg}{r_m}:mov {reg}{w},{mod}{r_m}{w} 4091000101{w},{mod}{reg}{r_m}:mov {mod}{r_m}{w},{reg}{w} 4101100011{w},{mod}000{r_m},{imm}:mov{w} {imm}{w},{mod}{r_m}{w} 4111011{w}{reg},{imm}:mov {imm}{w},{reg}{w} 4121010000{w},{abs}:mov {abs},{ax}{w} 4131010001{w},{abs}:mov {ax}{w},{abs} 41400001111,00100000,11{ccc}{reg}:mov {ccc},{reg} 41500001111,00100010,11{ccc}{reg}:mov {reg},{ccc} 41600001111,00100001,11{ddd}{reg}:mov {ddd},{reg} 41700001111,00100011,11{ddd}{reg}:mov {reg},{ddd} 41810001100,{mod}{sreg3}{r_m}:mov {sreg3},{mod}{r_m} 41910001110,{mod}{sreg3}{r_m}:mov {mod}{r_m},{sreg3} 4201010010{w}:{R}movs{w} {ds_si},{es_di} 42100001111,1011111{w},{mod}{reg}{r_m}:movsx{w} {mod}{r_m},{reg} 42200001111,1011011{w},{mod}{reg}{r_m}:movzx{w} {mod}{r_m},{reg} 4231111011{w},{mod}100{r_m}:mul{w} {mod}{r_m}{w} 4241111011{w},{mod}011{r_m}:neg{w} {mod}{r_m}{w} 425ifdef(`ASSEMBLER', 426`10010000:nop 42711110011,10010000:pause 428', 429`10010000:{R}INVALID 430')dnl 4311111011{w},{mod}010{r_m}:not{w} {mod}{r_m}{w} 4320000100{w},{mod}{reg}{r_m}:or {reg}{w},{mod}{r_m}{w} 4330000101{w},{mod}{reg}{r_m}:or {mod}{r_m}{w},{reg}{w} 4341000000{w},{mod}001{r_m},{imm}:or{w} {imm}{w},{mod}{r_m}{w} 435100000{s}{w},{mod}001{r_m},{imm}:or{w} {imm}{s},{mod}{r_m}{w} 4360000110{w},{imm}:or {imm}{w},{ax}{w} 4371110011{w},{imm8}:out {ax}{w},{imm8} 4381110111{w}:out {ax}{w},{dx} 4390110111{w}:{R}outs{w} {ds_si},{dx} 44010001111,{mod}000{r_m}:pop{w} {mod}{r_m} 44101011{reg}:pop {reg} 44200001111,10{sreg3}001:pop {sreg3} 44301100001:popa{W} 44410011101:popf{W} 44511111111,{mod}110{r_m}:push{w} {mod}{r_m} 44601010{reg}:push {reg} 447011010{s}0,{imm}:push {imm}{s} 448000{sreg2}110:push {sreg2} 44900001111,10{sreg3}000:push {sreg3} 45001100000:pusha{W} 45110011100:pushf{W} 4521101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w} 4531101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w} 4541100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w} 4551101000{w},{mod}011{r_m}:rcr{w} {mod}{r_m}{w} 4561101001{w},{mod}011{r_m}:rcr{w} %cl,{mod}{r_m}{w} 4571100000{w},{mod}011{r_m},{imm8}:rcr{w} {imm8},{mod}{r_m}{w} 45800001111,00110010:rdmsr 45900001111,00110011:rdpmc 46000001111,00110001:rdtsc 46111000011:ret 46211000010,{imm16}:ret {imm16} 46311001011:lret 46411001010,{imm16}:lret {imm16} 4651101000{w},{mod}000{r_m}:rol{w} {mod}{r_m}{w} 4661101001{w},{mod}000{r_m}:rol{w} %cl,{mod}{r_m}{w} 4671100000{w},{mod}000{r_m},{imm8}:rol{w} {imm8},{mod}{r_m}{w} 4681101000{w},{mod}001{r_m}:ror{w} {mod}{r_m}{w} 4691101001{w},{mod}001{r_m}:ror{w} %cl,{mod}{r_m}{w} 4701100000{w},{mod}001{r_m},{imm8}:ror{w} {imm8},{mod}{r_m}{w} 47100001111,10101010:rsm 47210011110:sahf 4731101000{w},{mod}111{r_m}:sar{w} {mod}{r_m}{w} 4741101001{w},{mod}111{r_m}:sar{w} %cl,{mod}{r_m}{w} 4751100000{w},{mod}111{r_m},{imm8}:sar{w} {imm8},{mod}{r_m}{w} 4760001100{w},{mod}{reg}{r_m}:sbb {reg}{w},{mod}{r_m}{w} 4770001101{w},{mod}{reg}{r_m}:sbb {mod}{r_m}{w},{reg}{w} 4780001110{w},{imm}:sbb {imm}{w},{ax}{w} 4791000000{w},{mod}011{r_m},{imm}:sbb{w} {imm}{w},{mod}{r_m}{w} 4801000001{w},{mod}011{r_m},{imms}:sbb{w} {imms},{mod}{r_m} 4811010111{w}:{RE}scas {es_di},{ax}{w} 48200001111,1001{tttn},{mod}000{r_m}:set{tttn} {mod}{r_m} 4831101000{w},{mod}100{r_m}:shl{w} {mod}{r_m}{w} 4841101001{w},{mod}100{r_m}:shl{w} %cl,{mod}{r_m}{w} 4851100000{w},{mod}100{r_m},{imm8}:shl{w} {imm8},{mod}{r_m}{w} 4861101000{w},{mod}101{r_m}:shr{w} {mod}{r_m}{w} 48700001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m} 48800001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m} 4891101001{w},{mod}101{r_m}:shr{w} %cl,{mod}{r_m}{w} 4901100000{w},{mod}101{r_m},{imm8}:shr{w} {imm8},{mod}{r_m}{w} 49100001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m} 49200001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m} 493# ORDER 49400001111,00000001,11000001:vmcall 49500001111,00000001,11000010:vmlaunch 49600001111,00000001,11000011:vmresume 49700001111,00000001,11000100:vmxoff 49800001111,00000001,{mod}000{r_m}:sgdtl {mod}{r_m} 499# ORDER END 500# ORDER 50100001111,00000001,11001000:monitor %eax,%ecx,%edx 50200001111,00000001,11001001:mwait %eax,%ecx 50300001111,00000001,{mod}001{r_m}:sidtl {mod}{r_m} 504# ORDER END 50500001111,00000000,{mod}000{r_m}:sldt {mod}{r_m} 50600001111,00000001,{mod}100{r_m}:smsw {mod}{r_m} 50711111001:stc 50811111101:std 50911111011:sti 5101010101{w}:{R}stos {ax}{w},{es_di} 51100001111,00000000,{mod}001{r_m}:str {mod}{r_m} 5120010100{w},{mod}{reg}{r_m}:sub {reg}{w},{mod}{r_m}{w} 5130010101{w},{mod}{reg}{r_m}:sub {mod}{r_m}{w},{reg}{w} 5140010110{w},{imm}:sub {imm}{w},{ax}{w} 5151000000{w},{mod}101{r_m},{imm}:sub{w} {imm}{w},{mod}{r_m}{w} 5161000001{w},{mod}101{r_m},{imms}:sub{w} {imms},{mod}{r_m} 5171000010{w},{mod}{reg}{r_m}:test {reg}{w},{mod}{r_m}{w} 5181010100{w},{imm}:test {imm}{w},{ax}{w} 5191111011{w},{mod}000{r_m},{imm}:test{w} {imm}{w},{mod}{r_m}{w} 52000001111,00001011:ud2a 52100001111,00000000,{mod}100{16r_m}:verr {mod}{16r_m} 52200001111,00000000,{mod}101{16r_m}:verw {mod}{16r_m} 52300001111,00001001:wbinvd 52400001111,00001101,{mod}000{8r_m}:prefetch {mod}{8r_m} 52500001111,00001101,{mod}001{8r_m}:prefetchw {mod}{8r_m} 52600001111,00011000,{mod}000{r_m}:prefetchnta {mod}{r_m} 52700001111,00011000,{mod}001{r_m}:prefetcht0 {mod}{r_m} 52800001111,00011000,{mod}010{r_m}:prefetcht1 {mod}{r_m} 52900001111,00011000,{mod}011{r_m}:prefetcht2 {mod}{r_m} 53000001111,00011111,{mod}{reg}{r_m}:nop{w} {mod}{r_m} 53100001111,00110000:wrmsr 53200001111,1100000{w},{mod}{reg}{r_m}:xadd{w} {reg},{mod}{r_m} 5331000011{w},{mod}{reg}{r_m}:xchg {reg}{w},{mod}{r_m}{w} 53410010{reg}:xchg {ax},{reg} 53511010111:xlat {ds_bx} 5360011000{w},{mod}{reg}{r_m}:xor {reg}{w},{mod}{r_m}{w} 5370011001{w},{mod}{reg}{r_m}:xor {mod}{r_m}{w},{reg}{w} 5380011010{w},{imm}:xor {imm}{w},{ax}{w} 5391000000{w},{mod}110{r_m},{imm}:xor{w} {imm}{w},{mod}{r_m}{w} 5401000001{w},{mod}110{r_m},{imms}:xor{w} {imms},{mod}{r_m} 54100001111,01110111:emms 54200001111,01101110,{mod}{mmxreg}{r_m}:movd {mod}{r_m},{mmxreg} 54300001111,01111110,{mod}{mmxreg}{r_m}:movd {mmxreg},{mod}{r_m} 54400001111,01101111,{MOD}{mmxreg}{R_M}:movq {MOD}{R_M},{mmxreg} 54500001111,01111111,{MOD}{mmxreg}{R_M}:movq {mmxreg},{MOD}{R_M} 54600001111,01101011,{MOD}{mmxreg}{R_M}:packssdw {MOD}{R_M},{mmxreg} 54700001111,01100011,{MOD}{mmxreg}{R_M}:packsswb {MOD}{R_M},{mmxreg} 54800001111,01100111,{MOD}{mmxreg}{R_M}:packuswb {MOD}{R_M},{mmxreg} 54900001111,111111{gg},{MOD}{mmxreg}{R_M}:padd{gg} {MOD}{R_M},{mmxreg} 55000001111,111111{0g},{MOD}{mmxreg}{R_M}:padds{0g} {MOD}{R_M},{mmxreg} 55100001111,110111{0g},{MOD}{mmxreg}{R_M}:paddus{0g} {MOD}{R_M},{mmxreg} 55200001111,11011011,{MOD}{mmxreg}{R_M}:pand {MOD}{R_M},{mmxreg} 55300001111,11011111,{MOD}{mmxreg}{R_M}:pandn {MOD}{R_M},{mmxreg} 55400001111,011101{gg},{MOD}{mmxreg}{R_M}:pcmpeq{gg} {MOD}{R_M},{mmxreg} 55500001111,011001{gg},{MOD}{mmxreg}{R_M}:pcmpgt{gg} {MOD}{R_M},{mmxreg} 55600001111,11110101,{MOD}{mmxreg}{R_M}:pmaddwd {MOD}{R_M},{mmxreg} 55700001111,11100101,{MOD}{mmxreg}{R_M}:pmulhw {MOD}{R_M},{mmxreg} 55800001111,11010101,{MOD}{mmxreg}{R_M}:pmullw {MOD}{R_M},{mmxreg} 55900001111,11101011,{MOD}{mmxreg}{R_M}:por {MOD}{R_M},{mmxreg} 56000001111,111100{GG},{MOD}{mmxreg}{R_M}:psll{GG} {MOD}{R_M},{mmxreg} 56100001111,011100{GG},11110{mmxreg},{imm8}:psll{GG} {imm8},{mmxreg} 56200001111,111000{gG},{MOD}{mmxreg}{R_M}:psra{gG} {MOD}{R_M},{mmxreg} 56300001111,011100{gG},11100{mmxreg},{imm8}:psra{gG} {imm8},{mmxreg} 56400001111,110100{GG},{MOD}{mmxreg}{R_M}:psrl{GG} {MOD}{R_M},{mmxreg} 56500001111,011100{GG},11010{mmxreg},{imm8}:psrl{GG} {imm8},{mmxreg} 56600001111,111110{gg},{MOD}{mmxreg}{R_M}:psub{gg} {MOD}{R_M},{mmxreg} 56700001111,111010{0g},{MOD}{mmxreg}{R_M}:psubs{0g} {MOD}{R_M},{mmxreg} 56800001111,110110{0g},{MOD}{mmxreg}{R_M}:psubus{0g} {MOD}{R_M},{mmxreg} 56900001111,011010{gg},{MOD}{mmxreg}{R_M}:punpckh{gg} {MOD}{R_M},{mmxreg} 57000001111,011000{gg},{MOD}{mmxreg}{R_M}:punpckl{gg} {MOD}{R_M},{mmxreg} 57100001111,11101111,{MOD}{mmxreg}{R_M}:pxor {MOD}{R_M},{mmxreg} 57200001111,01011000,{Mod}{xmmreg}{R_m}:addps {Mod}{R_m},{xmmreg} 57311110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg} 57400001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 57500001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 57600001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqps {Mod}{R_m},{xmmreg} 57700001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltps {Mod}{R_m},{xmmreg} 57800001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpleps {Mod}{R_m},{xmmreg} 57900001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordps {Mod}{R_m},{xmmreg} 58000001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqps {Mod}{R_m},{xmmreg} 58100001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltps {Mod}{R_m},{xmmreg} 58200001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnleps {Mod}{R_m},{xmmreg} 58300001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordps {Mod}{R_m},{xmmreg} 58411110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqss {Mod}{R_m},{xmmreg} 58511110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltss {Mod}{R_m},{xmmreg} 58611110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpless {Mod}{R_m},{xmmreg} 58711110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordss {Mod}{R_m},{xmmreg} 58811110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqss {Mod}{R_m},{xmmreg} 58911110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltss {Mod}{R_m},{xmmreg} 59011110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnless {Mod}{R_m},{xmmreg} 59111110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordss {Mod}{R_m},{xmmreg} 59200001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg} 59311110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg} 59400001111,10101110,{mod}001{r_m}:fxrstor {mod}{r_m} 59500001111,10101110,{mod}000{r_m}:fxsave {mod}{r_m} 59600001111,10101110,{mod}010{r_m}:ldmxcsr {mod}{r_m} 59700001111,01011111,{Mod}{xmmreg}{R_m}:maxps {Mod}{R_m},{xmmreg} 59811110011,00001111,01011111,{Mod}{xmmreg}{R_m}:maxss {Mod}{R_m},{xmmreg} 59900001111,01011101,{Mod}{xmmreg}{R_m}:minps {Mod}{R_m},{xmmreg} 60011110011,00001111,01011101,{Mod}{xmmreg}{R_m}:minss {Mod}{R_m},{xmmreg} 60111110010,00001111,00010000,{Mod}{xmmreg}{R_m}:movsd {Mod}{R_m},{xmmreg} 60211110011,00001111,00010000,{Mod}{xmmreg}{R_m}:movss {Mod}{R_m},{xmmreg} 60301100110,00001111,00010000,{Mod}{xmmreg}{R_m}:movupd {Mod}{R_m},{xmmreg} 60400001111,00010000,{Mod}{xmmreg}{R_m}:movups {Mod}{R_m},{xmmreg} 60511110010,00001111,00010001,{Mod}{xmmreg}{R_m}:movsd {xmmreg},{Mod}{R_m} 60611110011,00001111,00010001,{Mod}{xmmreg}{R_m}:movss {xmmreg},{Mod}{R_m} 60701100110,00001111,00010001,{Mod}{xmmreg}{R_m}:movupd {xmmreg},{Mod}{R_m} 60800001111,00010001,{Mod}{xmmreg}{R_m}:movups {xmmreg},{Mod}{R_m} 60911110010,00001111,00010010,{Mod}{xmmreg}{R_m}:movddup {Mod}{R_m},{xmmreg} 61011110011,00001111,00010010,{Mod}{xmmreg}{R_m}:movsldup {Mod}{R_m},{xmmreg} 61101100110,00001111,00010010,{Mod}{xmmreg}{R_m}:movlpd {Mod}{R_m},{xmmreg} 61200001111,00010010,11{xmmreg1}{xmmreg2}:movhlps {xmmreg2},{xmmreg1} 61300001111,00010010,{Mod}{xmmreg}{R_m}:movlps {Mod}{R_m},{xmmreg} 61401100110,00001111,00010011,11{xmmreg1}{xmmreg2}:movhlpd {xmmreg1},{xmmreg2} 61500001111,00010011,11{xmmreg1}{xmmreg2}:movhlps {xmmreg1},{xmmreg2} 61601100110,00001111,00010011,{Mod}{xmmreg}{R_m}:movlpd {xmmreg},{Mod}{R_m} 61700001111,00010011,{Mod}{xmmreg}{R_m}:movlps {xmmreg},{Mod}{R_m} 61801100110,00001111,00010100,{Mod}{xmmreg}{R_m}:unpcklpd {Mod}{R_m},{xmmreg} 61900001111,00010100,{Mod}{xmmreg}{R_m}:unpcklps {Mod}{R_m},{xmmreg} 62001100110,00001111,00010101,{Mod}{xmmreg}{R_m}:unpckhpd {Mod}{R_m},{xmmreg} 62100001111,00010101,{Mod}{xmmreg}{R_m}:unpckhps {Mod}{R_m},{xmmreg} 62211110011,00001111,00010110,{Mod}{xmmreg}{R_m}:movshdup {Mod}{R_m},{xmmreg} 62301100110,00001111,00010110,{Mod}{xmmreg}{R_m}:movhpd {Mod}{R_m},{xmmreg} 62400001111,00010110,11{xmmreg1}{xmmreg2}:movlhps {xmmreg2},{xmmreg1} 62500001111,00010110,{Mod}{xmmreg}{R_m}:movhps {Mod}{R_m},{xmmreg} 62601100110,00001111,00010111,11{xmmreg1}{xmmreg2}:movlhpd {xmmreg1},{xmmreg2} 62700001111,00010111,11{xmmreg1}{xmmreg2}:movlhps {xmmreg1},{xmmreg2} 62801100110,00001111,00010111,{Mod}{xmmreg}{R_m}:movhpd {xmmreg},{Mod}{R_m} 62900001111,00010111,{Mod}{xmmreg}{R_m}:movhps {xmmreg},{Mod}{R_m} 63001100110,00001111,00101000,{Mod}{xmmreg}{R_m}:movapd {Mod}{R_m},{xmmreg} 63100001111,00101000,{Mod}{xmmreg}{R_m}:movaps {Mod}{R_m},{xmmreg} 63201100110,00001111,00101001,{Mod}{xmmreg}{R_m}:movapd {xmmreg},{Mod}{R_m} 63300001111,00101001,{Mod}{xmmreg}{R_m}:movaps {xmmreg},{Mod}{R_m} 63411110010,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2sd {mod}{r_m},{xmmreg} 63511110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg} 63601100110,00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2pd {MOD}{R_M},{xmmreg} 63700001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2ps {MOD}{R_M},{xmmreg} 63801100110,00001111,00101011,{mod}{xmmreg}{r_m}:movntpd {xmmreg},{mod}{r_m} 63900001111,00101011,{mod}{xmmreg}{r_m}:movntps {xmmreg},{mod}{r_m} 64011110010,00001111,00101100,{Mod}{reg}{R_m}:cvttsd2si {Mod}{R_m},{reg} 64111110011,00001111,00101100,{Mod}{reg}{R_m}:cvttss2si {Mod}{R_m},{reg} 64201100110,00001111,00101100,{Mod}{mmxreg}{R_m}:cvttpd2pi {Mod}{R_m},{mmxreg} 64300001111,00101100,{Mod}{mmxreg}{R_m}:cvttps2pi {Mod}{R_m},{mmxreg} 64401100110,00001111,00101101,{Mod}{mmxreg}{R_m}:cvtpd2pi {Mod}{R_m},{mmxreg} 64511110010,00001111,00101101,{Mod}{reg}{R_m}:cvtsd2si {Mod}{R_m},{reg} 64611110011,00001111,00101101,{Mod}{reg}{R_m}:cvtss2si {Mod}{R_m},{reg} 64700001111,00101101,{Mod}{mmxreg}{R_m}:cvtps2pi {Mod}{R_m},{mmxreg} 64801100110,00001111,00101110,{Mod}{xmmreg}{R_m}:ucomisd {Mod}{R_m},{xmmreg} 64900001111,00101110,{Mod}{xmmreg}{R_m}:ucomiss {Mod}{R_m},{xmmreg} 65001100110,00001111,00101111,{Mod}{xmmreg}{R_m}:comisd {Mod}{R_m},{xmmreg} 65100001111,00101111,{Mod}{xmmreg}{R_m}:comiss {Mod}{R_m},{xmmreg} 65200001111,00110111:getsec 65301100110,00001111,01010000,11{reg}{xmmreg}:movmskpd {xmmreg},{reg} 65400001111,01010000,11{reg}{xmmreg}:movmskps {xmmreg},{reg} 65501100110,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtpd {Mod}{R_m},{xmmreg} 65611110010,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtsd {Mod}{R_m},{xmmreg} 65711110011,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtss {Mod}{R_m},{xmmreg} 65800001111,01010001,{Mod}{xmmreg}{R_m}:sqrtps {Mod}{R_m},{xmmreg} 65911110011,00001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtss {Mod}{R_m},{xmmreg} 66000001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtps {Mod}{R_m},{xmmreg} 66111110011,00001111,01010011,{Mod}{xmmreg}{R_m}:rcpss {Mod}{R_m},{xmmreg} 66200001111,01010011,{Mod}{xmmreg}{R_m}:rcpps {Mod}{R_m},{xmmreg} 663# ORDER: 664dnl Many previous entries depend on this being last. 665000{sreg2}111:pop {sreg2} 666# ORDER END: 667