16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 93d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 103d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// This file describes an abstract interface used to get information about a 113d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// target machines register file. This information is used for a variety of 123d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// purposed, especially register allocation. 133d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 143d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===----------------------------------------------------------------------===// 153d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#define LLVM_TARGET_TARGETREGISTERINFO_H 183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 1979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen#include "llvm/ADT/ArrayRef.h" 20255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/CodeGen/MachineBasicBlock.h" 2137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#include "llvm/CodeGen/MachineValueType.h" 220b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/CallingConv.h" 23255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/MC/MCRegisterInfo.h" 24cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/Support/CommandLine.h" 25cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/Support/Printable.h" 264d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <cassert> 274d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <functional> 283d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 29d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 30d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 31171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass BitVector; 32198ab640bbb0b8e1cdda518b7f8b348764e4402cChris Lattnerclass MachineFunction; 33171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass RegScavenger; 34b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengtemplate<class T> class SmallVectorImpl; 357eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesenclass VirtRegMap; 36414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesenclass raw_ostream; 37cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarclass LiveRegMatrix; 38cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 39cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// A bitmask representing the covering of a register with sub-registers. 40cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// 41cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// This is typically used to track liveness at sub-register granularity. 42cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// Lane masks for sub-register indices are similar to register units for 43cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// physical registers. The individual bits in a lane mask can't be assigned 44cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// any specific meaning. They can be used to check if two sub-register 45cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// indices overlap. 46cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// 47cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// Iff the target has a register such that: 48cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// 49cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// getSubReg(Reg, A) overlaps getSubReg(Reg, B) 50cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// 51cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// then: 52cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// 53cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0 54cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainartypedef unsigned LaneBitmask; 55282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 56f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramerclass TargetRegisterClass { 57282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanpublic: 58e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* iterator; 59e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* const_iterator; 602c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer typedef const MVT::SimpleValueType* vt_iterator; 613b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng typedef const TargetRegisterClass* const * sc_iterator; 62ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer 63ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer // Instance variables filled by tablegen, do not use! 64f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const MCRegisterClass *MC; 6516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner const vt_iterator VTs; 661d61f283fad2e49d3e50a3585aac4cc9183a0d28Jakob Stoklund Olesen const uint32_t *SubClassMask; 671a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *SuperRegIndices; 68cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const LaneBitmask LaneMask; 690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar /// Classes with a higher priority value are assigned first by register 700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar /// allocators using a greedy heuristic. The value is in the range [0,63]. 710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const uint8_t AllocationPriority; 724c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar /// Whether the class supports two (or more) disjunct subregister indices. 734c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const bool HasDisjunctSubRegs; 74c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng const sc_iterator SuperClasses; 75e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); 76320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen 77cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the register class ID number. 78f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getID() const { return MC->getID(); } 79f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 80f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// begin/end - Return all of the registers in this class. 81f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 82f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator begin() const { return MC->begin(); } 83f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator end() const { return MC->end(); } 84f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 85cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the number of registers in this class. 86f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getNumRegs() const { return MC->getNumRegs(); } 87f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 88cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the specified register in the class. 89f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getRegister(unsigned i) const { 90f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->getRegister(i); 91f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 92f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 93cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if the specified register is included in this register class. 94cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// This does not include virtual registers. 95f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg) const { 96f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg); 97f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 98f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 99cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if both registers are in this class. 100f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg1, unsigned Reg2) const { 101f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg1, Reg2); 102f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 103f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 104cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the size of the register in bytes, which is also the size 105f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// of a stack slot allocated to hold a spilled copy of this register. 106f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getSize() const { return MC->getSize(); } 107f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 108cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the minimum required alignment for a register of this class. 109f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getAlignment() const { return MC->getAlignment(); } 110f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 111cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the cost of copying a value between two registers in this class. 112cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// A negative number means the register class is very expensive 113f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// to copy e.g. status flag register classes. 114f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer int getCopyCost() const { return MC->getCopyCost(); } 115f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 116cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if this register class may be used to create virtual 117cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// registers. 118f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool isAllocatable() const { return MC->isAllocatable(); } 119f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 120cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if this TargetRegisterClass has the ValueType vt. 12137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines bool hasType(MVT vt) const { 122cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands for(int i = 0; VTs[i] != MVT::Other; ++i) 12337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (MVT(VTs[i]) == vt) 1246510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return true; 1256510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return false; 1266510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman } 12795923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 128696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// vt_begin / vt_end - Loop over all of the value types that can be 129696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// represented by values in this register class. 13016d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_begin() const { 13116d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return VTs; 13216d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 13316d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner 13416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_end() const { 13516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator I = VTs; 136cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands while (*I != MVT::Other) ++I; 13716d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return I; 13816d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 139696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 140cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if the specified TargetRegisterClass 141c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// is a proper sub-class of this TargetRegisterClass. 142c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSubClass(const TargetRegisterClass *RC) const { 143c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC != this && hasSubClassEq(RC); 144696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 145696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 146cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if RC is a sub-class of or equal to this class. 1471f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSubClassEq(const TargetRegisterClass *RC) const { 148c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen unsigned ID = RC->getID(); 149c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 150696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 15195923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 152cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if the specified TargetRegisterClass is a 153c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// proper super-class of this TargetRegisterClass. 154c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSuperClass(const TargetRegisterClass *RC) const { 155c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClass(this); 156c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 157c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng 158cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if RC is a super-class of or equal to this class. 1591f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSuperClassEq(const TargetRegisterClass *RC) const { 160c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClassEq(this); 1611f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen } 1621f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen 163cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns a bit vector of subclasses, including this one. 164c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 165c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// use it. 1669ebfbf8b9fd5f982e0db9293808bd32168615ba9Craig Topper const uint32_t *getSubClassMask() const { 167c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SubClassMask; 168c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 16995923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 170cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns a 0-terminated list of sub-register indices that project some 171cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// super-register class into this register class. The list has an entry for 172cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// each Idx such that: 1731a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1741a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// There exists SuperRC where: 1751a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// For all Reg in SuperRC: 1761a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// this->contains(Reg:Idx) 1771a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1781a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *getSuperRegIndices() const { 1791a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen return SuperRegIndices; 1801a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen } 1811a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen 182cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns a NULL-terminated list of super-classes. The 183c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// classes are ordered by ID which is also a topological ordering from large 184c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// to small classes. The list does NOT include the current class. 185c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen sc_iterator getSuperClasses() const { 186c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SuperClasses; 187c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 1888c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng 189cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if this TargetRegisterClass is a subset 190f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// class of at least one other TargetRegisterClass. 1918c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng bool isASubClass() const { 192dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return SuperClasses[0] != nullptr; 1938c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng } 19495923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 195cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns the preferred order for allocating registers from this register 196cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// class in MF. The raw order comes directly from the .td file and may 197cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// include reserved registers that are not allocatable. 198cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Register allocators should also make sure to allocate 19979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers only after all the volatiles are used. The 20079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// RegisterClassInfo class provides filtered allocation orders with 20179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers moved to the end. 20279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 20379c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// The MachineFunction argument can be used to tune the allocatable 20479c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers based on the characteristics of the function, subtarget, or 20579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// other criteria. 20679c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 20779c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// By default, this method returns all registers in the class. 20879c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 209e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { 210ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 21179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen } 212ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 213ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Returns the combination of all lane masks of register in this class. 214ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// The lane masks of the registers are the combination of all lane masks 215ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// of their subregisters. 216cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar LaneBitmask getLaneMask() const { 217ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return LaneMask; 218ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 219282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman}; 220282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 221cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// Extra information, not in MCRegisterDesc, about registers. 222cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// These are used by codegen, not by MC. 223a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengstruct TargetRegisterInfoDesc { 224a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng unsigned CostPerUse; // Extra cost of instructions using register. 225a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool inAllocatableClass; // Register belongs to an allocatable regclass. 226a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng}; 227282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 228ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// Each TargetRegisterClass has a per register weight, and weight 229ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// limit which must be less than the limits of its pressure sets. 230ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trickstruct RegClassWeight { 23133d9e89e5f8d7656e50353b014d5bb1b52f15e13Andrew Trick unsigned RegWeight; 232ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick unsigned WeightLimit; 233ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick}; 234ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick 2356f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// TargetRegisterInfo base class - We assume that the target defines a static 2366f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// array of TargetRegisterDesc objects that represent all of the machine 2376f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// registers that the target has. As such, we simply have to track a pointer 2386f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// to this array so that we can turn register number into a register 2396f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// descriptor. 2403d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 241a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengclass TargetRegisterInfo : public MCRegisterInfo { 2428797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerpublic: 2438797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner typedef const TargetRegisterClass * const * regclass_iterator; 2448797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerprivate: 245a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 2461fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *const *SubRegIndexNames; // Names of subreg indexes. 247a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen // Pointer to array of lane masks, one per sub-reg index. 248cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const LaneBitmask *SubRegIndexLaneMasks; 249a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen 2508797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 251997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen unsigned CoveringLanes; 252b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene 2533d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerprotected: 254a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 2556f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassBegin, 2566f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassEnd, 257a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const char *const *SRINames, 258cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const LaneBitmask *SRILaneMasks, 259997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen unsigned CoveringLanes); 2606f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman virtual ~TargetRegisterInfo(); 2613d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerpublic: 2623d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 263b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Register numbers can represent physical registers, virtual registers, and 264b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // sometimes stack slots. The unsigned values are divided into these ranges: 265b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 266b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 0 Not a register, can be used as a sentinel. 267b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [1;2^30) Physical registers assigned by TableGen. 268b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^30;2^31) Stack slots. (Rarely used.) 269b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 270b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 271b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Further sentinels can be allocated from the small negative integers. 272b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // DenseMapInfo<unsigned> uses -1u and -2u. 2733d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 274be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// isStackSlot - Sometimes it is useful the be able to store a non-negative 275be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// frame index in a variable that normally holds a register. isStackSlot() 276be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// returns true if Reg is in the range used for stack slots. 277be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 278da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 279da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// slots, so if a variable may contains a stack slot, always check 280da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// isStackSlot() first. 281be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 282be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static bool isStackSlot(unsigned Reg) { 283da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) >= (1 << 30); 284be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 285be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 286cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Compute the frame index from a register value representing a stack slot. 287be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static int stackSlot2Index(unsigned Reg) { 288be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(isStackSlot(Reg) && "Not a stack slot"); 289da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg - (1u << 30)); 290be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 291be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 292cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Convert a non-negative frame index to a stack slot register value. 293be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static unsigned index2StackSlot(int FI) { 294be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(FI >= 0 && "Cannot hold a negative frame index."); 295da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return FI + (1u << 30); 296be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 297be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 298cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if the specified register number is in 299bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the physical register namespace. 300bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isPhysicalRegister(unsigned Reg) { 301da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 302da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) > 0; 303bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 304bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 305cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if the specified register number is in 306bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the virtual register namespace. 307bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isVirtualRegister(unsigned Reg) { 308da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 309da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) < 0; 310bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 311bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 312cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Convert a virtual register number to a 0-based index. 313c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// The first virtual register in a function will get the index 0. 314c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen static unsigned virtReg2Index(unsigned Reg) { 315da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(isVirtualRegister(Reg) && "Not a virtual register"); 316dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Reg & ~(1u << 31); 317c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen } 318c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen 319cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Convert a 0-based index to a virtual register number. 320b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// This is the inverse operation of VirtReg2IndexFunctor below. 321b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen static unsigned index2VirtReg(unsigned Index) { 322dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Index | (1u << 31); 323b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen } 324b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 325cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns the Register Class of a physical register of the given type, 326cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// picking the most sub register class of the right type that contains this 327cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// physreg. 328d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola const TargetRegisterClass * 32937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const; 330ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 331cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the maximal subclass of the given register class that is 332cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// allocatable or NULL. 333f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass * 334f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick getAllocatableClass(const TargetRegisterClass *RC) const; 335f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 336cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns a bitset indexed by register number indicating if a register is 337cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// allocatable or not. If a register class is specified, returns the subset 338cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// for the class. 339769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohman BitVector getAllocatableSet(const MachineFunction &MF, 340dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *RC = nullptr) const; 341bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos 342cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the additional cost of using this register instead 3436bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// of other registers in its class. 3446bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen unsigned getCostPerUse(unsigned RegNo) const { 345a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].CostPerUse; 3466bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen } 3476bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen 348cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if the register is in the allocation of any register class. 349a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool isInAllocatableClass(unsigned RegNo) const { 350a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].inAllocatableClass; 35193aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos } 35293aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos 353cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the human-readable symbolic target-specific 3541fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// name for the specified SubRegIndex. 3551fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *getSubRegIndexName(unsigned SubIdx) const { 35659f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen assert(SubIdx && SubIdx < getNumSubRegIndices() && 35759f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen "This is not a subregister index"); 3581fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen return SubRegIndexNames[SubIdx-1]; 3591fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen } 3601fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen 361cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return a bitmask representing the parts of a register that are covered by 362cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// SubIdx \see LaneBitmask. 363a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 3644c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar /// SubIdx == 0 is allowed, it has the lane mask ~0u. 365cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { 366a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 367a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen return SubRegIndexLaneMasks[SubIdx]; 368a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen } 369a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen 370997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// The lane masks returned by getSubRegIndexLaneMask() above can only be 371997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// used to determine if sub-registers overlap - they can't be used to 372997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// determine if a set of sub-registers completely cover another 373997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub-register. 374997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 375997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// The X86 general purpose registers have two lanes corresponding to the 376997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have 377997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the 378997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub_32bit sub-register. 379997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 380997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// On the other hand, the ARM NEON lanes fully cover their registers: The 381997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. 382997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// This is related to the CoveredBySubRegs property on register definitions. 383997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 384997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// This function returns a bit mask of lanes that completely cover their 385997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub-registers. More precisely, given: 386997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 387997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// Covering = getCoveringLanes(); 388997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// MaskA = getSubRegIndexLaneMask(SubA); 389997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// MaskB = getSubRegIndexLaneMask(SubB); 390997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 391997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by 392997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// SubB. 393cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar LaneBitmask getCoveringLanes() const { return CoveringLanes; } 394997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen 395cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if the two registers are equal or alias each other. 396cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// The registers may be virtual registers. 3973f2f3f5341374c85955cfaffa71886724999762dLang Hames bool regsOverlap(unsigned regA, unsigned regB) const { 3981e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (regA == regB) return true; 3993f2f3f5341374c85955cfaffa71886724999762dLang Hames if (isVirtualRegister(regA) || isVirtualRegister(regB)) 4003f2f3f5341374c85955cfaffa71886724999762dLang Hames return false; 40196feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen 40296feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen // Regunits are numerically ordered. Find a common unit. 40396feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen MCRegUnitIterator RUA(regA, this); 40496feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen MCRegUnitIterator RUB(regB, this); 40596feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen do { 40696feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen if (*RUA == *RUB) return true; 40796feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen if (*RUA < *RUB) ++RUA; 40896feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen else ++RUB; 40996feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen } while (RUA.isValid() && RUB.isValid()); 41004319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos return false; 41104319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos } 41204319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos 413cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if Reg contains RegUnit. 41428897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { 41528897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) 41628897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen if (*Units == RegUnit) 41728897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen return true; 41828897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen return false; 41928897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen } 42028897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen 421cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return a null-terminated list of all of the callee-saved registers on 422cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// this target. The register should be in the order of desired callee-save 423cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// stack frame offset. The first register is closest to the incoming stack 424cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// pointer if stack grows down, and vice versa. 425bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 426dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines virtual const MCPhysReg* 4274c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar getCalleeSavedRegs(const MachineFunction *MF) const = 0; 4288797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 429cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual const MCPhysReg* 430cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar getCalleeSavedRegsViaCopy(const MachineFunction *MF) const { 431cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return nullptr; 432cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 433cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 434cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return a mask of call-preserved registers for the given calling convention 435cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// on the current function. The mask should include all call-preserved 436cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// aliases. This is used by the register allocator to determine which 437cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// registers can be live across a call. 438bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 439bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 440bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// A set bit indicates that all bits of the corresponding register are 441bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// preserved across the function call. The bit mask is expected to be 442bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-register complete, i.e. if A is preserved, so are all its 443bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-registers. 444bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 445bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// Bits are numbered from the LSB, so the bit for physical register Reg can 446bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 447478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// 448478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// A NULL pointer means that no register mask will be used, and call 449478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// instructions should use implicit-def operands to indicate call clobbered 450478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// registers. 451bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 4524c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF, 4534c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar CallingConv::ID) const { 454bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen // The default mask clobbers everything. All targets should override. 455dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 456bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen } 4578797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 458cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return a register mask that clobbers everything. 459cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual const uint32_t *getNoPreservedMask() const { 460cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar llvm_unreachable("target does not provide no presered mask"); 461cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 462cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 463cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return all the call-preserved register masks defined for this target. 464cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual ArrayRef<const uint32_t *> getRegMasks() const = 0; 465cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual ArrayRef<const char *> getRegMaskNames() const = 0; 466cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 467cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns a bitset indexed by physical register number indicating if a 468cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// register is a special register that has particular uses and should be 469cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// considered unavailable at all times, e.g. SP, RA. This is 4701c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// used by register scavenger to determine what registers are free. 471b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 472b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 473ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Prior to adding the live-out mask to a stackmap or patchpoint 474ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// instruction, provide the target the opportunity to adjust it (mainly to 475ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// remove pseudo-registers that should be ignored). 476ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const { } 477ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 478cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return a super-register of the specified register 4798a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// Reg so its sub-register of index SubIdx is Reg. 48095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 4818a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng const TargetRegisterClass *RC) const { 48233ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 4838a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng } 4848a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng 485cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return a subclass of the specified register 4865248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// class A so that each register in it has a sub-register of the 4875248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// specified sub-register index which is in the specified register class B. 488570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// 489570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing A sub-classes. 4905248468473f0488a652b545ad95f7abda302b7b5Evan Cheng virtual const TargetRegisterClass * 4915248468473f0488a652b545ad95f7abda302b7b5Evan Cheng getMatchingSuperRegClass(const TargetRegisterClass *A, 492dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen const TargetRegisterClass *B, unsigned Idx) const; 4935248468473f0488a652b545ad95f7abda302b7b5Evan Cheng 494cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // For a copy-like instruction that defines a register of class DefRC with 495cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // subreg index DefSubReg, reading from another source with class SrcRC and 496cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // subregister SrcSubReg return true if this is a preferrable copy 497cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // instruction or an earlier use should be used. 498cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 499cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned DefSubReg, 500cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *SrcRC, 501cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned SrcSubReg) const; 502cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 503cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns the largest legal sub-class of RC that 504845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supports the sub-register index Idx. 505845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If no such sub-class exists, return NULL. 506845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If all registers in RC already have an Idx sub-register, return RC. 507845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 508845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// TableGen generates a version of this function that is good enough in most 509845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// cases. Targets can override if they have constraints that TableGen 510845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// doesn't understand. For example, the x86 sub_8bit sub-register index is 511845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supported by the full GR32 register class in 64-bit mode, but only by the 512845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// GR32_ABCD regiister class in 32-bit mode. 513845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 514570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing RC sub-classes. 515845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen virtual const TargetRegisterClass * 516309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 517309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen assert(Idx == 0 && "Target has no sub-registers"); 518309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen return RC; 519309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen } 520845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen 521cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the subregister index you get from composing 5222da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// two subregister indices. 5232da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 524ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// The special null sub-register index composes as the identity. 525ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// 5262da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 5272da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// returns c. Note that composeSubRegIndices does not tell you about illegal 5282da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// compositions. If R does not have a subreg a, or R:a does not have a subreg 5292da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// b, composeSubRegIndices doesn't tell you. 5302da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 5312da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 5322da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// ssub_0:S0 - ssub_3:S3 subregs. 5332da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 5342da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 535ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen unsigned composeSubRegIndices(unsigned a, unsigned b) const { 536ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen if (!a) return b; 537ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen if (!b) return a; 538ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen return composeSubRegIndicesImpl(a, b); 5392da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen } 5402da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen 541ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Transforms a LaneMask computed for one subregister to the lanemask that 542ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// would have been computed when composing the subsubregisters with IdxA 543ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// first. @sa composeSubRegIndices() 544cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, 545cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar LaneBitmask Mask) const { 546ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (!IdxA) 547cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return Mask; 548cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return composeSubRegIndexLaneMaskImpl(IdxA, Mask); 549ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 550ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 55137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// Debugging helper: dump register in human readable form to dbgs() stream. 55237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0, 55337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterInfo* TRI = nullptr); 55437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 555ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesenprotected: 556ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// Overridden by TableGen in targets that have sub-registers. 557ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { 558ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen llvm_unreachable("Target has no sub-registers"); 559ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen } 560ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen 561ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Overridden by TableGen in targets that have sub-registers. 562cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual LaneBitmask 563cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const { 564ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines llvm_unreachable("Target has no sub-registers"); 565ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 566ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 567ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesenpublic: 568cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Find a common super-register class if it exists. 569fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 570fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// Find a register class, SuperRC and two sub-register indices, PreA and 571fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// PreB, such that: 572fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 573fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 574fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 575fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 576fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 577fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 578fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 579fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 580fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// requirements, and there is no register class with a smaller spill size 581fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// that satisfies the requirements. 582fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 583fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. 584fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 585fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// Either of the PreA and PreB sub-register indices may be returned as 0. In 586fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// that case, the returned register class will be a sub-class of the 587fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// corresponding argument register class. 588fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 589fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// The function returns NULL if no register class can be found. 590fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 591fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass* 592fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 593fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *RCB, unsigned SubB, 594fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned &PreA, unsigned &PreB) const; 595fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 5968797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner //===--------------------------------------------------------------------===// 5978797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // Register Class Information 5988797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // 5998797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 6008797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner /// Register class iterators 60192988ecdb6ca641ba39d1d1f8cbc57a89b63bbadChris Lattner /// 6028797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_begin() const { return RegClassBegin; } 6038797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_end() const { return RegClassEnd; } 6048797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 6058797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner unsigned getNumRegClasses() const { 60634cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)(regclass_end()-regclass_begin()); 6078797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner } 60895923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 609cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns the register class associated with the enumeration value. 610cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// See class MCOperandInfo. 61160f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey const TargetRegisterClass *getRegClass(unsigned i) const { 612a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman assert(i < getNumRegClasses() && "Register Class ID out of range"); 613a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman return RegClassBegin[i]; 61460f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey } 6158797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 616cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns the name of the register class. 61737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const char *getRegClassName(const TargetRegisterClass *Class) const { 61837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return MCRegisterInfo::getRegClassName(Class->MC); 61937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines } 62037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 621cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Find the largest common subclass of A and B. 622cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return NULL if there is no common subclass. 623cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// The common subclass should contain 624cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// simple value type SVT if it is not the Any type. 625e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass * 626e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen getCommonSubClass(const TargetRegisterClass *A, 627cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *B, 628cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const MVT::SimpleValueType SVT = 629cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MVT::SimpleValueType::Any) const; 630e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 631cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns a TargetRegisterClass used for pointer values. 632cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// If a target supports multiple different pointer register classes, 6332cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// kind specifies which one is indicated. 634397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen virtual const TargetRegisterClass * 635397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const { 63650bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement getPointerRegClass!"); 637770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng } 6388797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 639cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns a legal register class to copy a register in the specified class 640cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// to or from. If it is possible to copy the register directly without using 641cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// a cross register class copy, return the specified RC. Returns NULL if it 642cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// is not possible to copy between two registers of the specified class. 643ff110265753c19daf0468ee1facf357460497b7eEvan Cheng virtual const TargetRegisterClass * 644ff110265753c19daf0468ee1facf357460497b7eEvan Cheng getCrossCopyRegClass(const TargetRegisterClass *RC) const { 645b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng return RC; 646ff110265753c19daf0468ee1facf357460497b7eEvan Cheng } 647ff110265753c19daf0468ee1facf357460497b7eEvan Cheng 648cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns the largest super class of RC that is legal to use in the current 649cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// sub-target and has the same spill size. 650c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The returned register class can be used to create virtual registers which 651c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// means that all its registers can be copied and spilled. 6524c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar virtual const TargetRegisterClass * 6534c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar getLargestLegalSuperClass(const TargetRegisterClass *RC, 6544c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const MachineFunction &) const { 655c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The default implementation is very conservative and doesn't allow the 656c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// register allocator to inflate register classes. 657c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 658c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 659c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen 660cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return the register pressure "high water mark" for the specific register 661cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// class. The scheduler is in high register pressure mode (for the specific 662cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// register class) if it goes over the limit. 663decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// 664decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Note: this is the old register pressure model that relies on a manually 665decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// specified representative register class per value type. 666be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 667be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 668be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 669be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 670be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 671cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return a heuristic for the machine scheduler to compare the profitability 672cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// of increasing one register pressure set versus another. The scheduler 673cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// will prefer increasing the register pressure of the set which returns 674cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// the largest value for this function. 675cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual unsigned getRegPressureSetScore(const MachineFunction &MF, 676cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned PSetID) const { 677cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return PSetID; 678cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 679cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 68083dbce2fc817fcb094a8958ca713fd3ba13758c5Andrew Trick /// Get the weight in units of pressure for this register class. 681ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick virtual const RegClassWeight &getRegClassWeight( 682ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick const TargetRegisterClass *RC) const = 0; 683decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 684eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick /// Get the weight in units of pressure for this register unit. 685eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0; 686eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick 687decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the number of dimensions of register pressure. 688decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getNumRegPressureSets() const = 0; 689decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 690d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick /// Get the name of this register unit pressure set. 691d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 692d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick 693decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the register unit pressure limit for this dimension. 694decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// This limit must be adjusted dynamically for reserved registers. 6954c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, 6964c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar unsigned Idx) const = 0; 697decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 698decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the dimensions of register pressure impacted by this register class. 699decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Returns a -1 terminated array of pressure set IDs. 700decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual const int *getRegClassPressureSets( 701decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick const TargetRegisterClass *RC) const = 0; 702decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 703eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick /// Get the dimensions of register pressure impacted by this register unit. 704eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick /// Returns a -1 terminated array of pressure set IDs. 705eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0; 706eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick 7077eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// Get a list of 'hint' registers that the register allocator should try 7087eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// first when allocating a physical register for the virtual register 7097eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// VirtReg. These registers are effectively moved to the front of the 7107eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// allocation order. 7117eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// 7127eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// The Order argument is the allocation order for VirtReg's register class 7137eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// as returned from RegisterClassInfo::getOrder(). The hint registers must 7147eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// come from Order, and they must not be reserved. 7157eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// 7167eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// The default implementation of this function can resolve 7177eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// target-independent hints provided to MRI::setRegAllocationHint with 7187eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// HintType == 0. Targets that override this function should defer to the 7197eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// default implementation if they have no reason to change the allocation 7207eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// order for VirtReg. There may be target-independent hints. 7217eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen virtual void getRegAllocationHints(unsigned VirtReg, 7227eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 7237eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 7247eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const MachineFunction &MF, 725cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const VirtRegMap *VRM = nullptr, 726cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const LiveRegMatrix *Matrix = nullptr) 727cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const; 728cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 729cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// A callback to allow target a chance to update register allocation hints 730cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// when a register is "changed" (e.g. coalesced) to another register. 731cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// e.g. On ARM, some virtual registers should target register pairs, 732cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// if one of pair is coalesced to another register, the allocation hint of 733cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// the other half of the pair should be changed to point to the new register. 734ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, 735f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng MachineFunction &MF) const { 736f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng // Do nothing. 737f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng } 738f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng 73936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// Allow the target to reverse allocation order of local live ranges. This 74036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// will generally allocate shorter local live ranges first. For targets with 74136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// many registers, this could reduce regalloc compile time by a large 74236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// factor. It is disabled by default for three reasons: 74336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// (1) Top-down allocation is simpler and easier to debug for targets that 74436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// don't benefit from reversing the order. 74536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// (2) Bottom-up allocation could result in poor evicition decisions on some 74636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// targets affecting the performance of compiled code. 74736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// (3) Bottom-up allocation is no longer guaranteed to optimally color. 74836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines virtual bool reverseLocalAssignment() const { return false; } 74936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 75036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// Allow the target to override the cost of using a callee-saved register for 75136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// the first time. Default value of 0 means we will use a callee-saved 75236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// register if it is available. 75336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines virtual unsigned getCSRFirstUseCost() const { return 0; } 75436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 755cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if the target requires (and can make use of) the register 756cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// scavenger. 75736230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 75837f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng return false; 75937f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng } 76095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 761cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if the target wants to use frame pointer based accesses to 762cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// spill to the scavenger emergency spill slot. 7630f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 7640f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach return true; 7650f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach } 7660f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach 767cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if the target requires post PEI scavenging of registers for 768cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// materializing frame index constants. 76965c58daa8b8985d2116216043103009815a55e77Jim Grosbach virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 77065c58daa8b8985d2116216043103009815a55e77Jim Grosbach return false; 77165c58daa8b8985d2116216043103009815a55e77Jim Grosbach } 77265c58daa8b8985d2116216043103009815a55e77Jim Grosbach 773cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if the target wants the LocalStackAllocation pass to be run 774cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// and virtual base registers used for more efficient stack access. 775a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 776a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return false; 777a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach } 778a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 779cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if target has reserved a spill slot in the stack frame of 780cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// the given function for the specified register. e.g. On x86, if the frame 781cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// register is required, the first fixed stack object is reserved as its 782cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// spill slot. This tells PEI not to create a new stack frame 783910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// object for the given register. It should be called only after 784cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// determineCalleeSaves(). 78572852a8cfb605056d87b644d2e36b1346051413dEric Christopher virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 786910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng int &FrameIdx) const { 787910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng return false; 788910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng } 789910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng 790cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if the live-ins should be tracked after register allocation. 7916a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 7926a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return false; 7936a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd } 7946a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 795cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// True if the stack can be realigned for the target. 796cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual bool canRealignStack(const MachineFunction &MF) const; 797cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 798cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// True if storage within the function requires the stack pointer to be 799cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// aligned more than the normal calling convention calls for. 800cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// This cannot be overriden by the target, but canRealignStack can be 801cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// overridden. 802cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool needsStackRealignment(const MachineFunction &MF) const; 803b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen 804cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Get the offset from the referenced frame index in the instruction, 805cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// if there is one. 8061ab3f16f06698596716593a30545799688acccd7Jim Grosbach virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 8071ab3f16f06698596716593a30545799688acccd7Jim Grosbach int Idx) const { 808e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return 0; 809e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 810e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 811cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Returns true if the instruction's frame index reference would be better 812cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// served by a base register other than FP or SP. 813cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Used by LocalStackFrameAllocation to determine which frame index 8148708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// references it should create new base registers for. 8153197380143cdc18837722129ac888528b9fbfc2bJim Grosbach virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 8168708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 8178708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 8188708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 819cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx 820cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// before insertion point I. 821976ef86689ed065361a748f81c44ca3510af2202Bill Wendling virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 822e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned BaseReg, int FrameIdx, 823e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 82450bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("materializeFrameBaseRegister does not exist on this " 82550bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target"); 826dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 827dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 828cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Resolve a frame index operand of an instruction 829dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// to reference the indicated base register plus offset instead. 83036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 83136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines int64_t Offset) const { 83250bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("resolveFrameIndex does not exist on this target"); 833dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 834dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 835cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Determine whether a given base register plus offset immediate is 836cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// encodable to resolve a frame index. 8374c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 838e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 83950bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 84074d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach } 841dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 842cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Spill the register so it can be used by the register scavenger. 843cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// Return true if the register was spilled, false otherwise. 844cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// If this function does not spill the register, the scavenger 845540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// will instead spill it to the emergency spill slot. 846540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// 847540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 848540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach MachineBasicBlock::iterator I, 849d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach MachineBasicBlock::iterator &UseMI, 850540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach const TargetRegisterClass *RC, 8511f8f4d2db734d9881467a5706acac73660842d43Evan Cheng unsigned Reg) const { 8521f8f4d2db734d9881467a5706acac73660842d43Evan Cheng return false; 8531f8f4d2db734d9881467a5706acac73660842d43Evan Cheng } 854540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach 855cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// This method must be overriden to eliminate abstract frame indices from 856cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// instructions which may use them. The instruction referenced by the 857cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// iterator contains an MO_FrameIndex operand which must be eliminated by 858cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// this method. This method may modify or replace the specified instruction, 859cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// as long as it keeps the iterator pointing at the finished product. 860cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// SPAdj is the SP adjustment due to call frame setup instruction. 861cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar /// FIOperandNum is the FI operand number. 862fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 863108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 864dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines RegScavenger *RS = nullptr) const = 0; 865f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 866a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey //===--------------------------------------------------------------------===// 86737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// Subtarget Hooks 86837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 86937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true. 87037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines virtual bool shouldCoalesce(MachineInstr *MI, 87137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *SrcRC, 87237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned SubReg, 87337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *DstRC, 87437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned DstSubReg, 87537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *NewRC) const 87637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines { return true; } 87737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 87837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines //===--------------------------------------------------------------------===// 879a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// Debug information queries. 88095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 881a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// getFrameRegister - This method should return the register used as a base 8824188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// for values allocated in the current stack frame. 883b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 8843d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 8853d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 886c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng 88789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 88889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// SuperRegClassIterator 88989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 89089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 89189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// Iterate over the possible super-registers for a given register class. The 89289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// iterator will visit a list of pairs (Idx, Mask) corresponding to the 89389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// possible classes of super-registers. 89489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 89589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// Each bit mask will have at least one set bit, and each set bit in Mask 89689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// corresponds to a SuperRC such that: 89789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 89889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// For all Reg in SuperRC: Reg:Idx is in RC. 89989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 90089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// The iterator can include (O, RC->getSubClassMask()) as the first entry which 90189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// also satisfies the above requirement, assuming Reg:0 == Reg. 90289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 90389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesenclass SuperRegClassIterator { 90489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const unsigned RCMaskWords; 90589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen unsigned SubReg; 90689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint16_t *Idx; 90789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint32_t *Mask; 90889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 90989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesenpublic: 91089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Create a SuperRegClassIterator that visits all the super-register classes 91189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry. 91289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SuperRegClassIterator(const TargetRegisterClass *RC, 91389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const TargetRegisterInfo *TRI, 91489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen bool IncludeSelf = false) 91589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen : RCMaskWords((TRI->getNumRegClasses() + 31) / 32), 91689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SubReg(0), 91789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Idx(RC->getSuperRegIndices()), 91889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Mask(RC->getSubClassMask()) { 91989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen if (!IncludeSelf) 92089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen ++*this; 92189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen } 92289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 92389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns true if this iterator is still pointing at a valid entry. 92489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen bool isValid() const { return Idx; } 92589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 92689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns the current sub-register index. 92789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen unsigned getSubReg() const { return SubReg; } 92889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 92989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns the bit mask if register classes that getSubReg() projects into 93089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// RC. 93189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint32_t *getMask() const { return Mask; } 93289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 93389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Advance iterator to the next entry. 93489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen void operator++() { 93589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen assert(isValid() && "Cannot move iterator past end."); 93689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Mask += RCMaskWords; 93789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SubReg = *Idx++; 93889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen if (!SubReg) 939dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Idx = nullptr; 94089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen } 94189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen}; 94289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 94394c002a190cd2e3a52b1510bc997e53d63af0b3bChris Lattner// This is useful when building IndexedMaps keyed on virtual registers 94459bf4fcc0680e75b408579064d1205a132361196Duncan Sandsstruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 9454d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos unsigned operator()(unsigned Reg) const { 946c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen return TargetRegisterInfo::virtReg2Index(Reg); 9474d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos } 9484d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos}; 9494d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos 9504314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Prints virtual and physical registers with or without a TRI instance. 9514314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 9524314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// The format is: 95343a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %noreg - NoRegister 95443a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5 - a virtual register. 95543a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 95643a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %EAX - a physical register 95743a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %physreg17 - a physical register when no TRI instance given. 9584314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 9594314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 960cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarPrintable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, 961cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned SubRegIdx = 0); 9624314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 963cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// Create Printable object to print register units on a \ref raw_ostream. 9645ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 9655ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// Register units are named after their root registers: 9665ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 9675ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// AL - Single root. 9685ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// FP0~ST7 - Dual roots. 9695ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 9705ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; 971cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarPrintable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI); 9725ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 973cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// \brief Create Printable object to print virtual registers and physical 974cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// registers on a \ref raw_ostream. 975cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarPrintable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI); 97612d3dc73dc44acd8b11cca783b826ccbd66f44daAndrew Trick 977cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar/// Create Printable object to print LaneBitmasks on a \ref raw_ostream. 978cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarPrintable PrintLaneMask(LaneBitmask LaneMask); 97912d3dc73dc44acd8b11cca783b826ccbd66f44daAndrew Trick 980d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 981d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 9823d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#endif 983