CriticalAntiDepBreaker.cpp revision 46388526963aba92344ee8ebd9e86d3556baa088
1//===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the CriticalAntiDepBreaker class, which 11// implements register anti-dependence breaking along a blocks 12// critical path during post-RA scheduler. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "post-RA-sched" 17#include "CriticalAntiDepBreaker.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include "llvm/Target/TargetRegisterInfo.h" 23#include "llvm/Support/Debug.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26 27using namespace llvm; 28 29CriticalAntiDepBreaker:: 30CriticalAntiDepBreaker(MachineFunction& MFi) : 31 AntiDepBreaker(), MF(MFi), 32 MRI(MF.getRegInfo()), 33 TII(MF.getTarget().getInstrInfo()), 34 TRI(MF.getTarget().getRegisterInfo()), 35 AllocatableSet(TRI->getAllocatableSet(MF)), 36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), 37 KillIndices(TRI->getNumRegs(), 0), 38 DefIndices(TRI->getNumRegs(), 0) {} 39 40CriticalAntiDepBreaker::~CriticalAntiDepBreaker() { 41} 42 43void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { 44 const unsigned BBSize = BB->size(); 45 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { 46 // Clear out the register class data. 47 Classes[i] = static_cast<const TargetRegisterClass *>(0); 48 49 // Initialize the indices to indicate that no registers are live. 50 KillIndices[i] = ~0u; 51 DefIndices[i] = BBSize; 52 } 53 54 // Clear "do not change" set. 55 KeepRegs.clear(); 56 57 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); 58 59 // Determine the live-out physregs for this block. 60 if (IsReturnBlock) { 61 // In a return block, examine the function live-out regs. 62 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(), 63 E = MRI.liveout_end(); I != E; ++I) { 64 unsigned Reg = *I; 65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 66 KillIndices[Reg] = BB->size(); 67 DefIndices[Reg] = ~0u; 68 69 // Repeat, for all aliases. 70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 71 unsigned AliasReg = *Alias; 72 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 73 KillIndices[AliasReg] = BB->size(); 74 DefIndices[AliasReg] = ~0u; 75 } 76 } 77 } 78 79 // In a non-return block, examine the live-in regs of all successors. 80 // Note a return block can have successors if the return instruction is 81 // predicated. 82 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 83 SE = BB->succ_end(); SI != SE; ++SI) 84 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), 85 E = (*SI)->livein_end(); I != E; ++I) { 86 unsigned Reg = *I; 87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 88 KillIndices[Reg] = BB->size(); 89 DefIndices[Reg] = ~0u; 90 91 // Repeat, for all aliases. 92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 93 unsigned AliasReg = *Alias; 94 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 95 KillIndices[AliasReg] = BB->size(); 96 DefIndices[AliasReg] = ~0u; 97 } 98 } 99 100 // Mark live-out callee-saved registers. In a return block this is 101 // all callee-saved registers. In non-return this is any 102 // callee-saved register that is not saved in the prolog. 103 const MachineFrameInfo *MFI = MF.getFrameInfo(); 104 BitVector Pristine = MFI->getPristineRegs(BB); 105 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) { 106 unsigned Reg = *I; 107 if (!IsReturnBlock && !Pristine.test(Reg)) continue; 108 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 109 KillIndices[Reg] = BB->size(); 110 DefIndices[Reg] = ~0u; 111 112 // Repeat, for all aliases. 113 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 114 unsigned AliasReg = *Alias; 115 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 116 KillIndices[AliasReg] = BB->size(); 117 DefIndices[AliasReg] = ~0u; 118 } 119 } 120} 121 122void CriticalAntiDepBreaker::FinishBlock() { 123 RegRefs.clear(); 124 KeepRegs.clear(); 125} 126 127void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, 128 unsigned InsertPosIndex) { 129 if (MI->isDebugValue()) 130 return; 131 assert(Count < InsertPosIndex && "Instruction index out of expected range!"); 132 133 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 134 if (KillIndices[Reg] != ~0u) { 135 // If Reg is currently live, then mark that it can't be renamed as 136 // we don't know the extent of its live-range anymore (now that it 137 // has been scheduled). 138 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 139 KillIndices[Reg] = Count; 140 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { 141 // Any register which was defined within the previous scheduling region 142 // may have been rescheduled and its lifetime may overlap with registers 143 // in ways not reflected in our current liveness state. For each such 144 // register, adjust the liveness state to be conservatively correct. 145 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 146 147 // Move the def index to the end of the previous region, to reflect 148 // that the def could theoretically have been scheduled at the end. 149 DefIndices[Reg] = InsertPosIndex; 150 } 151 } 152 153 PrescanInstruction(MI); 154 ScanInstruction(MI, Count); 155} 156 157/// CriticalPathStep - Return the next SUnit after SU on the bottom-up 158/// critical path. 159static const SDep *CriticalPathStep(const SUnit *SU) { 160 const SDep *Next = 0; 161 unsigned NextDepth = 0; 162 // Find the predecessor edge with the greatest depth. 163 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); 164 P != PE; ++P) { 165 const SUnit *PredSU = P->getSUnit(); 166 unsigned PredLatency = P->getLatency(); 167 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency; 168 // In the case of a latency tie, prefer an anti-dependency edge over 169 // other types of edges. 170 if (NextDepth < PredTotalLatency || 171 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 172 NextDepth = PredTotalLatency; 173 Next = &*P; 174 } 175 } 176 return Next; 177} 178 179void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { 180 // It's not safe to change register allocation for source operands of 181 // that have special allocation requirements. Also assume all registers 182 // used in a call must not be changed (ABI). 183 // FIXME: The issue with predicated instruction is more complex. We are being 184 // conservative here because the kill markers cannot be trusted after 185 // if-conversion: 186 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] 187 // ... 188 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395] 189 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12] 190 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) 191 // 192 // The first R6 kill is not really a kill since it's killed by a predicated 193 // instruction which may not be executed. The second R6 def may or may not 194 // re-define R6 so it's not safe to change it since the last R6 use cannot be 195 // changed. 196 bool Special = MI->getDesc().isCall() || 197 MI->getDesc().hasExtraSrcRegAllocReq() || 198 TII->isPredicated(MI); 199 200 // Scan the register operands for this instruction and update 201 // Classes and RegRefs. 202 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 203 MachineOperand &MO = MI->getOperand(i); 204 if (!MO.isReg()) continue; 205 unsigned Reg = MO.getReg(); 206 if (Reg == 0) continue; 207 const TargetRegisterClass *NewRC = 0; 208 209 if (i < MI->getDesc().getNumOperands()) 210 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); 211 212 // For now, only allow the register to be changed if its register 213 // class is consistent across all uses. 214 if (!Classes[Reg] && NewRC) 215 Classes[Reg] = NewRC; 216 else if (!NewRC || Classes[Reg] != NewRC) 217 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 218 219 // Now check for aliases. 220 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 221 // If an alias of the reg is used during the live range, give up. 222 // Note that this allows us to skip checking if AntiDepReg 223 // overlaps with any of the aliases, among other things. 224 unsigned AliasReg = *Alias; 225 if (Classes[AliasReg]) { 226 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 227 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 228 } 229 } 230 231 // If we're still willing to consider this register, note the reference. 232 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) 233 RegRefs.insert(std::make_pair(Reg, &MO)); 234 235 if (MO.isUse() && Special) { 236 if (KeepRegs.insert(Reg)) { 237 for (const unsigned *Subreg = TRI->getSubRegisters(Reg); 238 *Subreg; ++Subreg) 239 KeepRegs.insert(*Subreg); 240 } 241 } 242 } 243} 244 245void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, 246 unsigned Count) { 247 // Update liveness. 248 // Proceding upwards, registers that are defed but not used in this 249 // instruction are now dead. 250 251 if (!TII->isPredicated(MI)) { 252 // Predicated defs are modeled as read + write, i.e. similar to two 253 // address updates. 254 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 255 MachineOperand &MO = MI->getOperand(i); 256 if (!MO.isReg()) continue; 257 unsigned Reg = MO.getReg(); 258 if (Reg == 0) continue; 259 if (!MO.isDef()) continue; 260 // Ignore two-addr defs. 261 if (MI->isRegTiedToUseOperand(i)) continue; 262 263 DefIndices[Reg] = Count; 264 KillIndices[Reg] = ~0u; 265 assert(((KillIndices[Reg] == ~0u) != 266 (DefIndices[Reg] == ~0u)) && 267 "Kill and Def maps aren't consistent for Reg!"); 268 KeepRegs.erase(Reg); 269 Classes[Reg] = 0; 270 RegRefs.erase(Reg); 271 // Repeat, for all subregs. 272 for (const unsigned *Subreg = TRI->getSubRegisters(Reg); 273 *Subreg; ++Subreg) { 274 unsigned SubregReg = *Subreg; 275 DefIndices[SubregReg] = Count; 276 KillIndices[SubregReg] = ~0u; 277 KeepRegs.erase(SubregReg); 278 Classes[SubregReg] = 0; 279 RegRefs.erase(SubregReg); 280 } 281 // Conservatively mark super-registers as unusable. 282 for (const unsigned *Super = TRI->getSuperRegisters(Reg); 283 *Super; ++Super) { 284 unsigned SuperReg = *Super; 285 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1); 286 } 287 } 288 } 289 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 290 MachineOperand &MO = MI->getOperand(i); 291 if (!MO.isReg()) continue; 292 unsigned Reg = MO.getReg(); 293 if (Reg == 0) continue; 294 if (!MO.isUse()) continue; 295 296 const TargetRegisterClass *NewRC = 0; 297 if (i < MI->getDesc().getNumOperands()) 298 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); 299 300 // For now, only allow the register to be changed if its register 301 // class is consistent across all uses. 302 if (!Classes[Reg] && NewRC) 303 Classes[Reg] = NewRC; 304 else if (!NewRC || Classes[Reg] != NewRC) 305 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 306 307 RegRefs.insert(std::make_pair(Reg, &MO)); 308 309 // It wasn't previously live but now it is, this is a kill. 310 if (KillIndices[Reg] == ~0u) { 311 KillIndices[Reg] = Count; 312 DefIndices[Reg] = ~0u; 313 assert(((KillIndices[Reg] == ~0u) != 314 (DefIndices[Reg] == ~0u)) && 315 "Kill and Def maps aren't consistent for Reg!"); 316 } 317 // Repeat, for all aliases. 318 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 319 unsigned AliasReg = *Alias; 320 if (KillIndices[AliasReg] == ~0u) { 321 KillIndices[AliasReg] = Count; 322 DefIndices[AliasReg] = ~0u; 323 } 324 } 325 } 326} 327 328// Check all machine instructions that define the antidependent register. 329// Return true if any of these instructions define the new register. 330bool 331CriticalAntiDepBreaker::isNewRegModifiedByRefs(RegRefIter RegRefBegin, 332 RegRefIter RegRefEnd, 333 unsigned NewReg) 334{ 335 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) { 336 MachineOperand *MO = I->second; 337 if (MO->isDef()) continue; 338 if (MO->getParent()->modifiesRegister(NewReg, TRI)) 339 return true; 340 } 341 return false; 342} 343 344unsigned 345CriticalAntiDepBreaker::findSuitableFreeRegister(RegRefIter RegRefBegin, 346 RegRefIter RegRefEnd, 347 unsigned AntiDepReg, 348 unsigned LastNewReg, 349 const TargetRegisterClass *RC) 350{ 351 for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF), 352 RE = RC->allocation_order_end(MF); R != RE; ++R) { 353 unsigned NewReg = *R; 354 // Don't consider non-allocatable registers 355 if (!AllocatableSet.test(NewReg)) continue; 356 // Don't replace a register with itself. 357 if (NewReg == AntiDepReg) continue; 358 // Don't replace a register with one that was recently used to repair 359 // an anti-dependence with this AntiDepReg, because that would 360 // re-introduce that anti-dependence. 361 if (NewReg == LastNewReg) continue; 362 // If any instructions that define AntiDepReg also define the NewReg, it's 363 // not suitable. For example, Instruction with multiple definitions can 364 // result in this condition. 365 if (isNewRegModifiedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue; 366 // If NewReg is dead and NewReg's most recent def is not before 367 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg. 368 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) 369 && "Kill and Def maps aren't consistent for AntiDepReg!"); 370 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) 371 && "Kill and Def maps aren't consistent for NewReg!"); 372 if (KillIndices[NewReg] != ~0u || 373 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) || 374 KillIndices[AntiDepReg] > DefIndices[NewReg]) 375 continue; 376 return NewReg; 377 } 378 379 // No registers are free and available! 380 return 0; 381} 382 383unsigned CriticalAntiDepBreaker:: 384BreakAntiDependencies(const std::vector<SUnit>& SUnits, 385 MachineBasicBlock::iterator Begin, 386 MachineBasicBlock::iterator End, 387 unsigned InsertPosIndex) { 388 // The code below assumes that there is at least one instruction, 389 // so just duck out immediately if the block is empty. 390 if (SUnits.empty()) return 0; 391 392 // Keep a map of the MachineInstr*'s back to the SUnit representing them. 393 // This is used for updating debug information. 394 DenseMap<MachineInstr*,const SUnit*> MISUnitMap; 395 396 // Find the node at the bottom of the critical path. 397 const SUnit *Max = 0; 398 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 399 const SUnit *SU = &SUnits[i]; 400 MISUnitMap[SU->getInstr()] = SU; 401 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 402 Max = SU; 403 } 404 405#ifndef NDEBUG 406 { 407 DEBUG(dbgs() << "Critical path has total latency " 408 << (Max->getDepth() + Max->Latency) << "\n"); 409 DEBUG(dbgs() << "Available regs:"); 410 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { 411 if (KillIndices[Reg] == ~0u) 412 DEBUG(dbgs() << " " << TRI->getName(Reg)); 413 } 414 DEBUG(dbgs() << '\n'); 415 } 416#endif 417 418 // Track progress along the critical path through the SUnit graph as we walk 419 // the instructions. 420 const SUnit *CriticalPathSU = Max; 421 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); 422 423 // Consider this pattern: 424 // A = ... 425 // ... = A 426 // A = ... 427 // ... = A 428 // A = ... 429 // ... = A 430 // A = ... 431 // ... = A 432 // There are three anti-dependencies here, and without special care, 433 // we'd break all of them using the same register: 434 // A = ... 435 // ... = A 436 // B = ... 437 // ... = B 438 // B = ... 439 // ... = B 440 // B = ... 441 // ... = B 442 // because at each anti-dependence, B is the first register that 443 // isn't A which is free. This re-introduces anti-dependencies 444 // at all but one of the original anti-dependencies that we were 445 // trying to break. To avoid this, keep track of the most recent 446 // register that each register was replaced with, avoid 447 // using it to repair an anti-dependence on the same register. 448 // This lets us produce this: 449 // A = ... 450 // ... = A 451 // B = ... 452 // ... = B 453 // C = ... 454 // ... = C 455 // B = ... 456 // ... = B 457 // This still has an anti-dependence on B, but at least it isn't on the 458 // original critical path. 459 // 460 // TODO: If we tracked more than one register here, we could potentially 461 // fix that remaining critical edge too. This is a little more involved, 462 // because unlike the most recent register, less recent registers should 463 // still be considered, though only if no other registers are available. 464 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0); 465 466 // Attempt to break anti-dependence edges on the critical path. Walk the 467 // instructions from the bottom up, tracking information about liveness 468 // as we go to help determine which registers are available. 469 unsigned Broken = 0; 470 unsigned Count = InsertPosIndex - 1; 471 for (MachineBasicBlock::iterator I = End, E = Begin; 472 I != E; --Count) { 473 MachineInstr *MI = --I; 474 if (MI->isDebugValue()) 475 continue; 476 477 // Check if this instruction has a dependence on the critical path that 478 // is an anti-dependence that we may be able to break. If it is, set 479 // AntiDepReg to the non-zero register associated with the anti-dependence. 480 // 481 // We limit our attention to the critical path as a heuristic to avoid 482 // breaking anti-dependence edges that aren't going to significantly 483 // impact the overall schedule. There are a limited number of registers 484 // and we want to save them for the important edges. 485 // 486 // TODO: Instructions with multiple defs could have multiple 487 // anti-dependencies. The current code here only knows how to break one 488 // edge per instruction. Note that we'd have to be able to break all of 489 // the anti-dependencies in an instruction in order to be effective. 490 unsigned AntiDepReg = 0; 491 if (MI == CriticalPathMI) { 492 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) { 493 const SUnit *NextSU = Edge->getSUnit(); 494 495 // Only consider anti-dependence edges. 496 if (Edge->getKind() == SDep::Anti) { 497 AntiDepReg = Edge->getReg(); 498 assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); 499 if (!AllocatableSet.test(AntiDepReg)) 500 // Don't break anti-dependencies on non-allocatable registers. 501 AntiDepReg = 0; 502 else if (KeepRegs.count(AntiDepReg)) 503 // Don't break anti-dependencies if an use down below requires 504 // this exact register. 505 AntiDepReg = 0; 506 else { 507 // If the SUnit has other dependencies on the SUnit that it 508 // anti-depends on, don't bother breaking the anti-dependency 509 // since those edges would prevent such units from being 510 // scheduled past each other regardless. 511 // 512 // Also, if there are dependencies on other SUnits with the 513 // same register as the anti-dependency, don't attempt to 514 // break it. 515 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(), 516 PE = CriticalPathSU->Preds.end(); P != PE; ++P) 517 if (P->getSUnit() == NextSU ? 518 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 519 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) { 520 AntiDepReg = 0; 521 break; 522 } 523 } 524 } 525 CriticalPathSU = NextSU; 526 CriticalPathMI = CriticalPathSU->getInstr(); 527 } else { 528 // We've reached the end of the critical path. 529 CriticalPathSU = 0; 530 CriticalPathMI = 0; 531 } 532 } 533 534 PrescanInstruction(MI); 535 536 // If MI's defs have a special allocation requirement, don't allow 537 // any def registers to be changed. Also assume all registers 538 // defined in a call must not be changed (ABI). 539 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() || 540 TII->isPredicated(MI)) 541 // If this instruction's defs have special allocation requirement, don't 542 // break this anti-dependency. 543 AntiDepReg = 0; 544 else if (AntiDepReg) { 545 // If this instruction has a use of AntiDepReg, breaking it 546 // is invalid. 547 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 548 MachineOperand &MO = MI->getOperand(i); 549 if (!MO.isReg()) continue; 550 unsigned Reg = MO.getReg(); 551 if (Reg == 0) continue; 552 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { 553 AntiDepReg = 0; 554 break; 555 } 556 } 557 } 558 559 // Determine AntiDepReg's register class, if it is live and is 560 // consistently used within a single class. 561 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0; 562 assert((AntiDepReg == 0 || RC != NULL) && 563 "Register should be live if it's causing an anti-dependence!"); 564 if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 565 AntiDepReg = 0; 566 567 // Look for a suitable register to use to break the anti-depenence. 568 // 569 // TODO: Instead of picking the first free register, consider which might 570 // be the best. 571 if (AntiDepReg != 0) { 572 std::pair<std::multimap<unsigned, MachineOperand *>::iterator, 573 std::multimap<unsigned, MachineOperand *>::iterator> 574 Range = RegRefs.equal_range(AntiDepReg); 575 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second, 576 AntiDepReg, 577 LastNewReg[AntiDepReg], 578 RC)) { 579 DEBUG(dbgs() << "Breaking anti-dependence edge on " 580 << TRI->getName(AntiDepReg) 581 << " with " << RegRefs.count(AntiDepReg) << " references" 582 << " using " << TRI->getName(NewReg) << "!\n"); 583 584 // Update the references to the old register to refer to the new 585 // register. 586 for (std::multimap<unsigned, MachineOperand *>::iterator 587 Q = Range.first, QE = Range.second; Q != QE; ++Q) { 588 Q->second->setReg(NewReg); 589 // If the SU for the instruction being updated has debug information 590 // related to the anti-dependency register, make sure to update that 591 // as well. 592 const SUnit *SU = MISUnitMap[Q->second->getParent()]; 593 if (!SU) continue; 594 for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) { 595 MachineInstr *DI = SU->DbgInstrList[i]; 596 assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() && 597 DI->getOperand(0).getReg() 598 && "Non register dbg_value attached to SUnit!"); 599 if (DI->getOperand(0).getReg() == AntiDepReg) 600 DI->getOperand(0).setReg(NewReg); 601 } 602 } 603 604 // We just went back in time and modified history; the 605 // liveness information for the anti-dependence reg is now 606 // inconsistent. Set the state as if it were dead. 607 Classes[NewReg] = Classes[AntiDepReg]; 608 DefIndices[NewReg] = DefIndices[AntiDepReg]; 609 KillIndices[NewReg] = KillIndices[AntiDepReg]; 610 assert(((KillIndices[NewReg] == ~0u) != 611 (DefIndices[NewReg] == ~0u)) && 612 "Kill and Def maps aren't consistent for NewReg!"); 613 614 Classes[AntiDepReg] = 0; 615 DefIndices[AntiDepReg] = KillIndices[AntiDepReg]; 616 KillIndices[AntiDepReg] = ~0u; 617 assert(((KillIndices[AntiDepReg] == ~0u) != 618 (DefIndices[AntiDepReg] == ~0u)) && 619 "Kill and Def maps aren't consistent for AntiDepReg!"); 620 621 RegRefs.erase(AntiDepReg); 622 LastNewReg[AntiDepReg] = NewReg; 623 ++Broken; 624 } 625 } 626 627 ScanInstruction(MI, Count); 628 } 629 630 return Broken; 631} 632