LiveRangeEdit.cpp revision 2ef661b0e8de0d4186c5f9cc990adce0a2493b17 
1//===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// The LiveRangeEdit class represents changes done to a virtual register when it
11// is spilled or split.
12//===----------------------------------------------------------------------===//
13
14#include "LiveRangeEdit.h"
15#include "VirtRegMap.h"
16#include "llvm/ADT/SetVector.h"
17#include "llvm/CodeGen/LiveIntervalAnalysis.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/raw_ostream.h"
22
23using namespace llvm;
24
25LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg,
26                                        LiveIntervals &LIS,
27                                        VirtRegMap &VRM) {
28  MachineRegisterInfo &MRI = VRM.getRegInfo();
29  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
30  VRM.grow();
31  VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
32  LiveInterval &LI = LIS.getOrCreateInterval(VReg);
33  newRegs_.push_back(&LI);
34  return LI;
35}
36
37void LiveRangeEdit::checkRematerializable(VNInfo *VNI,
38                                          const MachineInstr *DefMI,
39                                          const TargetInstrInfo &tii,
40                                          AliasAnalysis *aa) {
41  assert(DefMI && "Missing instruction");
42  if (tii.isTriviallyReMaterializable(DefMI, aa))
43    remattable_.insert(VNI);
44  scannedRemattable_ = true;
45}
46
47void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
48                                   const TargetInstrInfo &tii,
49                                   AliasAnalysis *aa) {
50  for (LiveInterval::vni_iterator I = parent_.vni_begin(),
51       E = parent_.vni_end(); I != E; ++I) {
52    VNInfo *VNI = *I;
53    if (VNI->isUnused())
54      continue;
55    MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
56    if (!DefMI)
57      continue;
58    checkRematerializable(VNI, DefMI, tii, aa);
59  }
60}
61
62bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
63                                        const TargetInstrInfo &tii,
64                                        AliasAnalysis *aa) {
65  if (!scannedRemattable_)
66    scanRemattable(lis, tii, aa);
67  return !remattable_.empty();
68}
69
70/// allUsesAvailableAt - Return true if all registers used by OrigMI at
71/// OrigIdx are also available with the same value at UseIdx.
72bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
73                                       SlotIndex OrigIdx,
74                                       SlotIndex UseIdx,
75                                       LiveIntervals &lis) {
76  OrigIdx = OrigIdx.getUseIndex();
77  UseIdx = UseIdx.getUseIndex();
78  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
79    const MachineOperand &MO = OrigMI->getOperand(i);
80    if (!MO.isReg() || !MO.getReg() || MO.isDef())
81      continue;
82    // Reserved registers are OK.
83    if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
84      continue;
85    // We cannot depend on virtual registers in uselessRegs_.
86    if (uselessRegs_)
87      for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui)
88        if ((*uselessRegs_)[ui]->reg == MO.getReg())
89          return false;
90
91    LiveInterval &li = lis.getInterval(MO.getReg());
92    const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
93    if (!OVNI)
94      continue;
95    if (OVNI != li.getVNInfoAt(UseIdx))
96      return false;
97  }
98  return true;
99}
100
101bool LiveRangeEdit::canRematerializeAt(Remat &RM,
102                                       SlotIndex UseIdx,
103                                       bool cheapAsAMove,
104                                       LiveIntervals &lis) {
105  assert(scannedRemattable_ && "Call anyRematerializable first");
106
107  // Use scanRemattable info.
108  if (!remattable_.count(RM.ParentVNI))
109    return false;
110
111  // No defining instruction provided.
112  SlotIndex DefIdx;
113  if (RM.OrigMI)
114    DefIdx = lis.getInstructionIndex(RM.OrigMI);
115  else {
116    DefIdx = RM.ParentVNI->def;
117    RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
118    assert(RM.OrigMI && "No defining instruction for remattable value");
119  }
120
121  // If only cheap remats were requested, bail out early.
122  if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
123    return false;
124
125  // Verify that all used registers are available with the same values.
126  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
127    return false;
128
129  return true;
130}
131
132SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
133                                         MachineBasicBlock::iterator MI,
134                                         unsigned DestReg,
135                                         const Remat &RM,
136                                         LiveIntervals &lis,
137                                         const TargetInstrInfo &tii,
138                                         const TargetRegisterInfo &tri) {
139  assert(RM.OrigMI && "Invalid remat");
140  tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
141  rematted_.insert(RM.ParentVNI);
142  return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
143}
144
145void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
146  if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
147    LIS.removeInterval(Reg);
148}
149
150void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
151                                      LiveIntervals &LIS, VirtRegMap &VRM,
152                                      const TargetInstrInfo &TII) {
153  SetVector<LiveInterval*,
154            SmallVector<LiveInterval*, 8>,
155            SmallPtrSet<LiveInterval*, 8> > ToShrink;
156
157  for (;;) {
158    // Erase all dead defs.
159    while (!Dead.empty()) {
160      MachineInstr *MI = Dead.pop_back_val();
161      assert(MI->allDefsAreDead() && "Def isn't really dead");
162      SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
163
164      // Never delete inline asm.
165      if (MI->isInlineAsm()) {
166        DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
167        continue;
168      }
169
170      // Use the same criteria as DeadMachineInstructionElim.
171      bool SawStore = false;
172      if (!MI->isSafeToMove(&TII, 0, SawStore)) {
173        DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
174        continue;
175      }
176
177      DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
178
179      // Check for live intervals that may shrink
180      for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
181             MOE = MI->operands_end(); MOI != MOE; ++MOI) {
182        if (!MOI->isReg())
183          continue;
184        unsigned Reg = MOI->getReg();
185        if (!TargetRegisterInfo::isVirtualRegister(Reg))
186          continue;
187        LiveInterval &LI = LIS.getInterval(Reg);
188
189        // Shrink read registers.
190        if (MI->readsVirtualRegister(Reg))
191          ToShrink.insert(&LI);
192
193        // Remove defined value.
194        if (MOI->isDef()) {
195          if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
196            if (delegate_)
197              delegate_->LRE_WillShrinkVirtReg(LI.reg);
198            LI.removeValNo(VNI);
199            if (LI.empty()) {
200              ToShrink.remove(&LI);
201              eraseVirtReg(Reg, LIS);
202            }
203          }
204        }
205      }
206
207      if (delegate_)
208        delegate_->LRE_WillEraseInstruction(MI);
209      LIS.RemoveMachineInstrFromMaps(MI);
210      MI->eraseFromParent();
211    }
212
213    if (ToShrink.empty())
214      break;
215
216    // Shrink just one live interval. Then delete new dead defs.
217    LiveInterval *LI = ToShrink.back();
218    ToShrink.pop_back();
219    if (delegate_)
220      delegate_->LRE_WillShrinkVirtReg(LI->reg);
221    if (!LIS.shrinkToUses(LI, &Dead))
222      continue;
223
224    // LI may have been separated, create new intervals.
225    LI->RenumberValues(LIS);
226    ConnectedVNInfoEqClasses ConEQ(LIS);
227    unsigned NumComp = ConEQ.Classify(LI);
228    if (NumComp <= 1)
229      continue;
230    DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
231    SmallVector<LiveInterval*, 8> Dups(1, LI);
232    for (unsigned i = 1; i != NumComp; ++i)
233      Dups.push_back(&createFrom(LI->reg, LIS, VRM));
234    ConEQ.Distribute(&Dups[0], VRM.getRegInfo());
235  }
236}
237
238