TwoAddressInstructionPass.cpp revision 15993f83a419950f06d2879d6701530ae6449317
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the TwoAddress instruction pass which is used 11// by most register allocators. Two-Address instructions are rewritten 12// from: 13// 14// A = B op C 15// 16// to: 17// 18// A = B 19// A op= C 20// 21// Note that if a register allocator chooses to use this pass, that it 22// has to be capable of handling the non-SSA nature of these rewritten 23// virtual registers. 24// 25// It is also worth noting that the duplicate operand of the two 26// address instruction is removed. 27// 28//===----------------------------------------------------------------------===// 29 30#define DEBUG_TYPE "twoaddrinstr" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/Function.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineInstr.h" 36#include "llvm/CodeGen/MachineInstrBuilder.h" 37#include "llvm/CodeGen/MachineRegisterInfo.h" 38#include "llvm/Analysis/AliasAnalysis.h" 39#include "llvm/Target/TargetRegisterInfo.h" 40#include "llvm/Target/TargetInstrInfo.h" 41#include "llvm/Target/TargetMachine.h" 42#include "llvm/Target/TargetOptions.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/ErrorHandling.h" 45#include "llvm/ADT/BitVector.h" 46#include "llvm/ADT/DenseMap.h" 47#include "llvm/ADT/SmallSet.h" 48#include "llvm/ADT/Statistic.h" 49#include "llvm/ADT/STLExtras.h" 50using namespace llvm; 51 52STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions"); 53STATISTIC(NumCommuted , "Number of instructions commuted to coalesce"); 54STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted"); 55STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address"); 56STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk"); 57STATISTIC(NumReMats, "Number of instructions re-materialized"); 58STATISTIC(NumDeletes, "Number of dead instructions deleted"); 59 60namespace { 61 class TwoAddressInstructionPass : public MachineFunctionPass { 62 const TargetInstrInfo *TII; 63 const TargetRegisterInfo *TRI; 64 MachineRegisterInfo *MRI; 65 LiveVariables *LV; 66 AliasAnalysis *AA; 67 68 // DistanceMap - Keep track the distance of a MI from the start of the 69 // current basic block. 70 DenseMap<MachineInstr*, unsigned> DistanceMap; 71 72 // SrcRegMap - A map from virtual registers to physical registers which 73 // are likely targets to be coalesced to due to copies from physical 74 // registers to virtual registers. e.g. v1024 = move r0. 75 DenseMap<unsigned, unsigned> SrcRegMap; 76 77 // DstRegMap - A map from virtual registers to physical registers which 78 // are likely targets to be coalesced to due to copies to physical 79 // registers from virtual registers. e.g. r1 = move v1024. 80 DenseMap<unsigned, unsigned> DstRegMap; 81 82 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen 83 /// during the initial walk of the machine function. 84 SmallVector<MachineInstr*, 16> RegSequences; 85 86 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI, 87 unsigned Reg, 88 MachineBasicBlock::iterator OldPos); 89 90 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC, 91 MachineInstr *MI, MachineInstr *DefMI, 92 MachineBasicBlock *MBB, unsigned Loc); 93 94 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist, 95 unsigned &LastDef); 96 97 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB, 98 unsigned Dist); 99 100 bool isProfitableToCommute(unsigned regB, unsigned regC, 101 MachineInstr *MI, MachineBasicBlock *MBB, 102 unsigned Dist); 103 104 bool CommuteInstruction(MachineBasicBlock::iterator &mi, 105 MachineFunction::iterator &mbbi, 106 unsigned RegB, unsigned RegC, unsigned Dist); 107 108 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB); 109 110 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 111 MachineBasicBlock::iterator &nmi, 112 MachineFunction::iterator &mbbi, 113 unsigned RegA, unsigned RegB, unsigned Dist); 114 115 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill; 116 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 117 SmallVector<NewKill, 4> &NewKills, 118 MachineBasicBlock *MBB, unsigned Dist); 119 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 120 MachineBasicBlock::iterator &nmi, 121 MachineFunction::iterator &mbbi, unsigned Dist); 122 123 bool TryInstructionTransform(MachineBasicBlock::iterator &mi, 124 MachineBasicBlock::iterator &nmi, 125 MachineFunction::iterator &mbbi, 126 unsigned SrcIdx, unsigned DstIdx, 127 unsigned Dist, 128 SmallPtrSet<MachineInstr*, 8> &Processed); 129 130 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB, 131 SmallPtrSet<MachineInstr*, 8> &Processed); 132 133 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB, 134 SmallPtrSet<MachineInstr*, 8> &Processed); 135 136 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg); 137 138 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 139 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as 140 /// sub-register references of the register defined by REG_SEQUENCE. 141 bool EliminateRegSequences(); 142 143 public: 144 static char ID; // Pass identification, replacement for typeid 145 TwoAddressInstructionPass() : MachineFunctionPass(ID) { 146 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); 147 } 148 149 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 150 AU.setPreservesCFG(); 151 AU.addRequired<AliasAnalysis>(); 152 AU.addPreserved<LiveVariables>(); 153 AU.addPreservedID(MachineLoopInfoID); 154 AU.addPreservedID(MachineDominatorsID); 155 AU.addPreservedID(PHIEliminationID); 156 MachineFunctionPass::getAnalysisUsage(AU); 157 } 158 159 /// runOnMachineFunction - Pass entry point. 160 bool runOnMachineFunction(MachineFunction&); 161 }; 162} 163 164char TwoAddressInstructionPass::ID = 0; 165INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction", 166 "Two-Address instruction pass", false, false) 167INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 168INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction", 169 "Two-Address instruction pass", false, false) 170 171char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID; 172 173/// Sink3AddrInstruction - A two-address instruction has been converted to a 174/// three-address instruction to avoid clobbering a register. Try to sink it 175/// past the instruction that would kill the above mentioned register to reduce 176/// register pressure. 177bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB, 178 MachineInstr *MI, unsigned SavedReg, 179 MachineBasicBlock::iterator OldPos) { 180 // Check if it's safe to move this instruction. 181 bool SeenStore = true; // Be conservative. 182 if (!MI->isSafeToMove(TII, AA, SeenStore)) 183 return false; 184 185 unsigned DefReg = 0; 186 SmallSet<unsigned, 4> UseRegs; 187 188 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 189 const MachineOperand &MO = MI->getOperand(i); 190 if (!MO.isReg()) 191 continue; 192 unsigned MOReg = MO.getReg(); 193 if (!MOReg) 194 continue; 195 if (MO.isUse() && MOReg != SavedReg) 196 UseRegs.insert(MO.getReg()); 197 if (!MO.isDef()) 198 continue; 199 if (MO.isImplicit()) 200 // Don't try to move it if it implicitly defines a register. 201 return false; 202 if (DefReg) 203 // For now, don't move any instructions that define multiple registers. 204 return false; 205 DefReg = MO.getReg(); 206 } 207 208 // Find the instruction that kills SavedReg. 209 MachineInstr *KillMI = NULL; 210 for (MachineRegisterInfo::use_nodbg_iterator 211 UI = MRI->use_nodbg_begin(SavedReg), 212 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 213 MachineOperand &UseMO = UI.getOperand(); 214 if (!UseMO.isKill()) 215 continue; 216 KillMI = UseMO.getParent(); 217 break; 218 } 219 220 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI) 221 return false; 222 223 // If any of the definitions are used by another instruction between the 224 // position and the kill use, then it's not safe to sink it. 225 // 226 // FIXME: This can be sped up if there is an easy way to query whether an 227 // instruction is before or after another instruction. Then we can use 228 // MachineRegisterInfo def / use instead. 229 MachineOperand *KillMO = NULL; 230 MachineBasicBlock::iterator KillPos = KillMI; 231 ++KillPos; 232 233 unsigned NumVisited = 0; 234 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) { 235 MachineInstr *OtherMI = I; 236 // DBG_VALUE cannot be counted against the limit. 237 if (OtherMI->isDebugValue()) 238 continue; 239 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. 240 return false; 241 ++NumVisited; 242 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { 243 MachineOperand &MO = OtherMI->getOperand(i); 244 if (!MO.isReg()) 245 continue; 246 unsigned MOReg = MO.getReg(); 247 if (!MOReg) 248 continue; 249 if (DefReg == MOReg) 250 return false; 251 252 if (MO.isKill()) { 253 if (OtherMI == KillMI && MOReg == SavedReg) 254 // Save the operand that kills the register. We want to unset the kill 255 // marker if we can sink MI past it. 256 KillMO = &MO; 257 else if (UseRegs.count(MOReg)) 258 // One of the uses is killed before the destination. 259 return false; 260 } 261 } 262 } 263 264 // Update kill and LV information. 265 KillMO->setIsKill(false); 266 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 267 KillMO->setIsKill(true); 268 269 if (LV) 270 LV->replaceKillInstruction(SavedReg, KillMI, MI); 271 272 // Move instruction to its destination. 273 MBB->remove(MI); 274 MBB->insert(KillPos, MI); 275 276 ++Num3AddrSunk; 277 return true; 278} 279 280/// isTwoAddrUse - Return true if the specified MI is using the specified 281/// register as a two-address operand. 282static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { 283 const TargetInstrDesc &TID = UseMI->getDesc(); 284 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 285 MachineOperand &MO = UseMI->getOperand(i); 286 if (MO.isReg() && MO.getReg() == Reg && 287 (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) 288 // Earlier use is a two-address one. 289 return true; 290 } 291 return false; 292} 293 294/// isProfitableToReMat - Return true if the heuristics determines it is likely 295/// to be profitable to re-materialize the definition of Reg rather than copy 296/// the register. 297bool 298TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg, 299 const TargetRegisterClass *RC, 300 MachineInstr *MI, MachineInstr *DefMI, 301 MachineBasicBlock *MBB, unsigned Loc) { 302 bool OtherUse = false; 303 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg), 304 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 305 MachineOperand &UseMO = UI.getOperand(); 306 MachineInstr *UseMI = UseMO.getParent(); 307 MachineBasicBlock *UseMBB = UseMI->getParent(); 308 if (UseMBB == MBB) { 309 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 310 if (DI != DistanceMap.end() && DI->second == Loc) 311 continue; // Current use. 312 OtherUse = true; 313 // There is at least one other use in the MBB that will clobber the 314 // register. 315 if (isTwoAddrUse(UseMI, Reg)) 316 return true; 317 } 318 } 319 320 // If other uses in MBB are not two-address uses, then don't remat. 321 if (OtherUse) 322 return false; 323 324 // No other uses in the same block, remat if it's defined in the same 325 // block so it does not unnecessarily extend the live range. 326 return MBB == DefMI->getParent(); 327} 328 329/// NoUseAfterLastDef - Return true if there are no intervening uses between the 330/// last instruction in the MBB that defines the specified register and the 331/// two-address instruction which is being processed. It also returns the last 332/// def location by reference 333bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg, 334 MachineBasicBlock *MBB, unsigned Dist, 335 unsigned &LastDef) { 336 LastDef = 0; 337 unsigned LastUse = Dist; 338 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 339 E = MRI->reg_end(); I != E; ++I) { 340 MachineOperand &MO = I.getOperand(); 341 MachineInstr *MI = MO.getParent(); 342 if (MI->getParent() != MBB || MI->isDebugValue()) 343 continue; 344 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 345 if (DI == DistanceMap.end()) 346 continue; 347 if (MO.isUse() && DI->second < LastUse) 348 LastUse = DI->second; 349 if (MO.isDef() && DI->second > LastDef) 350 LastDef = DI->second; 351 } 352 353 return !(LastUse > LastDef && LastUse < Dist); 354} 355 356MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg, 357 MachineBasicBlock *MBB, 358 unsigned Dist) { 359 unsigned LastUseDist = 0; 360 MachineInstr *LastUse = 0; 361 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 362 E = MRI->reg_end(); I != E; ++I) { 363 MachineOperand &MO = I.getOperand(); 364 MachineInstr *MI = MO.getParent(); 365 if (MI->getParent() != MBB || MI->isDebugValue()) 366 continue; 367 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI); 368 if (DI == DistanceMap.end()) 369 continue; 370 if (DI->second >= Dist) 371 continue; 372 373 if (MO.isUse() && DI->second > LastUseDist) { 374 LastUse = DI->first; 375 LastUseDist = DI->second; 376 } 377 } 378 return LastUse; 379} 380 381/// isCopyToReg - Return true if the specified MI is a copy instruction or 382/// a extract_subreg instruction. It also returns the source and destination 383/// registers and whether they are physical registers by reference. 384static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, 385 unsigned &SrcReg, unsigned &DstReg, 386 bool &IsSrcPhys, bool &IsDstPhys) { 387 SrcReg = 0; 388 DstReg = 0; 389 if (MI.isCopy()) { 390 DstReg = MI.getOperand(0).getReg(); 391 SrcReg = MI.getOperand(1).getReg(); 392 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { 393 DstReg = MI.getOperand(0).getReg(); 394 SrcReg = MI.getOperand(2).getReg(); 395 } else 396 return false; 397 398 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 399 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 400 return true; 401} 402 403/// isKilled - Test if the given register value, which is used by the given 404/// instruction, is killed by the given instruction. This looks through 405/// coalescable copies to see if the original value is potentially not killed. 406/// 407/// For example, in this code: 408/// 409/// %reg1034 = copy %reg1024 410/// %reg1035 = copy %reg1025<kill> 411/// %reg1036 = add %reg1034<kill>, %reg1035<kill> 412/// 413/// %reg1034 is not considered to be killed, since it is copied from a 414/// register which is not killed. Treating it as not killed lets the 415/// normal heuristics commute the (two-address) add, which lets 416/// coalescing eliminate the extra copy. 417/// 418static bool isKilled(MachineInstr &MI, unsigned Reg, 419 const MachineRegisterInfo *MRI, 420 const TargetInstrInfo *TII) { 421 MachineInstr *DefMI = &MI; 422 for (;;) { 423 if (!DefMI->killsRegister(Reg)) 424 return false; 425 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 426 return true; 427 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg); 428 // If there are multiple defs, we can't do a simple analysis, so just 429 // go with what the kill flag says. 430 if (llvm::next(Begin) != MRI->def_end()) 431 return true; 432 DefMI = &*Begin; 433 bool IsSrcPhys, IsDstPhys; 434 unsigned SrcReg, DstReg; 435 // If the def is something other than a copy, then it isn't going to 436 // be coalesced, so follow the kill flag. 437 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 438 return true; 439 Reg = SrcReg; 440 } 441} 442 443/// isTwoAddrUse - Return true if the specified MI uses the specified register 444/// as a two-address use. If so, return the destination register by reference. 445static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { 446 const TargetInstrDesc &TID = MI.getDesc(); 447 unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands(); 448 for (unsigned i = 0; i != NumOps; ++i) { 449 const MachineOperand &MO = MI.getOperand(i); 450 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 451 continue; 452 unsigned ti; 453 if (MI.isRegTiedToDefOperand(i, &ti)) { 454 DstReg = MI.getOperand(ti).getReg(); 455 return true; 456 } 457 } 458 return false; 459} 460 461/// findOnlyInterestingUse - Given a register, if has a single in-basic block 462/// use, return the use instruction if it's a copy or a two-address use. 463static 464MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, 465 MachineRegisterInfo *MRI, 466 const TargetInstrInfo *TII, 467 bool &IsCopy, 468 unsigned &DstReg, bool &IsDstPhys) { 469 if (!MRI->hasOneNonDBGUse(Reg)) 470 // None or more than one use. 471 return 0; 472 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg); 473 if (UseMI.getParent() != MBB) 474 return 0; 475 unsigned SrcReg; 476 bool IsSrcPhys; 477 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 478 IsCopy = true; 479 return &UseMI; 480 } 481 IsDstPhys = false; 482 if (isTwoAddrUse(UseMI, Reg, DstReg)) { 483 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 484 return &UseMI; 485 } 486 return 0; 487} 488 489/// getMappedReg - Return the physical register the specified virtual register 490/// might be mapped to. 491static unsigned 492getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) { 493 while (TargetRegisterInfo::isVirtualRegister(Reg)) { 494 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg); 495 if (SI == RegMap.end()) 496 return 0; 497 Reg = SI->second; 498 } 499 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 500 return Reg; 501 return 0; 502} 503 504/// regsAreCompatible - Return true if the two registers are equal or aliased. 505/// 506static bool 507regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { 508 if (RegA == RegB) 509 return true; 510 if (!RegA || !RegB) 511 return false; 512 return TRI->regsOverlap(RegA, RegB); 513} 514 515 516/// isProfitableToReMat - Return true if it's potentially profitable to commute 517/// the two-address instruction that's being processed. 518bool 519TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC, 520 MachineInstr *MI, MachineBasicBlock *MBB, 521 unsigned Dist) { 522 // Determine if it's profitable to commute this two address instruction. In 523 // general, we want no uses between this instruction and the definition of 524 // the two-address register. 525 // e.g. 526 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 527 // %reg1029<def> = MOV8rr %reg1028 528 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 529 // insert => %reg1030<def> = MOV8rr %reg1028 530 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 531 // In this case, it might not be possible to coalesce the second MOV8rr 532 // instruction if the first one is coalesced. So it would be profitable to 533 // commute it: 534 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 535 // %reg1029<def> = MOV8rr %reg1028 536 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> 537 // insert => %reg1030<def> = MOV8rr %reg1029 538 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> 539 540 if (!MI->killsRegister(regC)) 541 return false; 542 543 // Ok, we have something like: 544 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> 545 // let's see if it's worth commuting it. 546 547 // Look for situations like this: 548 // %reg1024<def> = MOV r1 549 // %reg1025<def> = MOV r0 550 // %reg1026<def> = ADD %reg1024, %reg1025 551 // r0 = MOV %reg1026 552 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy. 553 unsigned FromRegB = getMappedReg(regB, SrcRegMap); 554 unsigned FromRegC = getMappedReg(regC, SrcRegMap); 555 unsigned ToRegB = getMappedReg(regB, DstRegMap); 556 unsigned ToRegC = getMappedReg(regC, DstRegMap); 557 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) && 558 ((!FromRegC && !ToRegC) || 559 regsAreCompatible(FromRegB, ToRegC, TRI) || 560 regsAreCompatible(FromRegC, ToRegB, TRI))) 561 return true; 562 563 // If there is a use of regC between its last def (could be livein) and this 564 // instruction, then bail. 565 unsigned LastDefC = 0; 566 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC)) 567 return false; 568 569 // If there is a use of regB between its last def (could be livein) and this 570 // instruction, then go ahead and make this transformation. 571 unsigned LastDefB = 0; 572 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB)) 573 return true; 574 575 // Since there are no intervening uses for both registers, then commute 576 // if the def of regC is closer. Its live interval is shorter. 577 return LastDefB && LastDefC && LastDefC > LastDefB; 578} 579 580/// CommuteInstruction - Commute a two-address instruction and update the basic 581/// block, distance map, and live variables if needed. Return true if it is 582/// successful. 583bool 584TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi, 585 MachineFunction::iterator &mbbi, 586 unsigned RegB, unsigned RegC, unsigned Dist) { 587 MachineInstr *MI = mi; 588 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); 589 MachineInstr *NewMI = TII->commuteInstruction(MI); 590 591 if (NewMI == 0) { 592 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); 593 return false; 594 } 595 596 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI); 597 // If the instruction changed to commute it, update livevar. 598 if (NewMI != MI) { 599 if (LV) 600 // Update live variables 601 LV->replaceKillInstruction(RegC, MI, NewMI); 602 603 mbbi->insert(mi, NewMI); // Insert the new inst 604 mbbi->erase(mi); // Nuke the old inst. 605 mi = NewMI; 606 DistanceMap.insert(std::make_pair(NewMI, Dist)); 607 } 608 609 // Update source register map. 610 unsigned FromRegC = getMappedReg(RegC, SrcRegMap); 611 if (FromRegC) { 612 unsigned RegA = MI->getOperand(0).getReg(); 613 SrcRegMap[RegA] = FromRegC; 614 } 615 616 return true; 617} 618 619/// isProfitableToConv3Addr - Return true if it is profitable to convert the 620/// given 2-address instruction to a 3-address one. 621bool 622TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ 623 // Look for situations like this: 624 // %reg1024<def> = MOV r1 625 // %reg1025<def> = MOV r0 626 // %reg1026<def> = ADD %reg1024, %reg1025 627 // r2 = MOV %reg1026 628 // Turn ADD into a 3-address instruction to avoid a copy. 629 unsigned FromRegB = getMappedReg(RegB, SrcRegMap); 630 if (!FromRegB) 631 return false; 632 unsigned ToRegA = getMappedReg(RegA, DstRegMap); 633 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); 634} 635 636/// ConvertInstTo3Addr - Convert the specified two-address instruction into a 637/// three address one. Return true if this transformation was successful. 638bool 639TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi, 640 MachineBasicBlock::iterator &nmi, 641 MachineFunction::iterator &mbbi, 642 unsigned RegA, unsigned RegB, 643 unsigned Dist) { 644 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV); 645 if (NewMI) { 646 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi); 647 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI); 648 bool Sunk = false; 649 650 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 651 // FIXME: Temporary workaround. If the new instruction doesn't 652 // uses RegB, convertToThreeAddress must have created more 653 // then one instruction. 654 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi); 655 656 mbbi->erase(mi); // Nuke the old inst. 657 658 if (!Sunk) { 659 DistanceMap.insert(std::make_pair(NewMI, Dist)); 660 mi = NewMI; 661 nmi = llvm::next(mi); 662 } 663 664 // Update source and destination register maps. 665 SrcRegMap.erase(RegA); 666 DstRegMap.erase(RegB); 667 return true; 668 } 669 670 return false; 671} 672 673/// ScanUses - Scan forward recursively for only uses, update maps if the use 674/// is a copy or a two-address instruction. 675void 676TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB, 677 SmallPtrSet<MachineInstr*, 8> &Processed) { 678 SmallVector<unsigned, 4> VirtRegPairs; 679 bool IsDstPhys; 680 bool IsCopy = false; 681 unsigned NewReg = 0; 682 unsigned Reg = DstReg; 683 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy, 684 NewReg, IsDstPhys)) { 685 if (IsCopy && !Processed.insert(UseMI)) 686 break; 687 688 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI); 689 if (DI != DistanceMap.end()) 690 // Earlier in the same MBB.Reached via a back edge. 691 break; 692 693 if (IsDstPhys) { 694 VirtRegPairs.push_back(NewReg); 695 break; 696 } 697 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second; 698 if (!isNew) 699 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!"); 700 VirtRegPairs.push_back(NewReg); 701 Reg = NewReg; 702 } 703 704 if (!VirtRegPairs.empty()) { 705 unsigned ToReg = VirtRegPairs.back(); 706 VirtRegPairs.pop_back(); 707 while (!VirtRegPairs.empty()) { 708 unsigned FromReg = VirtRegPairs.back(); 709 VirtRegPairs.pop_back(); 710 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second; 711 if (!isNew) 712 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!"); 713 ToReg = FromReg; 714 } 715 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second; 716 if (!isNew) 717 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!"); 718 } 719} 720 721/// ProcessCopy - If the specified instruction is not yet processed, process it 722/// if it's a copy. For a copy instruction, we find the physical registers the 723/// source and destination registers might be mapped to. These are kept in 724/// point-to maps used to determine future optimizations. e.g. 725/// v1024 = mov r0 726/// v1025 = mov r1 727/// v1026 = add v1024, v1025 728/// r1 = mov r1026 729/// If 'add' is a two-address instruction, v1024, v1026 are both potentially 730/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is 731/// potentially joined with r1 on the output side. It's worthwhile to commute 732/// 'add' to eliminate a copy. 733void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI, 734 MachineBasicBlock *MBB, 735 SmallPtrSet<MachineInstr*, 8> &Processed) { 736 if (Processed.count(MI)) 737 return; 738 739 bool IsSrcPhys, IsDstPhys; 740 unsigned SrcReg, DstReg; 741 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 742 return; 743 744 if (IsDstPhys && !IsSrcPhys) 745 DstRegMap.insert(std::make_pair(SrcReg, DstReg)); 746 else if (!IsDstPhys && IsSrcPhys) { 747 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second; 748 if (!isNew) 749 assert(SrcRegMap[DstReg] == SrcReg && 750 "Can't map to two src physical registers!"); 751 752 ScanUses(DstReg, MBB, Processed); 753 } 754 755 Processed.insert(MI); 756 return; 757} 758 759/// isSafeToDelete - If the specified instruction does not produce any side 760/// effects and all of its defs are dead, then it's safe to delete. 761static bool isSafeToDelete(MachineInstr *MI, 762 const TargetInstrInfo *TII, 763 SmallVector<unsigned, 4> &Kills) { 764 const TargetInstrDesc &TID = MI->getDesc(); 765 if (TID.mayStore() || TID.isCall()) 766 return false; 767 if (TID.isTerminator() || MI->hasUnmodeledSideEffects()) 768 return false; 769 770 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 771 MachineOperand &MO = MI->getOperand(i); 772 if (!MO.isReg()) 773 continue; 774 if (MO.isDef() && !MO.isDead()) 775 return false; 776 if (MO.isUse() && MO.isKill()) 777 Kills.push_back(MO.getReg()); 778 } 779 return true; 780} 781 782/// canUpdateDeletedKills - Check if all the registers listed in Kills are 783/// killed by instructions in MBB preceding the current instruction at 784/// position Dist. If so, return true and record information about the 785/// preceding kills in NewKills. 786bool TwoAddressInstructionPass:: 787canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills, 788 SmallVector<NewKill, 4> &NewKills, 789 MachineBasicBlock *MBB, unsigned Dist) { 790 while (!Kills.empty()) { 791 unsigned Kill = Kills.back(); 792 Kills.pop_back(); 793 if (TargetRegisterInfo::isPhysicalRegister(Kill)) 794 return false; 795 796 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist); 797 if (!LastKill) 798 return false; 799 800 bool isModRef = LastKill->definesRegister(Kill); 801 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef), 802 LastKill)); 803 } 804 return true; 805} 806 807/// DeleteUnusedInstr - If an instruction with a tied register operand can 808/// be safely deleted, just delete it. 809bool 810TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi, 811 MachineBasicBlock::iterator &nmi, 812 MachineFunction::iterator &mbbi, 813 unsigned Dist) { 814 // Check if the instruction has no side effects and if all its defs are dead. 815 SmallVector<unsigned, 4> Kills; 816 if (!isSafeToDelete(mi, TII, Kills)) 817 return false; 818 819 // If this instruction kills some virtual registers, we need to 820 // update the kill information. If it's not possible to do so, 821 // then bail out. 822 SmallVector<NewKill, 4> NewKills; 823 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist)) 824 return false; 825 826 if (LV) { 827 while (!NewKills.empty()) { 828 MachineInstr *NewKill = NewKills.back().second; 829 unsigned Kill = NewKills.back().first.first; 830 bool isDead = NewKills.back().first.second; 831 NewKills.pop_back(); 832 if (LV->removeVirtualRegisterKilled(Kill, mi)) { 833 if (isDead) 834 LV->addVirtualRegisterDead(Kill, NewKill); 835 else 836 LV->addVirtualRegisterKilled(Kill, NewKill); 837 } 838 } 839 } 840 841 mbbi->erase(mi); // Nuke the old inst. 842 mi = nmi; 843 return true; 844} 845 846/// TryInstructionTransform - For the case where an instruction has a single 847/// pair of tied register operands, attempt some transformations that may 848/// either eliminate the tied operands or improve the opportunities for 849/// coalescing away the register copy. Returns true if the tied operands 850/// are eliminated altogether. 851bool TwoAddressInstructionPass:: 852TryInstructionTransform(MachineBasicBlock::iterator &mi, 853 MachineBasicBlock::iterator &nmi, 854 MachineFunction::iterator &mbbi, 855 unsigned SrcIdx, unsigned DstIdx, unsigned Dist, 856 SmallPtrSet<MachineInstr*, 8> &Processed) { 857 const TargetInstrDesc &TID = mi->getDesc(); 858 unsigned regA = mi->getOperand(DstIdx).getReg(); 859 unsigned regB = mi->getOperand(SrcIdx).getReg(); 860 861 assert(TargetRegisterInfo::isVirtualRegister(regB) && 862 "cannot make instruction into two-address form"); 863 864 // If regA is dead and the instruction can be deleted, just delete 865 // it so it doesn't clobber regB. 866 bool regBKilled = isKilled(*mi, regB, MRI, TII); 867 if (!regBKilled && mi->getOperand(DstIdx).isDead() && 868 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) { 869 ++NumDeletes; 870 return true; // Done with this instruction. 871 } 872 873 // Check if it is profitable to commute the operands. 874 unsigned SrcOp1, SrcOp2; 875 unsigned regC = 0; 876 unsigned regCIdx = ~0U; 877 bool TryCommute = false; 878 bool AggressiveCommute = false; 879 if (TID.isCommutable() && mi->getNumOperands() >= 3 && 880 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) { 881 if (SrcIdx == SrcOp1) 882 regCIdx = SrcOp2; 883 else if (SrcIdx == SrcOp2) 884 regCIdx = SrcOp1; 885 886 if (regCIdx != ~0U) { 887 regC = mi->getOperand(regCIdx).getReg(); 888 if (!regBKilled && isKilled(*mi, regC, MRI, TII)) 889 // If C dies but B does not, swap the B and C operands. 890 // This makes the live ranges of A and C joinable. 891 TryCommute = true; 892 else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) { 893 TryCommute = true; 894 AggressiveCommute = true; 895 } 896 } 897 } 898 899 // If it's profitable to commute, try to do so. 900 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) { 901 ++NumCommuted; 902 if (AggressiveCommute) 903 ++NumAggrCommuted; 904 return false; 905 } 906 907 if (TargetRegisterInfo::isVirtualRegister(regA)) 908 ScanUses(regA, &*mbbi, Processed); 909 910 if (TID.isConvertibleTo3Addr()) { 911 // This instruction is potentially convertible to a true 912 // three-address instruction. Check if it is profitable. 913 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { 914 // Try to convert it. 915 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) { 916 ++NumConvertedTo3Addr; 917 return true; // Done with this instruction. 918 } 919 } 920 } 921 922 // If this is an instruction with a load folded into it, try unfolding 923 // the load, e.g. avoid this: 924 // movq %rdx, %rcx 925 // addq (%rax), %rcx 926 // in favor of this: 927 // movq (%rax), %rcx 928 // addq %rdx, %rcx 929 // because it's preferable to schedule a load than a register copy. 930 if (TID.mayLoad() && !regBKilled) { 931 // Determine if a load can be unfolded. 932 unsigned LoadRegIndex; 933 unsigned NewOpc = 934 TII->getOpcodeAfterMemoryUnfold(mi->getOpcode(), 935 /*UnfoldLoad=*/true, 936 /*UnfoldStore=*/false, 937 &LoadRegIndex); 938 if (NewOpc != 0) { 939 const TargetInstrDesc &UnfoldTID = TII->get(NewOpc); 940 if (UnfoldTID.getNumDefs() == 1) { 941 MachineFunction &MF = *mbbi->getParent(); 942 943 // Unfold the load. 944 DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi); 945 const TargetRegisterClass *RC = 946 TII->getRegClass(UnfoldTID, LoadRegIndex, TRI); 947 unsigned Reg = MRI->createVirtualRegister(RC); 948 SmallVector<MachineInstr *, 2> NewMIs; 949 if (!TII->unfoldMemoryOperand(MF, mi, Reg, 950 /*UnfoldLoad=*/true,/*UnfoldStore=*/false, 951 NewMIs)) { 952 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 953 return false; 954 } 955 assert(NewMIs.size() == 2 && 956 "Unfolded a load into multiple instructions!"); 957 // The load was previously folded, so this is the only use. 958 NewMIs[1]->addRegisterKilled(Reg, TRI); 959 960 // Tentatively insert the instructions into the block so that they 961 // look "normal" to the transformation logic. 962 mbbi->insert(mi, NewMIs[0]); 963 mbbi->insert(mi, NewMIs[1]); 964 965 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] 966 << "2addr: NEW INST: " << *NewMIs[1]); 967 968 // Transform the instruction, now that it no longer has a load. 969 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); 970 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); 971 MachineBasicBlock::iterator NewMI = NewMIs[1]; 972 bool TransformSuccess = 973 TryInstructionTransform(NewMI, mi, mbbi, 974 NewSrcIdx, NewDstIdx, Dist, Processed); 975 if (TransformSuccess || 976 NewMIs[1]->getOperand(NewSrcIdx).isKill()) { 977 // Success, or at least we made an improvement. Keep the unfolded 978 // instructions and discard the original. 979 if (LV) { 980 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 981 MachineOperand &MO = mi->getOperand(i); 982 if (MO.isReg() && 983 TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 984 if (MO.isUse()) { 985 if (MO.isKill()) { 986 if (NewMIs[0]->killsRegister(MO.getReg())) 987 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]); 988 else { 989 assert(NewMIs[1]->killsRegister(MO.getReg()) && 990 "Kill missing after load unfold!"); 991 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]); 992 } 993 } 994 } else if (LV->removeVirtualRegisterDead(MO.getReg(), mi)) { 995 if (NewMIs[1]->registerDefIsDead(MO.getReg())) 996 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]); 997 else { 998 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && 999 "Dead flag missing after load unfold!"); 1000 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]); 1001 } 1002 } 1003 } 1004 } 1005 LV->addVirtualRegisterKilled(Reg, NewMIs[1]); 1006 } 1007 mi->eraseFromParent(); 1008 mi = NewMIs[1]; 1009 if (TransformSuccess) 1010 return true; 1011 } else { 1012 // Transforming didn't eliminate the tie and didn't lead to an 1013 // improvement. Clean up the unfolded instructions and keep the 1014 // original. 1015 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); 1016 NewMIs[0]->eraseFromParent(); 1017 NewMIs[1]->eraseFromParent(); 1018 } 1019 } 1020 } 1021 } 1022 1023 return false; 1024} 1025 1026/// runOnMachineFunction - Reduce two-address instructions to two operands. 1027/// 1028bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { 1029 DEBUG(dbgs() << "Machine Function\n"); 1030 const TargetMachine &TM = MF.getTarget(); 1031 MRI = &MF.getRegInfo(); 1032 TII = TM.getInstrInfo(); 1033 TRI = TM.getRegisterInfo(); 1034 LV = getAnalysisIfAvailable<LiveVariables>(); 1035 AA = &getAnalysis<AliasAnalysis>(); 1036 1037 bool MadeChange = false; 1038 1039 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n"); 1040 DEBUG(dbgs() << "********** Function: " 1041 << MF.getFunction()->getName() << '\n'); 1042 1043 // ReMatRegs - Keep track of the registers whose def's are remat'ed. 1044 BitVector ReMatRegs(MRI->getNumVirtRegs()); 1045 1046 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> > 1047 TiedOperandMap; 1048 TiedOperandMap TiedOperands(4); 1049 1050 SmallPtrSet<MachineInstr*, 8> Processed; 1051 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end(); 1052 mbbi != mbbe; ++mbbi) { 1053 unsigned Dist = 0; 1054 DistanceMap.clear(); 1055 SrcRegMap.clear(); 1056 DstRegMap.clear(); 1057 Processed.clear(); 1058 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); 1059 mi != me; ) { 1060 MachineBasicBlock::iterator nmi = llvm::next(mi); 1061 if (mi->isDebugValue()) { 1062 mi = nmi; 1063 continue; 1064 } 1065 1066 // Remember REG_SEQUENCE instructions, we'll deal with them later. 1067 if (mi->isRegSequence()) 1068 RegSequences.push_back(&*mi); 1069 1070 const TargetInstrDesc &TID = mi->getDesc(); 1071 bool FirstTied = true; 1072 1073 DistanceMap.insert(std::make_pair(mi, ++Dist)); 1074 1075 ProcessCopy(&*mi, &*mbbi, Processed); 1076 1077 // First scan through all the tied register uses in this instruction 1078 // and record a list of pairs of tied operands for each register. 1079 unsigned NumOps = mi->isInlineAsm() 1080 ? mi->getNumOperands() : TID.getNumOperands(); 1081 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { 1082 unsigned DstIdx = 0; 1083 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) 1084 continue; 1085 1086 if (FirstTied) { 1087 FirstTied = false; 1088 ++NumTwoAddressInstrs; 1089 DEBUG(dbgs() << '\t' << *mi); 1090 } 1091 1092 assert(mi->getOperand(SrcIdx).isReg() && 1093 mi->getOperand(SrcIdx).getReg() && 1094 mi->getOperand(SrcIdx).isUse() && 1095 "two address instruction invalid"); 1096 1097 unsigned regB = mi->getOperand(SrcIdx).getReg(); 1098 TiedOperands[regB].push_back(std::make_pair(SrcIdx, DstIdx)); 1099 } 1100 1101 // Now iterate over the information collected above. 1102 for (TiedOperandMap::iterator OI = TiedOperands.begin(), 1103 OE = TiedOperands.end(); OI != OE; ++OI) { 1104 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second; 1105 1106 // If the instruction has a single pair of tied operands, try some 1107 // transformations that may either eliminate the tied operands or 1108 // improve the opportunities for coalescing away the register copy. 1109 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) { 1110 unsigned SrcIdx = TiedPairs[0].first; 1111 unsigned DstIdx = TiedPairs[0].second; 1112 1113 // If the registers are already equal, nothing needs to be done. 1114 if (mi->getOperand(SrcIdx).getReg() == 1115 mi->getOperand(DstIdx).getReg()) 1116 break; // Done with this instruction. 1117 1118 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist, 1119 Processed)) 1120 break; // The tied operands have been eliminated. 1121 } 1122 1123 bool IsEarlyClobber = false; 1124 bool RemovedKillFlag = false; 1125 bool AllUsesCopied = true; 1126 unsigned LastCopiedReg = 0; 1127 unsigned regB = OI->first; 1128 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) { 1129 unsigned SrcIdx = TiedPairs[tpi].first; 1130 unsigned DstIdx = TiedPairs[tpi].second; 1131 1132 const MachineOperand &DstMO = mi->getOperand(DstIdx); 1133 unsigned regA = DstMO.getReg(); 1134 IsEarlyClobber |= DstMO.isEarlyClobber(); 1135 1136 // Grab regB from the instruction because it may have changed if the 1137 // instruction was commuted. 1138 regB = mi->getOperand(SrcIdx).getReg(); 1139 1140 if (regA == regB) { 1141 // The register is tied to multiple destinations (or else we would 1142 // not have continued this far), but this use of the register 1143 // already matches the tied destination. Leave it. 1144 AllUsesCopied = false; 1145 continue; 1146 } 1147 LastCopiedReg = regA; 1148 1149 assert(TargetRegisterInfo::isVirtualRegister(regB) && 1150 "cannot make instruction into two-address form"); 1151 1152#ifndef NDEBUG 1153 // First, verify that we don't have a use of "a" in the instruction 1154 // (a = b + a for example) because our transformation will not 1155 // work. This should never occur because we are in SSA form. 1156 for (unsigned i = 0; i != mi->getNumOperands(); ++i) 1157 assert(i == DstIdx || 1158 !mi->getOperand(i).isReg() || 1159 mi->getOperand(i).getReg() != regA); 1160#endif 1161 1162 // Emit a copy or rematerialize the definition. 1163 const TargetRegisterClass *rc = MRI->getRegClass(regB); 1164 MachineInstr *DefMI = MRI->getVRegDef(regB); 1165 // If it's safe and profitable, remat the definition instead of 1166 // copying it. 1167 if (DefMI && 1168 DefMI->getDesc().isAsCheapAsAMove() && 1169 DefMI->isSafeToReMat(TII, AA, regB) && 1170 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){ 1171 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n"); 1172 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); 1173 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); 1174 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB)); 1175 ++NumReMats; 1176 } else { 1177 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), 1178 regA).addReg(regB); 1179 } 1180 1181 MachineBasicBlock::iterator prevMI = prior(mi); 1182 // Update DistanceMap. 1183 DistanceMap.insert(std::make_pair(prevMI, Dist)); 1184 DistanceMap[mi] = ++Dist; 1185 1186 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI); 1187 1188 MachineOperand &MO = mi->getOperand(SrcIdx); 1189 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() && 1190 "inconsistent operand info for 2-reg pass"); 1191 if (MO.isKill()) { 1192 MO.setIsKill(false); 1193 RemovedKillFlag = true; 1194 } 1195 MO.setReg(regA); 1196 } 1197 1198 if (AllUsesCopied) { 1199 if (!IsEarlyClobber) { 1200 // Replace other (un-tied) uses of regB with LastCopiedReg. 1201 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1202 MachineOperand &MO = mi->getOperand(i); 1203 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1204 if (MO.isKill()) { 1205 MO.setIsKill(false); 1206 RemovedKillFlag = true; 1207 } 1208 MO.setReg(LastCopiedReg); 1209 } 1210 } 1211 } 1212 1213 // Update live variables for regB. 1214 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi)) 1215 LV->addVirtualRegisterKilled(regB, prior(mi)); 1216 1217 } else if (RemovedKillFlag) { 1218 // Some tied uses of regB matched their destination registers, so 1219 // regB is still used in this instruction, but a kill flag was 1220 // removed from a different tied use of regB, so now we need to add 1221 // a kill flag to one of the remaining uses of regB. 1222 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { 1223 MachineOperand &MO = mi->getOperand(i); 1224 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { 1225 MO.setIsKill(true); 1226 break; 1227 } 1228 } 1229 } 1230 1231 // Schedule the source copy / remat inserted to form two-address 1232 // instruction. FIXME: Does it matter the distance map may not be 1233 // accurate after it's scheduled? 1234 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI); 1235 1236 MadeChange = true; 1237 1238 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); 1239 } 1240 1241 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form. 1242 if (mi->isInsertSubreg()) { 1243 // From %reg = INSERT_SUBREG %reg, %subreg, subidx 1244 // To %reg:subidx = COPY %subreg 1245 unsigned SubIdx = mi->getOperand(3).getImm(); 1246 mi->RemoveOperand(3); 1247 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx"); 1248 mi->getOperand(0).setSubReg(SubIdx); 1249 mi->RemoveOperand(1); 1250 mi->setDesc(TII->get(TargetOpcode::COPY)); 1251 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi); 1252 } 1253 1254 // Clear TiedOperands here instead of at the top of the loop 1255 // since most instructions do not have tied operands. 1256 TiedOperands.clear(); 1257 mi = nmi; 1258 } 1259 } 1260 1261 // Some remat'ed instructions are dead. 1262 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) { 1263 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); 1264 if (MRI->use_nodbg_empty(VReg)) { 1265 MachineInstr *DefMI = MRI->getVRegDef(VReg); 1266 DefMI->eraseFromParent(); 1267 } 1268 } 1269 1270 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve 1271 // SSA form. It's now safe to de-SSA. 1272 MadeChange |= EliminateRegSequences(); 1273 1274 return MadeChange; 1275} 1276 1277static void UpdateRegSequenceSrcs(unsigned SrcReg, 1278 unsigned DstReg, unsigned SubIdx, 1279 MachineRegisterInfo *MRI, 1280 const TargetRegisterInfo &TRI) { 1281 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), 1282 RE = MRI->reg_end(); RI != RE; ) { 1283 MachineOperand &MO = RI.getOperand(); 1284 ++RI; 1285 MO.substVirtReg(DstReg, SubIdx, TRI); 1286 } 1287} 1288 1289/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are 1290/// EXTRACT_SUBREG from the same register and to the same virtual register 1291/// with different sub-register indices, attempt to combine the 1292/// EXTRACT_SUBREGs and pre-coalesce them. e.g. 1293/// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 1294/// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 1295/// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 1296/// Since D subregs 5, 6 can combine to a Q register, we can coalesce 1297/// reg1026 to reg1029. 1298void 1299TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, 1300 unsigned DstReg) { 1301 SmallSet<unsigned, 4> Seen; 1302 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) { 1303 unsigned SrcReg = Srcs[i]; 1304 if (!Seen.insert(SrcReg)) 1305 continue; 1306 1307 // Check that the instructions are all in the same basic block. 1308 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg); 1309 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg); 1310 if (SrcDefMI->getParent() != DstDefMI->getParent()) 1311 continue; 1312 1313 // If there are no other uses than copies which feed into 1314 // the reg_sequence, then we might be able to coalesce them. 1315 bool CanCoalesce = true; 1316 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices; 1317 for (MachineRegisterInfo::use_nodbg_iterator 1318 UI = MRI->use_nodbg_begin(SrcReg), 1319 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1320 MachineInstr *UseMI = &*UI; 1321 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) { 1322 CanCoalesce = false; 1323 break; 1324 } 1325 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg()); 1326 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg()); 1327 } 1328 1329 if (!CanCoalesce || SrcSubIndices.size() < 2) 1330 continue; 1331 1332 // Check that the source subregisters can be combined. 1333 std::sort(SrcSubIndices.begin(), SrcSubIndices.end()); 1334 unsigned NewSrcSubIdx = 0; 1335 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, 1336 NewSrcSubIdx)) 1337 continue; 1338 1339 // Check that the destination subregisters can also be combined. 1340 std::sort(DstSubIndices.begin(), DstSubIndices.end()); 1341 unsigned NewDstSubIdx = 0; 1342 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, 1343 NewDstSubIdx)) 1344 continue; 1345 1346 // If neither source nor destination can be combined to the full register, 1347 // just give up. This could be improved if it ever matters. 1348 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0) 1349 continue; 1350 1351 // Now that we know that all the uses are extract_subregs and that those 1352 // subregs can somehow be combined, scan all the extract_subregs again to 1353 // make sure the subregs are in the right order and can be composed. 1354 MachineInstr *SomeMI = 0; 1355 CanCoalesce = true; 1356 for (MachineRegisterInfo::use_nodbg_iterator 1357 UI = MRI->use_nodbg_begin(SrcReg), 1358 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 1359 MachineInstr *UseMI = &*UI; 1360 assert(UseMI->isCopy()); 1361 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg(); 1362 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg(); 1363 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination"); 1364 if ((NewDstSubIdx == 0 && 1365 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) || 1366 (NewSrcSubIdx == 0 && 1367 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) { 1368 CanCoalesce = false; 1369 break; 1370 } 1371 // Keep track of one of the uses. 1372 SomeMI = UseMI; 1373 } 1374 if (!CanCoalesce) 1375 continue; 1376 1377 // Insert a copy to replace the original. 1378 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI, 1379 SomeMI->getDebugLoc(), 1380 TII->get(TargetOpcode::COPY)) 1381 .addReg(DstReg, RegState::Define, NewDstSubIdx) 1382 .addReg(SrcReg, 0, NewSrcSubIdx); 1383 1384 // Remove all the old extract instructions. 1385 for (MachineRegisterInfo::use_nodbg_iterator 1386 UI = MRI->use_nodbg_begin(SrcReg), 1387 UE = MRI->use_nodbg_end(); UI != UE; ) { 1388 MachineInstr *UseMI = &*UI; 1389 ++UI; 1390 if (UseMI == CopyMI) 1391 continue; 1392 assert(UseMI->isCopy()); 1393 // Move any kills to the new copy or extract instruction. 1394 if (UseMI->getOperand(1).isKill()) { 1395 CopyMI->getOperand(1).setIsKill(); 1396 if (LV) 1397 // Update live variables 1398 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI); 1399 } 1400 UseMI->eraseFromParent(); 1401 } 1402 } 1403} 1404 1405static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq, 1406 MachineRegisterInfo *MRI) { 1407 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg), 1408 UE = MRI->use_end(); UI != UE; ++UI) { 1409 MachineInstr *UseMI = &*UI; 1410 if (UseMI != RegSeq && UseMI->isRegSequence()) 1411 return true; 1412 } 1413 return false; 1414} 1415 1416/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part 1417/// of the de-ssa process. This replaces sources of REG_SEQUENCE as 1418/// sub-register references of the register defined by REG_SEQUENCE. e.g. 1419/// 1420/// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ... 1421/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6 1422/// => 1423/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ... 1424bool TwoAddressInstructionPass::EliminateRegSequences() { 1425 if (RegSequences.empty()) 1426 return false; 1427 1428 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) { 1429 MachineInstr *MI = RegSequences[i]; 1430 unsigned DstReg = MI->getOperand(0).getReg(); 1431 if (MI->getOperand(0).getSubReg() || 1432 TargetRegisterInfo::isPhysicalRegister(DstReg) || 1433 !(MI->getNumOperands() & 1)) { 1434 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1435 llvm_unreachable(0); 1436 } 1437 1438 bool IsImpDef = true; 1439 SmallVector<unsigned, 4> RealSrcs; 1440 SmallSet<unsigned, 4> Seen; 1441 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1442 unsigned SrcReg = MI->getOperand(i).getReg(); 1443 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1444 if (MI->getOperand(i).getSubReg() || 1445 TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 1446 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); 1447 llvm_unreachable(0); 1448 } 1449 1450 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 1451 if (DefMI->isImplicitDef()) { 1452 DefMI->eraseFromParent(); 1453 continue; 1454 } 1455 IsImpDef = false; 1456 1457 // Remember COPY sources. These might be candidate for coalescing. 1458 if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg()) 1459 RealSrcs.push_back(DefMI->getOperand(1).getReg()); 1460 1461 bool isKill = MI->getOperand(i).isKill(); 1462 if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() || 1463 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) || 1464 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), 1465 MRI->getRegClass(SrcReg), SubIdx)) { 1466 // REG_SEQUENCE cannot have duplicated operands, add a copy. 1467 // Also add an copy if the source is live-in the block. We don't want 1468 // to end up with a partial-redef of a livein, e.g. 1469 // BB0: 1470 // reg1051:10<def> = 1471 // ... 1472 // BB1: 1473 // ... = reg1051:10 1474 // BB2: 1475 // reg1051:9<def> = 1476 // LiveIntervalAnalysis won't like it. 1477 // 1478 // If the REG_SEQUENCE doesn't kill its source, keeping live variables 1479 // correctly up to date becomes very difficult. Insert a copy. 1480 1481 // Defer any kill flag to the last operand using SrcReg. Otherwise, we 1482 // might insert a COPY that uses SrcReg after is was killed. 1483 if (isKill) 1484 for (unsigned j = i + 2; j < e; j += 2) 1485 if (MI->getOperand(j).getReg() == SrcReg) { 1486 MI->getOperand(j).setIsKill(); 1487 isKill = false; 1488 break; 1489 } 1490 1491 MachineBasicBlock::iterator InsertLoc = MI; 1492 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc, 1493 MI->getDebugLoc(), TII->get(TargetOpcode::COPY)) 1494 .addReg(DstReg, RegState::Define, SubIdx) 1495 .addReg(SrcReg, getKillRegState(isKill)); 1496 MI->getOperand(i).setReg(0); 1497 if (LV && isKill) 1498 LV->replaceKillInstruction(SrcReg, MI, CopyMI); 1499 DEBUG(dbgs() << "Inserted: " << *CopyMI); 1500 } 1501 } 1502 1503 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { 1504 unsigned SrcReg = MI->getOperand(i).getReg(); 1505 if (!SrcReg) continue; 1506 unsigned SubIdx = MI->getOperand(i+1).getImm(); 1507 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); 1508 } 1509 1510 if (IsImpDef) { 1511 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); 1512 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 1513 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) 1514 MI->RemoveOperand(j); 1515 } else { 1516 DEBUG(dbgs() << "Eliminated: " << *MI); 1517 MI->eraseFromParent(); 1518 } 1519 1520 // Try coalescing some EXTRACT_SUBREG instructions. This can create 1521 // INSERT_SUBREG instructions that must have <undef> flags added by 1522 // LiveIntervalAnalysis, so only run it when LiveVariables is available. 1523 if (LV) 1524 CoalesceExtSubRegs(RealSrcs, DstReg); 1525 } 1526 1527 RegSequences.clear(); 1528 return true; 1529} 1530