ARMBaseRegisterInfo.cpp revision 0f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9 
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMFrameLowering.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "MCTargetDesc/ARMAddressingModes.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameLowering.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "ARMGenRegisterInfo.inc"
44
45using namespace llvm;
46
47static cl::opt<bool>
48ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
49          cl::desc("Force use of virtual base registers for stack load/store"));
50static cl::opt<bool>
51EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
52          cl::desc("Enable pre-regalloc stack frame index allocation"));
53static cl::opt<bool>
54EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
58                                         const ARMSubtarget &sti)
59  : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
61    BasePtr(ARM::R6) {
62}
63
64const unsigned*
65ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66  return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
67}
68
69const uint32_t*
70ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
71  return (STI.isTargetIOS()) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
72}
73
74BitVector ARMBaseRegisterInfo::
75getReservedRegs(const MachineFunction &MF) const {
76  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
77
78  // FIXME: avoid re-calculating this every time.
79  BitVector Reserved(getNumRegs());
80  Reserved.set(ARM::SP);
81  Reserved.set(ARM::PC);
82  if (TFI->hasFP(MF))
83    Reserved.set(FramePtr);
84  if (hasBasePointer(MF))
85    Reserved.set(BasePtr);
86  // Some targets reserve R9.
87  if (STI.isR9Reserved())
88    Reserved.set(ARM::R9);
89  // Reserve D16-D31 if the subtarget doesn't support them.
90  if (!STI.hasVFP3() || STI.hasD16()) {
91    assert(ARM::D31 == ARM::D16 + 15);
92    for (unsigned i = 0; i != 16; ++i)
93      Reserved.set(ARM::D16 + i);
94  }
95  return Reserved;
96}
97
98bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
99                                        unsigned Reg) const {
100  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
101
102  switch (Reg) {
103  default: break;
104  case ARM::SP:
105  case ARM::PC:
106    return true;
107  case ARM::R6:
108    if (hasBasePointer(MF))
109      return true;
110    break;
111  case ARM::R7:
112  case ARM::R11:
113    if (FramePtr == Reg && TFI->hasFP(MF))
114      return true;
115    break;
116  case ARM::R9:
117    return STI.isR9Reserved();
118  }
119
120  return false;
121}
122
123bool
124ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
125                                          SmallVectorImpl<unsigned> &SubIndices,
126                                          unsigned &NewSubIdx) const {
127
128  unsigned Size = RC->getSize() * 8;
129  if (Size < 6)
130    return 0;
131
132  NewSubIdx = 0;  // Whole register.
133  unsigned NumRegs = SubIndices.size();
134  if (NumRegs == 8) {
135    // 8 D registers -> 1 QQQQ register.
136    return (Size == 512 &&
137            SubIndices[0] == ARM::dsub_0 &&
138            SubIndices[1] == ARM::dsub_1 &&
139            SubIndices[2] == ARM::dsub_2 &&
140            SubIndices[3] == ARM::dsub_3 &&
141            SubIndices[4] == ARM::dsub_4 &&
142            SubIndices[5] == ARM::dsub_5 &&
143            SubIndices[6] == ARM::dsub_6 &&
144            SubIndices[7] == ARM::dsub_7);
145  } else if (NumRegs == 4) {
146    if (SubIndices[0] == ARM::qsub_0) {
147      // 4 Q registers -> 1 QQQQ register.
148      return (Size == 512 &&
149              SubIndices[1] == ARM::qsub_1 &&
150              SubIndices[2] == ARM::qsub_2 &&
151              SubIndices[3] == ARM::qsub_3);
152    } else if (SubIndices[0] == ARM::dsub_0) {
153      // 4 D registers -> 1 QQ register.
154      if (Size >= 256 &&
155          SubIndices[1] == ARM::dsub_1 &&
156          SubIndices[2] == ARM::dsub_2 &&
157          SubIndices[3] == ARM::dsub_3) {
158        if (Size == 512)
159          NewSubIdx = ARM::qqsub_0;
160        return true;
161      }
162    } else if (SubIndices[0] == ARM::dsub_4) {
163      // 4 D registers -> 1 QQ register (2nd).
164      if (Size == 512 &&
165          SubIndices[1] == ARM::dsub_5 &&
166          SubIndices[2] == ARM::dsub_6 &&
167          SubIndices[3] == ARM::dsub_7) {
168        NewSubIdx = ARM::qqsub_1;
169        return true;
170      }
171    } else if (SubIndices[0] == ARM::ssub_0) {
172      // 4 S registers -> 1 Q register.
173      if (Size >= 128 &&
174          SubIndices[1] == ARM::ssub_1 &&
175          SubIndices[2] == ARM::ssub_2 &&
176          SubIndices[3] == ARM::ssub_3) {
177        if (Size >= 256)
178          NewSubIdx = ARM::qsub_0;
179        return true;
180      }
181    }
182  } else if (NumRegs == 2) {
183    if (SubIndices[0] == ARM::qsub_0) {
184      // 2 Q registers -> 1 QQ register.
185      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
186        if (Size == 512)
187          NewSubIdx = ARM::qqsub_0;
188        return true;
189      }
190    } else if (SubIndices[0] == ARM::qsub_2) {
191      // 2 Q registers -> 1 QQ register (2nd).
192      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
193        NewSubIdx = ARM::qqsub_1;
194        return true;
195      }
196    } else if (SubIndices[0] == ARM::dsub_0) {
197      // 2 D registers -> 1 Q register.
198      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
199        if (Size >= 256)
200          NewSubIdx = ARM::qsub_0;
201        return true;
202      }
203    } else if (SubIndices[0] == ARM::dsub_2) {
204      // 2 D registers -> 1 Q register (2nd).
205      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
206        NewSubIdx = ARM::qsub_1;
207        return true;
208      }
209    } else if (SubIndices[0] == ARM::dsub_4) {
210      // 2 D registers -> 1 Q register (3rd).
211      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
212        NewSubIdx = ARM::qsub_2;
213        return true;
214      }
215    } else if (SubIndices[0] == ARM::dsub_6) {
216      // 2 D registers -> 1 Q register (3rd).
217      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
218        NewSubIdx = ARM::qsub_3;
219        return true;
220      }
221    } else if (SubIndices[0] == ARM::ssub_0) {
222      // 2 S registers -> 1 D register.
223      if (SubIndices[1] == ARM::ssub_1) {
224        if (Size >= 128)
225          NewSubIdx = ARM::dsub_0;
226        return true;
227      }
228    } else if (SubIndices[0] == ARM::ssub_2) {
229      // 2 S registers -> 1 D register (2nd).
230      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
231        NewSubIdx = ARM::dsub_1;
232        return true;
233      }
234    }
235  }
236  return false;
237}
238
239const TargetRegisterClass*
240ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
241                                                                         const {
242  const TargetRegisterClass *Super = RC;
243  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
244  do {
245    switch (Super->getID()) {
246    case ARM::GPRRegClassID:
247    case ARM::SPRRegClassID:
248    case ARM::DPRRegClassID:
249    case ARM::QPRRegClassID:
250    case ARM::QQPRRegClassID:
251    case ARM::QQQQPRRegClassID:
252      return Super;
253    }
254    Super = *I++;
255  } while (Super);
256  return RC;
257}
258
259const TargetRegisterClass *
260ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
261  return ARM::GPRRegisterClass;
262}
263
264const TargetRegisterClass *
265ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
266  if (RC == &ARM::CCRRegClass)
267    return 0;  // Can't copy CCR registers.
268  return RC;
269}
270
271unsigned
272ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
273                                         MachineFunction &MF) const {
274  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
275
276  switch (RC->getID()) {
277  default:
278    return 0;
279  case ARM::tGPRRegClassID:
280    return TFI->hasFP(MF) ? 4 : 5;
281  case ARM::GPRRegClassID: {
282    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
283    return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
284  }
285  case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
286  case ARM::DPRRegClassID:
287    return 32 - 10;
288  }
289}
290
291/// getRawAllocationOrder - Returns the register allocation order for a
292/// specified register class with a target-dependent hint.
293ArrayRef<unsigned>
294ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
295                                           unsigned HintType, unsigned HintReg,
296                                           const MachineFunction &MF) const {
297  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
298  // Alternative register allocation orders when favoring even / odd registers
299  // of register pairs.
300
301  // No FP, R9 is available.
302  static const unsigned GPREven1[] = {
303    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
304    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
305    ARM::R9, ARM::R11
306  };
307  static const unsigned GPROdd1[] = {
308    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
309    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
310    ARM::R8, ARM::R10
311  };
312
313  // FP is R7, R9 is available.
314  static const unsigned GPREven2[] = {
315    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
316    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
317    ARM::R9, ARM::R11
318  };
319  static const unsigned GPROdd2[] = {
320    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
321    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
322    ARM::R8, ARM::R10
323  };
324
325  // FP is R11, R9 is available.
326  static const unsigned GPREven3[] = {
327    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
328    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
329    ARM::R9
330  };
331  static const unsigned GPROdd3[] = {
332    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
333    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
334    ARM::R8
335  };
336
337  // No FP, R9 is not available.
338  static const unsigned GPREven4[] = {
339    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
340    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
341    ARM::R11
342  };
343  static const unsigned GPROdd4[] = {
344    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
345    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
346    ARM::R10
347  };
348
349  // FP is R7, R9 is not available.
350  static const unsigned GPREven5[] = {
351    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
352    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
353    ARM::R11
354  };
355  static const unsigned GPROdd5[] = {
356    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
357    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
358    ARM::R10
359  };
360
361  // FP is R11, R9 is not available.
362  static const unsigned GPREven6[] = {
363    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
364    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
365  };
366  static const unsigned GPROdd6[] = {
367    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
368    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
369  };
370
371  // We only support even/odd hints for GPR and rGPR.
372  if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
373    return RC->getRawAllocationOrder(MF);
374
375  if (HintType == ARMRI::RegPairEven) {
376    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
377      // It's no longer possible to fulfill this hint. Return the default
378      // allocation order.
379      return RC->getRawAllocationOrder(MF);
380
381    if (!TFI->hasFP(MF)) {
382      if (!STI.isR9Reserved())
383        return makeArrayRef(GPREven1);
384      else
385        return makeArrayRef(GPREven4);
386    } else if (FramePtr == ARM::R7) {
387      if (!STI.isR9Reserved())
388        return makeArrayRef(GPREven2);
389      else
390        return makeArrayRef(GPREven5);
391    } else { // FramePtr == ARM::R11
392      if (!STI.isR9Reserved())
393        return makeArrayRef(GPREven3);
394      else
395        return makeArrayRef(GPREven6);
396    }
397  } else if (HintType == ARMRI::RegPairOdd) {
398    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
399      // It's no longer possible to fulfill this hint. Return the default
400      // allocation order.
401      return RC->getRawAllocationOrder(MF);
402
403    if (!TFI->hasFP(MF)) {
404      if (!STI.isR9Reserved())
405        return makeArrayRef(GPROdd1);
406      else
407        return makeArrayRef(GPROdd4);
408    } else if (FramePtr == ARM::R7) {
409      if (!STI.isR9Reserved())
410        return makeArrayRef(GPROdd2);
411      else
412        return makeArrayRef(GPROdd5);
413    } else { // FramePtr == ARM::R11
414      if (!STI.isR9Reserved())
415        return makeArrayRef(GPROdd3);
416      else
417        return makeArrayRef(GPROdd6);
418    }
419  }
420  return RC->getRawAllocationOrder(MF);
421}
422
423/// ResolveRegAllocHint - Resolves the specified register allocation hint
424/// to a physical register. Returns the physical register if it is successful.
425unsigned
426ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
427                                         const MachineFunction &MF) const {
428  if (Reg == 0 || !isPhysicalRegister(Reg))
429    return 0;
430  if (Type == 0)
431    return Reg;
432  else if (Type == (unsigned)ARMRI::RegPairOdd)
433    // Odd register.
434    return getRegisterPairOdd(Reg, MF);
435  else if (Type == (unsigned)ARMRI::RegPairEven)
436    // Even register.
437    return getRegisterPairEven(Reg, MF);
438  return 0;
439}
440
441void
442ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
443                                        MachineFunction &MF) const {
444  MachineRegisterInfo *MRI = &MF.getRegInfo();
445  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
446  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
447       Hint.first == (unsigned)ARMRI::RegPairEven) &&
448      TargetRegisterInfo::isVirtualRegister(Hint.second)) {
449    // If 'Reg' is one of the even / odd register pair and it's now changed
450    // (e.g. coalesced) into a different register. The other register of the
451    // pair allocation hint must be updated to reflect the relationship
452    // change.
453    unsigned OtherReg = Hint.second;
454    Hint = MRI->getRegAllocationHint(OtherReg);
455    if (Hint.second == Reg)
456      // Make sure the pair has not already divorced.
457      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
458  }
459}
460
461bool
462ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
463  // CortexA9 has a Write-after-write hazard for NEON registers.
464  if (!STI.isCortexA9())
465    return false;
466
467  switch (RC->getID()) {
468  case ARM::DPRRegClassID:
469  case ARM::DPR_8RegClassID:
470  case ARM::DPR_VFP2RegClassID:
471  case ARM::QPRRegClassID:
472  case ARM::QPR_8RegClassID:
473  case ARM::QPR_VFP2RegClassID:
474  case ARM::SPRRegClassID:
475  case ARM::SPR_8RegClassID:
476    // Avoid reusing S, D, and Q registers.
477    // Don't increase register pressure for QQ and QQQQ.
478    return true;
479  default:
480    return false;
481  }
482}
483
484bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
485  const MachineFrameInfo *MFI = MF.getFrameInfo();
486  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
487  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
488
489  if (!EnableBasePointer)
490    return false;
491
492  // When outgoing call frames are so large that we adjust the stack pointer
493  // around the call, we can no longer use the stack pointer to reach the
494  // emergency spill slot.
495  if (needsStackRealignment(MF) && (MFI->hasVarSizedObjects() ||
496                                    !TFI->hasReservedCallFrame(MF)))
497    return true;
498
499  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
500  // negative range for ldr/str (255), and thumb1 is positive offsets only.
501  // It's going to be better to use the SP or Base Pointer instead. When there
502  // are variable sized objects, we can't reference off of the SP, so we
503  // reserve a Base Pointer.
504  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
505    // Conservatively estimate whether the negative offset from the frame
506    // pointer will be sufficient to reach. If a function has a smallish
507    // frame, it's less likely to have lots of spills and callee saved
508    // space, so it's all more likely to be within range of the frame pointer.
509    // If it's wrong, the scavenger will still enable access to work, it just
510    // won't be optimal.
511    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
512      return false;
513    return true;
514  }
515
516  return false;
517}
518
519bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
520  const MachineFrameInfo *MFI = MF.getFrameInfo();
521  const MachineRegisterInfo *MRI = &MF.getRegInfo();
522  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
523  // We can't realign the stack if:
524  // 1. Dynamic stack realignment is explicitly disabled,
525  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
526  // 3. There are VLAs in the function and the base pointer is disabled.
527  if (!MF.getTarget().Options.RealignStack)
528    return false;
529  if (AFI->isThumb1OnlyFunction())
530    return false;
531  // Stack realignment requires a frame pointer.  If we already started
532  // register allocation with frame pointer elimination, it is too late now.
533  if (!MRI->canReserveReg(FramePtr))
534    return false;
535  // We may also need a base pointer if there are dynamic allocas.
536  if (!MFI->hasVarSizedObjects())
537    return true;
538  if (!EnableBasePointer)
539    return false;
540  // A base pointer is required and allowed.  Check that it isn't too late to
541  // reserve it.
542  return MRI->canReserveReg(BasePtr);
543}
544
545bool ARMBaseRegisterInfo::
546needsStackRealignment(const MachineFunction &MF) const {
547  const MachineFrameInfo *MFI = MF.getFrameInfo();
548  const Function *F = MF.getFunction();
549  unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
550  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
551                               F->hasFnAttr(Attribute::StackAlignment));
552
553  return requiresRealignment && canRealignStack(MF);
554}
555
556bool ARMBaseRegisterInfo::
557cannotEliminateFrame(const MachineFunction &MF) const {
558  const MachineFrameInfo *MFI = MF.getFrameInfo();
559  if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
560    return true;
561  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
562    || needsStackRealignment(MF);
563}
564
565unsigned
566ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
567  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
568
569  if (TFI->hasFP(MF))
570    return FramePtr;
571  return ARM::SP;
572}
573
574unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
575  llvm_unreachable("What is the exception register");
576}
577
578unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
579  llvm_unreachable("What is the exception handler register");
580}
581
582unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
583                                              const MachineFunction &MF) const {
584  switch (Reg) {
585  default: break;
586  // Return 0 if either register of the pair is a special register.
587  // So no R12, etc.
588  case ARM::R1: return ARM::R0;
589  case ARM::R3: return ARM::R2;
590  case ARM::R5: return ARM::R4;
591  case ARM::R7:
592    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
593      ? 0 : ARM::R6;
594  case ARM::R9: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
595  case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
596
597  case ARM::S1: return ARM::S0;
598  case ARM::S3: return ARM::S2;
599  case ARM::S5: return ARM::S4;
600  case ARM::S7: return ARM::S6;
601  case ARM::S9: return ARM::S8;
602  case ARM::S11: return ARM::S10;
603  case ARM::S13: return ARM::S12;
604  case ARM::S15: return ARM::S14;
605  case ARM::S17: return ARM::S16;
606  case ARM::S19: return ARM::S18;
607  case ARM::S21: return ARM::S20;
608  case ARM::S23: return ARM::S22;
609  case ARM::S25: return ARM::S24;
610  case ARM::S27: return ARM::S26;
611  case ARM::S29: return ARM::S28;
612  case ARM::S31: return ARM::S30;
613
614  case ARM::D1: return ARM::D0;
615  case ARM::D3: return ARM::D2;
616  case ARM::D5: return ARM::D4;
617  case ARM::D7: return ARM::D6;
618  case ARM::D9: return ARM::D8;
619  case ARM::D11: return ARM::D10;
620  case ARM::D13: return ARM::D12;
621  case ARM::D15: return ARM::D14;
622  case ARM::D17: return ARM::D16;
623  case ARM::D19: return ARM::D18;
624  case ARM::D21: return ARM::D20;
625  case ARM::D23: return ARM::D22;
626  case ARM::D25: return ARM::D24;
627  case ARM::D27: return ARM::D26;
628  case ARM::D29: return ARM::D28;
629  case ARM::D31: return ARM::D30;
630  }
631
632  return 0;
633}
634
635unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
636                                             const MachineFunction &MF) const {
637  switch (Reg) {
638  default: break;
639  // Return 0 if either register of the pair is a special register.
640  // So no R12, etc.
641  case ARM::R0: return ARM::R1;
642  case ARM::R2: return ARM::R3;
643  case ARM::R4: return ARM::R5;
644  case ARM::R6:
645    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
646      ? 0 : ARM::R7;
647  case ARM::R8: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
648  case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
649
650  case ARM::S0: return ARM::S1;
651  case ARM::S2: return ARM::S3;
652  case ARM::S4: return ARM::S5;
653  case ARM::S6: return ARM::S7;
654  case ARM::S8: return ARM::S9;
655  case ARM::S10: return ARM::S11;
656  case ARM::S12: return ARM::S13;
657  case ARM::S14: return ARM::S15;
658  case ARM::S16: return ARM::S17;
659  case ARM::S18: return ARM::S19;
660  case ARM::S20: return ARM::S21;
661  case ARM::S22: return ARM::S23;
662  case ARM::S24: return ARM::S25;
663  case ARM::S26: return ARM::S27;
664  case ARM::S28: return ARM::S29;
665  case ARM::S30: return ARM::S31;
666
667  case ARM::D0: return ARM::D1;
668  case ARM::D2: return ARM::D3;
669  case ARM::D4: return ARM::D5;
670  case ARM::D6: return ARM::D7;
671  case ARM::D8: return ARM::D9;
672  case ARM::D10: return ARM::D11;
673  case ARM::D12: return ARM::D13;
674  case ARM::D14: return ARM::D15;
675  case ARM::D16: return ARM::D17;
676  case ARM::D18: return ARM::D19;
677  case ARM::D20: return ARM::D21;
678  case ARM::D22: return ARM::D23;
679  case ARM::D24: return ARM::D25;
680  case ARM::D26: return ARM::D27;
681  case ARM::D28: return ARM::D29;
682  case ARM::D30: return ARM::D31;
683  }
684
685  return 0;
686}
687
688/// emitLoadConstPool - Emits a load from constpool to materialize the
689/// specified immediate.
690void ARMBaseRegisterInfo::
691emitLoadConstPool(MachineBasicBlock &MBB,
692                  MachineBasicBlock::iterator &MBBI,
693                  DebugLoc dl,
694                  unsigned DestReg, unsigned SubIdx, int Val,
695                  ARMCC::CondCodes Pred,
696                  unsigned PredReg, unsigned MIFlags) const {
697  MachineFunction &MF = *MBB.getParent();
698  MachineConstantPool *ConstantPool = MF.getConstantPool();
699  const Constant *C =
700        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
701  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
702
703  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
704    .addReg(DestReg, getDefRegState(true), SubIdx)
705    .addConstantPoolIndex(Idx)
706    .addImm(0).addImm(Pred).addReg(PredReg)
707    .setMIFlags(MIFlags);
708}
709
710bool ARMBaseRegisterInfo::
711requiresRegisterScavenging(const MachineFunction &MF) const {
712  return true;
713}
714
715bool ARMBaseRegisterInfo::
716requiresFrameIndexScavenging(const MachineFunction &MF) const {
717  return true;
718}
719
720bool ARMBaseRegisterInfo::
721requiresVirtualBaseRegisters(const MachineFunction &MF) const {
722  return EnableLocalStackAlloc;
723}
724
725static void
726emitSPUpdate(bool isARM,
727             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
728             DebugLoc dl, const ARMBaseInstrInfo &TII,
729             int NumBytes,
730             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
731  if (isARM)
732    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
733                            Pred, PredReg, TII);
734  else
735    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
736                           Pred, PredReg, TII);
737}
738
739
740void ARMBaseRegisterInfo::
741eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
742                              MachineBasicBlock::iterator I) const {
743  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
744  if (!TFI->hasReservedCallFrame(MF)) {
745    // If we have alloca, convert as follows:
746    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
747    // ADJCALLSTACKUP   -> add, sp, sp, amount
748    MachineInstr *Old = I;
749    DebugLoc dl = Old->getDebugLoc();
750    unsigned Amount = Old->getOperand(0).getImm();
751    if (Amount != 0) {
752      // We need to keep the stack aligned properly.  To do this, we round the
753      // amount of space needed for the outgoing arguments up to the next
754      // alignment boundary.
755      unsigned Align = TFI->getStackAlignment();
756      Amount = (Amount+Align-1)/Align*Align;
757
758      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
759      assert(!AFI->isThumb1OnlyFunction() &&
760             "This eliminateCallFramePseudoInstr does not support Thumb1!");
761      bool isARM = !AFI->isThumbFunction();
762
763      // Replace the pseudo instruction with a new instruction...
764      unsigned Opc = Old->getOpcode();
765      int PIdx = Old->findFirstPredOperandIdx();
766      ARMCC::CondCodes Pred = (PIdx == -1)
767        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
768      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
769        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
770        unsigned PredReg = Old->getOperand(2).getReg();
771        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
772      } else {
773        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
774        unsigned PredReg = Old->getOperand(3).getReg();
775        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
776        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
777      }
778    }
779  }
780  MBB.erase(I);
781}
782
783int64_t ARMBaseRegisterInfo::
784getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
785  const MCInstrDesc &Desc = MI->getDesc();
786  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
787  int64_t InstrOffs = 0;
788  int Scale = 1;
789  unsigned ImmIdx = 0;
790  switch (AddrMode) {
791  case ARMII::AddrModeT2_i8:
792  case ARMII::AddrModeT2_i12:
793  case ARMII::AddrMode_i12:
794    InstrOffs = MI->getOperand(Idx+1).getImm();
795    Scale = 1;
796    break;
797  case ARMII::AddrMode5: {
798    // VFP address mode.
799    const MachineOperand &OffOp = MI->getOperand(Idx+1);
800    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
801    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
802      InstrOffs = -InstrOffs;
803    Scale = 4;
804    break;
805  }
806  case ARMII::AddrMode2: {
807    ImmIdx = Idx+2;
808    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
809    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
810      InstrOffs = -InstrOffs;
811    break;
812  }
813  case ARMII::AddrMode3: {
814    ImmIdx = Idx+2;
815    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
816    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
817      InstrOffs = -InstrOffs;
818    break;
819  }
820  case ARMII::AddrModeT1_s: {
821    ImmIdx = Idx+1;
822    InstrOffs = MI->getOperand(ImmIdx).getImm();
823    Scale = 4;
824    break;
825  }
826  default:
827    llvm_unreachable("Unsupported addressing mode!");
828  }
829
830  return InstrOffs * Scale;
831}
832
833/// needsFrameBaseReg - Returns true if the instruction's frame index
834/// reference would be better served by a base register other than FP
835/// or SP. Used by LocalStackFrameAllocation to determine which frame index
836/// references it should create new base registers for.
837bool ARMBaseRegisterInfo::
838needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
839  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
840    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
841  }
842
843  // It's the load/store FI references that cause issues, as it can be difficult
844  // to materialize the offset if it won't fit in the literal field. Estimate
845  // based on the size of the local frame and some conservative assumptions
846  // about the rest of the stack frame (note, this is pre-regalloc, so
847  // we don't know everything for certain yet) whether this offset is likely
848  // to be out of range of the immediate. Return true if so.
849
850  // We only generate virtual base registers for loads and stores, so
851  // return false for everything else.
852  unsigned Opc = MI->getOpcode();
853  switch (Opc) {
854  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
855  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
856  case ARM::t2LDRi12: case ARM::t2LDRi8:
857  case ARM::t2STRi12: case ARM::t2STRi8:
858  case ARM::VLDRS: case ARM::VLDRD:
859  case ARM::VSTRS: case ARM::VSTRD:
860  case ARM::tSTRspi: case ARM::tLDRspi:
861    if (ForceAllBaseRegAlloc)
862      return true;
863    break;
864  default:
865    return false;
866  }
867
868  // Without a virtual base register, if the function has variable sized
869  // objects, all fixed-size local references will be via the frame pointer,
870  // Approximate the offset and see if it's legal for the instruction.
871  // Note that the incoming offset is based on the SP value at function entry,
872  // so it'll be negative.
873  MachineFunction &MF = *MI->getParent()->getParent();
874  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
875  MachineFrameInfo *MFI = MF.getFrameInfo();
876  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
877
878  // Estimate an offset from the frame pointer.
879  // Conservatively assume all callee-saved registers get pushed. R4-R6
880  // will be earlier than the FP, so we ignore those.
881  // R7, LR
882  int64_t FPOffset = Offset - 8;
883  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
884  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
885    FPOffset -= 80;
886  // Estimate an offset from the stack pointer.
887  // The incoming offset is relating to the SP at the start of the function,
888  // but when we access the local it'll be relative to the SP after local
889  // allocation, so adjust our SP-relative offset by that allocation size.
890  Offset = -Offset;
891  Offset += MFI->getLocalFrameSize();
892  // Assume that we'll have at least some spill slots allocated.
893  // FIXME: This is a total SWAG number. We should run some statistics
894  //        and pick a real one.
895  Offset += 128; // 128 bytes of spill slots
896
897  // If there is a frame pointer, try using it.
898  // The FP is only available if there is no dynamic realignment. We
899  // don't know for sure yet whether we'll need that, so we guess based
900  // on whether there are any local variables that would trigger it.
901  unsigned StackAlign = TFI->getStackAlignment();
902  if (TFI->hasFP(MF) &&
903      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
904    if (isFrameOffsetLegal(MI, FPOffset))
905      return false;
906  }
907  // If we can reference via the stack pointer, try that.
908  // FIXME: This (and the code that resolves the references) can be improved
909  //        to only disallow SP relative references in the live range of
910  //        the VLA(s). In practice, it's unclear how much difference that
911  //        would make, but it may be worth doing.
912  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
913    return false;
914
915  // The offset likely isn't legal, we want to allocate a virtual base register.
916  return true;
917}
918
919/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
920/// be a pointer to FrameIdx at the beginning of the basic block.
921void ARMBaseRegisterInfo::
922materializeFrameBaseRegister(MachineBasicBlock *MBB,
923                             unsigned BaseReg, int FrameIdx,
924                             int64_t Offset) const {
925  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
926  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
927    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
928
929  MachineBasicBlock::iterator Ins = MBB->begin();
930  DebugLoc DL;                  // Defaults to "unknown"
931  if (Ins != MBB->end())
932    DL = Ins->getDebugLoc();
933
934  const MCInstrDesc &MCID = TII.get(ADDriOpc);
935  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
936  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
937
938  MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
939    .addFrameIndex(FrameIdx).addImm(Offset));
940
941  if (!AFI->isThumb1OnlyFunction())
942    AddDefaultCC(MIB);
943}
944
945void
946ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
947                                       unsigned BaseReg, int64_t Offset) const {
948  MachineInstr &MI = *I;
949  MachineBasicBlock &MBB = *MI.getParent();
950  MachineFunction &MF = *MBB.getParent();
951  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
952  int Off = Offset; // ARM doesn't need the general 64-bit offsets
953  unsigned i = 0;
954
955  assert(!AFI->isThumb1OnlyFunction() &&
956         "This resolveFrameIndex does not support Thumb1!");
957
958  while (!MI.getOperand(i).isFI()) {
959    ++i;
960    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
961  }
962  bool Done = false;
963  if (!AFI->isThumbFunction())
964    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
965  else {
966    assert(AFI->isThumb2Function());
967    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
968  }
969  assert (Done && "Unable to resolve frame index!");
970  (void)Done;
971}
972
973bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
974                                             int64_t Offset) const {
975  const MCInstrDesc &Desc = MI->getDesc();
976  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
977  unsigned i = 0;
978
979  while (!MI->getOperand(i).isFI()) {
980    ++i;
981    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
982  }
983
984  // AddrMode4 and AddrMode6 cannot handle any offset.
985  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
986    return Offset == 0;
987
988  unsigned NumBits = 0;
989  unsigned Scale = 1;
990  bool isSigned = true;
991  switch (AddrMode) {
992  case ARMII::AddrModeT2_i8:
993  case ARMII::AddrModeT2_i12:
994    // i8 supports only negative, and i12 supports only positive, so
995    // based on Offset sign, consider the appropriate instruction
996    Scale = 1;
997    if (Offset < 0) {
998      NumBits = 8;
999      Offset = -Offset;
1000    } else {
1001      NumBits = 12;
1002    }
1003    break;
1004  case ARMII::AddrMode5:
1005    // VFP address mode.
1006    NumBits = 8;
1007    Scale = 4;
1008    break;
1009  case ARMII::AddrMode_i12:
1010  case ARMII::AddrMode2:
1011    NumBits = 12;
1012    break;
1013  case ARMII::AddrMode3:
1014    NumBits = 8;
1015    break;
1016  case ARMII::AddrModeT1_s:
1017    NumBits = 5;
1018    Scale = 4;
1019    isSigned = false;
1020    break;
1021  default:
1022    llvm_unreachable("Unsupported addressing mode!");
1023  }
1024
1025  Offset += getFrameIndexInstrOffset(MI, i);
1026  // Make sure the offset is encodable for instructions that scale the
1027  // immediate.
1028  if ((Offset & (Scale-1)) != 0)
1029    return false;
1030
1031  if (isSigned && Offset < 0)
1032    Offset = -Offset;
1033
1034  unsigned Mask = (1 << NumBits) - 1;
1035  if ((unsigned)Offset <= Mask * Scale)
1036    return true;
1037
1038  return false;
1039}
1040
1041void
1042ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1043                                         int SPAdj, RegScavenger *RS) const {
1044  unsigned i = 0;
1045  MachineInstr &MI = *II;
1046  MachineBasicBlock &MBB = *MI.getParent();
1047  MachineFunction &MF = *MBB.getParent();
1048  const ARMFrameLowering *TFI =
1049    static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1050  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1051  assert(!AFI->isThumb1OnlyFunction() &&
1052         "This eliminateFrameIndex does not support Thumb1!");
1053
1054  while (!MI.getOperand(i).isFI()) {
1055    ++i;
1056    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1057  }
1058
1059  int FrameIndex = MI.getOperand(i).getIndex();
1060  unsigned FrameReg;
1061
1062  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1063
1064  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
1065  // call frame setup/destroy instructions have already been eliminated.  That
1066  // means the stack pointer cannot be used to access the emergency spill slot
1067  // when !hasReservedCallFrame().
1068#ifndef NDEBUG
1069  if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
1070    assert(TFI->hasReservedCallFrame(MF) &&
1071           "Cannot use SP to access the emergency spill slot in "
1072           "functions without a reserved call frame");
1073    assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
1074           "Cannot use SP to access the emergency spill slot in "
1075           "functions with variable sized frame objects");
1076  }
1077#endif // NDEBUG
1078
1079  // Special handling of dbg_value instructions.
1080  if (MI.isDebugValue()) {
1081    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1082    MI.getOperand(i+1).ChangeToImmediate(Offset);
1083    return;
1084  }
1085
1086  // Modify MI as necessary to handle as much of 'Offset' as possible
1087  bool Done = false;
1088  if (!AFI->isThumbFunction())
1089    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1090  else {
1091    assert(AFI->isThumb2Function());
1092    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1093  }
1094  if (Done)
1095    return;
1096
1097  // If we get here, the immediate doesn't fit into the instruction.  We folded
1098  // as much as possible above, handle the rest, providing a register that is
1099  // SP+LargeImm.
1100  assert((Offset ||
1101          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1102          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1103         "This code isn't needed if offset already handled!");
1104
1105  unsigned ScratchReg = 0;
1106  int PIdx = MI.findFirstPredOperandIdx();
1107  ARMCC::CondCodes Pred = (PIdx == -1)
1108    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1109  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1110  if (Offset == 0)
1111    // Must be addrmode4/6.
1112    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1113  else {
1114    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1115    if (!AFI->isThumbFunction())
1116      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1117                              Offset, Pred, PredReg, TII);
1118    else {
1119      assert(AFI->isThumb2Function());
1120      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1121                             Offset, Pred, PredReg, TII);
1122    }
1123    // Update the original instruction to use the scratch register.
1124    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1125  }
1126}
1127