ARMBaseRegisterInfo.cpp revision 22c687b6421d9cc03351ddb0c7fd3d45382bc01a 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46}
47
48using namespace llvm;
49
50unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
51                                                   bool *isSPVFP) {
52  if (isSPVFP)
53    *isSPVFP = false;
54
55  using namespace ARM;
56  switch (RegEnum) {
57  default:
58    llvm_unreachable("Unknown ARM register!");
59  case R0:  case D0:  case Q0:  return 0;
60  case R1:  case D1:  case Q1:  return 1;
61  case R2:  case D2:  case Q2:  return 2;
62  case R3:  case D3:  case Q3:  return 3;
63  case R4:  case D4:  case Q4:  return 4;
64  case R5:  case D5:  case Q5:  return 5;
65  case R6:  case D6:  case Q6:  return 6;
66  case R7:  case D7:  case Q7:  return 7;
67  case R8:  case D8:  case Q8:  return 8;
68  case R9:  case D9:  case Q9:  return 9;
69  case R10: case D10: case Q10: return 10;
70  case R11: case D11: case Q11: return 11;
71  case R12: case D12: case Q12: return 12;
72  case SP:  case D13: case Q13: return 13;
73  case LR:  case D14: case Q14: return 14;
74  case PC:  case D15: case Q15: return 15;
75
76  case D16: return 16;
77  case D17: return 17;
78  case D18: return 18;
79  case D19: return 19;
80  case D20: return 20;
81  case D21: return 21;
82  case D22: return 22;
83  case D23: return 23;
84  case D24: return 24;
85  case D25: return 25;
86  case D26: return 26;
87  case D27: return 27;
88  case D28: return 28;
89  case D29: return 29;
90  case D30: return 30;
91  case D31: return 31;
92
93  case S0: case S1: case S2: case S3:
94  case S4: case S5: case S6: case S7:
95  case S8: case S9: case S10: case S11:
96  case S12: case S13: case S14: case S15:
97  case S16: case S17: case S18: case S19:
98  case S20: case S21: case S22: case S23:
99  case S24: case S25: case S26: case S27:
100  case S28: case S29: case S30: case S31: {
101    if (isSPVFP)
102      *isSPVFP = true;
103    switch (RegEnum) {
104    default: return 0; // Avoid compile time warning.
105    case S0: return 0;
106    case S1: return 1;
107    case S2: return 2;
108    case S3: return 3;
109    case S4: return 4;
110    case S5: return 5;
111    case S6: return 6;
112    case S7: return 7;
113    case S8: return 8;
114    case S9: return 9;
115    case S10: return 10;
116    case S11: return 11;
117    case S12: return 12;
118    case S13: return 13;
119    case S14: return 14;
120    case S15: return 15;
121    case S16: return 16;
122    case S17: return 17;
123    case S18: return 18;
124    case S19: return 19;
125    case S20: return 20;
126    case S21: return 21;
127    case S22: return 22;
128    case S23: return 23;
129    case S24: return 24;
130    case S25: return 25;
131    case S26: return 26;
132    case S27: return 27;
133    case S28: return 28;
134    case S29: return 29;
135    case S30: return 30;
136    case S31: return 31;
137    }
138  }
139  }
140}
141
142ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143                                         const ARMSubtarget &sti)
144  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
145    TII(tii), STI(sti),
146    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
147}
148
149const unsigned*
150ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151  static const unsigned CalleeSavedRegs[] = {
152    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
154
155    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
157    0
158  };
159
160  static const unsigned DarwinCalleeSavedRegs[] = {
161    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
162    // register.
163    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
164    ARM::R11, ARM::R10, ARM::R8,
165
166    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
168    0
169  };
170  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
171}
172
173const TargetRegisterClass* const *
174ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
175  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
176    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
177    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
179
180    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
181    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182    0
183  };
184
185  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
186    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
188    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
189
190    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
191    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192    0
193  };
194
195  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
196    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
197    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198    &ARM::GPRRegClass, &ARM::GPRRegClass,
199
200    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
201    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202    0
203  };
204
205  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
206    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
207    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
208    &ARM::GPRRegClass,  &ARM::GPRRegClass,
209
210    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
211    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212    0
213  };
214
215  if (STI.isThumb1Only()) {
216    return STI.isTargetDarwin()
217      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
218  }
219  return STI.isTargetDarwin()
220    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
221}
222
223BitVector ARMBaseRegisterInfo::
224getReservedRegs(const MachineFunction &MF) const {
225  // FIXME: avoid re-calculating this everytime.
226  BitVector Reserved(getNumRegs());
227  Reserved.set(ARM::SP);
228  Reserved.set(ARM::PC);
229  if (STI.isTargetDarwin() || hasFP(MF))
230    Reserved.set(FramePtr);
231  // Some targets reserve R9.
232  if (STI.isR9Reserved())
233    Reserved.set(ARM::R9);
234  return Reserved;
235}
236
237bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238                                        unsigned Reg) const {
239  switch (Reg) {
240  default: break;
241  case ARM::SP:
242  case ARM::PC:
243    return true;
244  case ARM::R7:
245  case ARM::R11:
246    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
247      return true;
248    break;
249  case ARM::R9:
250    return STI.isR9Reserved();
251  }
252
253  return false;
254}
255
256const TargetRegisterClass *
257ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258                                              const TargetRegisterClass *B,
259                                              unsigned SubIdx) const {
260  switch (SubIdx) {
261  default: return 0;
262  case 1:
263  case 2:
264  case 3:
265  case 4: {
266    // S sub-registers.
267    if (A->getSize() == 8) {
268      if (B == &ARM::SPR_8RegClass)
269        return &ARM::DPR_8RegClass;
270      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
271      if (A == &ARM::DPR_8RegClass)
272        return A;
273      return &ARM::DPR_VFP2RegClass;
274    }
275
276    if (A->getSize() == 16) {
277      if (B == &ARM::SPR_8RegClass)
278        return &ARM::QPR_8RegClass;
279      return &ARM::QPR_VFP2RegClass;
280    }
281
282    if (A->getSize() == 32) {
283      if (B == &ARM::SPR_8RegClass)
284        return 0;  // Do not allow coalescing!
285      return &ARM::QQPR_VFP2RegClass;
286    }
287
288    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
289    return 0;  // Do not allow coalescing!
290  }
291  case 5:
292  case 6:
293  case 7:
294  case 8: {
295    // D sub-registers.
296    if (A->getSize() == 16) {
297      if (B == &ARM::DPR_VFP2RegClass)
298        return &ARM::QPR_VFP2RegClass;
299      if (B == &ARM::DPR_8RegClass)
300        return 0;  // Do not allow coalescing!
301      return A;
302    }
303
304    if (A->getSize() == 32) {
305      if (B == &ARM::DPR_VFP2RegClass)
306        return &ARM::QQPR_VFP2RegClass;
307      if (B == &ARM::DPR_8RegClass)
308        return 0;  // Do not allow coalescing!
309      return A;
310    }
311
312    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
313    if (B != &ARM::DPRRegClass)
314      return 0;  // Do not allow coalescing!
315    return A;
316  }
317  case 9:
318  case 10:
319  case 11:
320  case 12: {
321    // D sub-registers of QQQQ registers.
322    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
323      return A;
324    return 0;  // Do not allow coalescing!
325  }
326
327  case 13:
328  case 14: {
329    // Q sub-registers.
330    if (A->getSize() == 32) {
331      if (B == &ARM::QPR_VFP2RegClass)
332        return &ARM::QQPR_VFP2RegClass;
333      if (B == &ARM::QPR_8RegClass)
334        return 0;  // Do not allow coalescing!
335      return A;
336    }
337
338    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
339    if (B == &ARM::QPRRegClass)
340      return A;
341    return 0;  // Do not allow coalescing!
342  }
343  case 15:
344  case 16: {
345    // Q sub-registers of QQQQ registers.
346    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
347      return A;
348    return 0;  // Do not allow coalescing!
349  }
350  }
351  return 0;
352}
353
354const TargetRegisterClass *
355ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
356  return ARM::GPRRegisterClass;
357}
358
359/// getAllocationOrder - Returns the register allocation order for a specified
360/// register class in the form of a pair of TargetRegisterClass iterators.
361std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
362ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
363                                        unsigned HintType, unsigned HintReg,
364                                        const MachineFunction &MF) const {
365  // Alternative register allocation orders when favoring even / odd registers
366  // of register pairs.
367
368  // No FP, R9 is available.
369  static const unsigned GPREven1[] = {
370    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
371    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
372    ARM::R9, ARM::R11
373  };
374  static const unsigned GPROdd1[] = {
375    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
376    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
377    ARM::R8, ARM::R10
378  };
379
380  // FP is R7, R9 is available.
381  static const unsigned GPREven2[] = {
382    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
383    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
384    ARM::R9, ARM::R11
385  };
386  static const unsigned GPROdd2[] = {
387    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
388    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
389    ARM::R8, ARM::R10
390  };
391
392  // FP is R11, R9 is available.
393  static const unsigned GPREven3[] = {
394    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
395    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
396    ARM::R9
397  };
398  static const unsigned GPROdd3[] = {
399    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
400    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
401    ARM::R8
402  };
403
404  // No FP, R9 is not available.
405  static const unsigned GPREven4[] = {
406    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
407    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
408    ARM::R11
409  };
410  static const unsigned GPROdd4[] = {
411    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
412    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
413    ARM::R10
414  };
415
416  // FP is R7, R9 is not available.
417  static const unsigned GPREven5[] = {
418    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
419    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
420    ARM::R11
421  };
422  static const unsigned GPROdd5[] = {
423    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
424    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
425    ARM::R10
426  };
427
428  // FP is R11, R9 is not available.
429  static const unsigned GPREven6[] = {
430    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
431    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
432  };
433  static const unsigned GPROdd6[] = {
434    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
435    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
436  };
437
438
439  if (HintType == ARMRI::RegPairEven) {
440    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
441      // It's no longer possible to fulfill this hint. Return the default
442      // allocation order.
443      return std::make_pair(RC->allocation_order_begin(MF),
444                            RC->allocation_order_end(MF));
445
446    if (!STI.isTargetDarwin() && !hasFP(MF)) {
447      if (!STI.isR9Reserved())
448        return std::make_pair(GPREven1,
449                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
450      else
451        return std::make_pair(GPREven4,
452                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
453    } else if (FramePtr == ARM::R7) {
454      if (!STI.isR9Reserved())
455        return std::make_pair(GPREven2,
456                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
457      else
458        return std::make_pair(GPREven5,
459                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
460    } else { // FramePtr == ARM::R11
461      if (!STI.isR9Reserved())
462        return std::make_pair(GPREven3,
463                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
464      else
465        return std::make_pair(GPREven6,
466                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
467    }
468  } else if (HintType == ARMRI::RegPairOdd) {
469    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
470      // It's no longer possible to fulfill this hint. Return the default
471      // allocation order.
472      return std::make_pair(RC->allocation_order_begin(MF),
473                            RC->allocation_order_end(MF));
474
475    if (!STI.isTargetDarwin() && !hasFP(MF)) {
476      if (!STI.isR9Reserved())
477        return std::make_pair(GPROdd1,
478                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
479      else
480        return std::make_pair(GPROdd4,
481                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
482    } else if (FramePtr == ARM::R7) {
483      if (!STI.isR9Reserved())
484        return std::make_pair(GPROdd2,
485                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
486      else
487        return std::make_pair(GPROdd5,
488                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
489    } else { // FramePtr == ARM::R11
490      if (!STI.isR9Reserved())
491        return std::make_pair(GPROdd3,
492                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
493      else
494        return std::make_pair(GPROdd6,
495                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
496    }
497  }
498  return std::make_pair(RC->allocation_order_begin(MF),
499                        RC->allocation_order_end(MF));
500}
501
502/// ResolveRegAllocHint - Resolves the specified register allocation hint
503/// to a physical register. Returns the physical register if it is successful.
504unsigned
505ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
506                                         const MachineFunction &MF) const {
507  if (Reg == 0 || !isPhysicalRegister(Reg))
508    return 0;
509  if (Type == 0)
510    return Reg;
511  else if (Type == (unsigned)ARMRI::RegPairOdd)
512    // Odd register.
513    return getRegisterPairOdd(Reg, MF);
514  else if (Type == (unsigned)ARMRI::RegPairEven)
515    // Even register.
516    return getRegisterPairEven(Reg, MF);
517  return 0;
518}
519
520void
521ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
522                                        MachineFunction &MF) const {
523  MachineRegisterInfo *MRI = &MF.getRegInfo();
524  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
525  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
526       Hint.first == (unsigned)ARMRI::RegPairEven) &&
527      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
528    // If 'Reg' is one of the even / odd register pair and it's now changed
529    // (e.g. coalesced) into a different register. The other register of the
530    // pair allocation hint must be updated to reflect the relationship
531    // change.
532    unsigned OtherReg = Hint.second;
533    Hint = MRI->getRegAllocationHint(OtherReg);
534    if (Hint.second == Reg)
535      // Make sure the pair has not already divorced.
536      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
537  }
538}
539
540/// hasFP - Return true if the specified function should have a dedicated frame
541/// pointer register.  This is true if the function has variable sized allocas
542/// or if frame pointer elimination is disabled.
543///
544bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
545  const MachineFrameInfo *MFI = MF.getFrameInfo();
546  return ((DisableFramePointerElim(MF) && MFI->hasCalls())||
547          needsStackRealignment(MF) ||
548          MFI->hasVarSizedObjects() ||
549          MFI->isFrameAddressTaken());
550}
551
552bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
553  const MachineFrameInfo *MFI = MF.getFrameInfo();
554  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
555  return (RealignStack &&
556          !AFI->isThumb1OnlyFunction() &&
557          !MFI->hasVarSizedObjects());
558}
559
560bool ARMBaseRegisterInfo::
561needsStackRealignment(const MachineFunction &MF) const {
562  const MachineFrameInfo *MFI = MF.getFrameInfo();
563  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
564  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
565  return (RealignStack &&
566          !AFI->isThumb1OnlyFunction() &&
567          (MFI->getMaxAlignment() > StackAlign) &&
568          !MFI->hasVarSizedObjects());
569}
570
571bool ARMBaseRegisterInfo::
572cannotEliminateFrame(const MachineFunction &MF) const {
573  const MachineFrameInfo *MFI = MF.getFrameInfo();
574  if (DisableFramePointerElim(MF) && MFI->hasCalls())
575    return true;
576  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
577    || needsStackRealignment(MF);
578}
579
580/// estimateStackSize - Estimate and return the size of the frame.
581static unsigned estimateStackSize(MachineFunction &MF) {
582  const MachineFrameInfo *FFI = MF.getFrameInfo();
583  int Offset = 0;
584  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
585    int FixedOff = -FFI->getObjectOffset(i);
586    if (FixedOff > Offset) Offset = FixedOff;
587  }
588  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
589    if (FFI->isDeadObjectIndex(i))
590      continue;
591    Offset += FFI->getObjectSize(i);
592    unsigned Align = FFI->getObjectAlignment(i);
593    // Adjust to alignment boundary
594    Offset = (Offset+Align-1)/Align*Align;
595  }
596  return (unsigned)Offset;
597}
598
599/// estimateRSStackSizeLimit - Look at each instruction that references stack
600/// frames and return the stack size limit beyond which some of these
601/// instructions will require a scratch register during their expansion later.
602unsigned
603ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
604  unsigned Limit = (1 << 12) - 1;
605  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
606    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
607         I != E; ++I) {
608      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
609        if (!I->getOperand(i).isFI()) continue;
610
611        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
612        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
613        if (AddrMode == ARMII::AddrMode3 ||
614            AddrMode == ARMII::AddrModeT2_i8)
615          return (1 << 8) - 1;
616
617        if (AddrMode == ARMII::AddrMode5 ||
618            AddrMode == ARMII::AddrModeT2_i8s4)
619          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
620
621        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
622          // When the stack offset is negative, we will end up using
623          // the i8 instructions instead.
624          return (1 << 8) - 1;
625
626        if (AddrMode == ARMII::AddrMode6)
627          return 0;
628        break; // At most one FI per instruction
629      }
630    }
631  }
632
633  return Limit;
634}
635
636void
637ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
638                                                       RegScavenger *RS) const {
639  // This tells PEI to spill the FP as if it is any other callee-save register
640  // to take advantage the eliminateFrameIndex machinery. This also ensures it
641  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
642  // to combine multiple loads / stores.
643  bool CanEliminateFrame = true;
644  bool CS1Spilled = false;
645  bool LRSpilled = false;
646  unsigned NumGPRSpills = 0;
647  SmallVector<unsigned, 4> UnspilledCS1GPRs;
648  SmallVector<unsigned, 4> UnspilledCS2GPRs;
649  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
650
651  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
652  // scratch register.
653  // FIXME: It will be better just to find spare register here.
654  if (needsStackRealignment(MF) &&
655      AFI->isThumb2Function())
656    MF.getRegInfo().setPhysRegUsed(ARM::R4);
657
658  // Spill LR if Thumb1 function uses variable length argument lists.
659  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
660    MF.getRegInfo().setPhysRegUsed(ARM::LR);
661
662  // Don't spill FP if the frame can be eliminated. This is determined
663  // by scanning the callee-save registers to see if any is used.
664  const unsigned *CSRegs = getCalleeSavedRegs();
665  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
666  for (unsigned i = 0; CSRegs[i]; ++i) {
667    unsigned Reg = CSRegs[i];
668    bool Spilled = false;
669    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
670      AFI->setCSRegisterIsSpilled(Reg);
671      Spilled = true;
672      CanEliminateFrame = false;
673    } else {
674      // Check alias registers too.
675      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
676        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
677          Spilled = true;
678          CanEliminateFrame = false;
679        }
680      }
681    }
682
683    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
684        CSRegClasses[i] == ARM::tGPRRegisterClass) {
685      if (Spilled) {
686        NumGPRSpills++;
687
688        if (!STI.isTargetDarwin()) {
689          if (Reg == ARM::LR)
690            LRSpilled = true;
691          CS1Spilled = true;
692          continue;
693        }
694
695        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
696        switch (Reg) {
697        case ARM::LR:
698          LRSpilled = true;
699          // Fallthrough
700        case ARM::R4:
701        case ARM::R5:
702        case ARM::R6:
703        case ARM::R7:
704          CS1Spilled = true;
705          break;
706        default:
707          break;
708        }
709      } else {
710        if (!STI.isTargetDarwin()) {
711          UnspilledCS1GPRs.push_back(Reg);
712          continue;
713        }
714
715        switch (Reg) {
716        case ARM::R4:
717        case ARM::R5:
718        case ARM::R6:
719        case ARM::R7:
720        case ARM::LR:
721          UnspilledCS1GPRs.push_back(Reg);
722          break;
723        default:
724          UnspilledCS2GPRs.push_back(Reg);
725          break;
726        }
727      }
728    }
729  }
730
731  bool ForceLRSpill = false;
732  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
733    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
734    // Force LR to be spilled if the Thumb function size is > 2048. This enables
735    // use of BL to implement far jump. If it turns out that it's not needed
736    // then the branch fix up path will undo it.
737    if (FnSize >= (1 << 11)) {
738      CanEliminateFrame = false;
739      ForceLRSpill = true;
740    }
741  }
742
743  // If any of the stack slot references may be out of range of an immediate
744  // offset, make sure a register (or a spill slot) is available for the
745  // register scavenger. Note that if we're indexing off the frame pointer, the
746  // effective stack size is 4 bytes larger since the FP points to the stack
747  // slot of the previous FP.
748  bool BigStack = RS &&
749    estimateStackSize(MF) + (hasFP(MF) ? 4 : 0) >= estimateRSStackSizeLimit(MF);
750
751  bool ExtraCSSpill = false;
752  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
753    AFI->setHasStackFrame(true);
754
755    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
756    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
757    if (!LRSpilled && CS1Spilled) {
758      MF.getRegInfo().setPhysRegUsed(ARM::LR);
759      AFI->setCSRegisterIsSpilled(ARM::LR);
760      NumGPRSpills++;
761      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
762                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
763      ForceLRSpill = false;
764      ExtraCSSpill = true;
765    }
766
767    // Darwin ABI requires FP to point to the stack slot that contains the
768    // previous FP.
769    if (STI.isTargetDarwin() || hasFP(MF)) {
770      MF.getRegInfo().setPhysRegUsed(FramePtr);
771      NumGPRSpills++;
772    }
773
774    // If stack and double are 8-byte aligned and we are spilling an odd number
775    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
776    // the integer and double callee save areas.
777    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
778    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
779      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
780        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
781          unsigned Reg = UnspilledCS1GPRs[i];
782          // Don't spill high register if the function is thumb1
783          if (!AFI->isThumb1OnlyFunction() ||
784              isARMLowRegister(Reg) || Reg == ARM::LR) {
785            MF.getRegInfo().setPhysRegUsed(Reg);
786            AFI->setCSRegisterIsSpilled(Reg);
787            if (!isReservedReg(MF, Reg))
788              ExtraCSSpill = true;
789            break;
790          }
791        }
792      } else if (!UnspilledCS2GPRs.empty() &&
793                 !AFI->isThumb1OnlyFunction()) {
794        unsigned Reg = UnspilledCS2GPRs.front();
795        MF.getRegInfo().setPhysRegUsed(Reg);
796        AFI->setCSRegisterIsSpilled(Reg);
797        if (!isReservedReg(MF, Reg))
798          ExtraCSSpill = true;
799      }
800    }
801
802    // Estimate if we might need to scavenge a register at some point in order
803    // to materialize a stack offset. If so, either spill one additional
804    // callee-saved register or reserve a special spill slot to facilitate
805    // register scavenging. Thumb1 needs a spill slot for stack pointer
806    // adjustments also, even when the frame itself is small.
807    if (BigStack && !ExtraCSSpill) {
808      // If any non-reserved CS register isn't spilled, just spill one or two
809      // extra. That should take care of it!
810      unsigned NumExtras = TargetAlign / 4;
811      SmallVector<unsigned, 2> Extras;
812      while (NumExtras && !UnspilledCS1GPRs.empty()) {
813        unsigned Reg = UnspilledCS1GPRs.back();
814        UnspilledCS1GPRs.pop_back();
815        if (!isReservedReg(MF, Reg) &&
816            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
817             Reg == ARM::LR)) {
818          Extras.push_back(Reg);
819          NumExtras--;
820        }
821      }
822      // For non-Thumb1 functions, also check for hi-reg CS registers
823      if (!AFI->isThumb1OnlyFunction()) {
824        while (NumExtras && !UnspilledCS2GPRs.empty()) {
825          unsigned Reg = UnspilledCS2GPRs.back();
826          UnspilledCS2GPRs.pop_back();
827          if (!isReservedReg(MF, Reg)) {
828            Extras.push_back(Reg);
829            NumExtras--;
830          }
831        }
832      }
833      if (Extras.size() && NumExtras == 0) {
834        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
835          MF.getRegInfo().setPhysRegUsed(Extras[i]);
836          AFI->setCSRegisterIsSpilled(Extras[i]);
837        }
838      } else if (!AFI->isThumb1OnlyFunction()) {
839        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
840        // closest to SP or frame pointer.
841        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
842        MachineFrameInfo *MFI = MF.getFrameInfo();
843        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
844                                                           RC->getAlignment(),
845                                                           false));
846      }
847    }
848  }
849
850  if (ForceLRSpill) {
851    MF.getRegInfo().setPhysRegUsed(ARM::LR);
852    AFI->setCSRegisterIsSpilled(ARM::LR);
853    AFI->setLRIsSpilledForFarJump(true);
854  }
855}
856
857unsigned ARMBaseRegisterInfo::getRARegister() const {
858  return ARM::LR;
859}
860
861unsigned
862ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
863  if (STI.isTargetDarwin() || hasFP(MF))
864    return FramePtr;
865  return ARM::SP;
866}
867
868int
869ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
870                                            unsigned &FrameReg) const {
871  const MachineFrameInfo *MFI = MF.getFrameInfo();
872  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
873  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
874  bool isFixed = MFI->isFixedObjectIndex(FI);
875
876  FrameReg = ARM::SP;
877  if (AFI->isGPRCalleeSavedArea1Frame(FI))
878    Offset -= AFI->getGPRCalleeSavedArea1Offset();
879  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
880    Offset -= AFI->getGPRCalleeSavedArea2Offset();
881  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
882    Offset -= AFI->getDPRCalleeSavedAreaOffset();
883  else if (needsStackRealignment(MF)) {
884    // When dynamically realigning the stack, use the frame pointer for
885    // parameters, and the stack pointer for locals.
886    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
887    if (isFixed) {
888      FrameReg = getFrameRegister(MF);
889      Offset -= AFI->getFramePtrSpillOffset();
890    }
891  } else if (hasFP(MF) && AFI->hasStackFrame()) {
892    if (isFixed || MFI->hasVarSizedObjects()) {
893      // Use frame pointer to reference fixed objects unless this is a
894      // frameless function.
895      FrameReg = getFrameRegister(MF);
896      Offset -= AFI->getFramePtrSpillOffset();
897    } else if (AFI->isThumb2Function()) {
898      // In Thumb2 mode, the negative offset is very limited.
899      int FPOffset = Offset - AFI->getFramePtrSpillOffset();
900      if (FPOffset >= -255 && FPOffset < 0) {
901        FrameReg = getFrameRegister(MF);
902        Offset = FPOffset;
903      }
904    }
905  }
906  return Offset;
907}
908
909
910int
911ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
912                                         int FI) const {
913  unsigned FrameReg;
914  return getFrameIndexReference(MF, FI, FrameReg);
915}
916
917unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
918  llvm_unreachable("What is the exception register");
919  return 0;
920}
921
922unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
923  llvm_unreachable("What is the exception handler register");
924  return 0;
925}
926
927int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
928  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
929}
930
931unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
932                                              const MachineFunction &MF) const {
933  switch (Reg) {
934  default: break;
935  // Return 0 if either register of the pair is a special register.
936  // So no R12, etc.
937  case ARM::R1:
938    return ARM::R0;
939  case ARM::R3:
940    return ARM::R2;
941  case ARM::R5:
942    return ARM::R4;
943  case ARM::R7:
944    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
945  case ARM::R9:
946    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
947  case ARM::R11:
948    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
949
950  case ARM::S1:
951    return ARM::S0;
952  case ARM::S3:
953    return ARM::S2;
954  case ARM::S5:
955    return ARM::S4;
956  case ARM::S7:
957    return ARM::S6;
958  case ARM::S9:
959    return ARM::S8;
960  case ARM::S11:
961    return ARM::S10;
962  case ARM::S13:
963    return ARM::S12;
964  case ARM::S15:
965    return ARM::S14;
966  case ARM::S17:
967    return ARM::S16;
968  case ARM::S19:
969    return ARM::S18;
970  case ARM::S21:
971    return ARM::S20;
972  case ARM::S23:
973    return ARM::S22;
974  case ARM::S25:
975    return ARM::S24;
976  case ARM::S27:
977    return ARM::S26;
978  case ARM::S29:
979    return ARM::S28;
980  case ARM::S31:
981    return ARM::S30;
982
983  case ARM::D1:
984    return ARM::D0;
985  case ARM::D3:
986    return ARM::D2;
987  case ARM::D5:
988    return ARM::D4;
989  case ARM::D7:
990    return ARM::D6;
991  case ARM::D9:
992    return ARM::D8;
993  case ARM::D11:
994    return ARM::D10;
995  case ARM::D13:
996    return ARM::D12;
997  case ARM::D15:
998    return ARM::D14;
999  case ARM::D17:
1000    return ARM::D16;
1001  case ARM::D19:
1002    return ARM::D18;
1003  case ARM::D21:
1004    return ARM::D20;
1005  case ARM::D23:
1006    return ARM::D22;
1007  case ARM::D25:
1008    return ARM::D24;
1009  case ARM::D27:
1010    return ARM::D26;
1011  case ARM::D29:
1012    return ARM::D28;
1013  case ARM::D31:
1014    return ARM::D30;
1015  }
1016
1017  return 0;
1018}
1019
1020unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1021                                             const MachineFunction &MF) const {
1022  switch (Reg) {
1023  default: break;
1024  // Return 0 if either register of the pair is a special register.
1025  // So no R12, etc.
1026  case ARM::R0:
1027    return ARM::R1;
1028  case ARM::R2:
1029    return ARM::R3;
1030  case ARM::R4:
1031    return ARM::R5;
1032  case ARM::R6:
1033    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
1034  case ARM::R8:
1035    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1036  case ARM::R10:
1037    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1038
1039  case ARM::S0:
1040    return ARM::S1;
1041  case ARM::S2:
1042    return ARM::S3;
1043  case ARM::S4:
1044    return ARM::S5;
1045  case ARM::S6:
1046    return ARM::S7;
1047  case ARM::S8:
1048    return ARM::S9;
1049  case ARM::S10:
1050    return ARM::S11;
1051  case ARM::S12:
1052    return ARM::S13;
1053  case ARM::S14:
1054    return ARM::S15;
1055  case ARM::S16:
1056    return ARM::S17;
1057  case ARM::S18:
1058    return ARM::S19;
1059  case ARM::S20:
1060    return ARM::S21;
1061  case ARM::S22:
1062    return ARM::S23;
1063  case ARM::S24:
1064    return ARM::S25;
1065  case ARM::S26:
1066    return ARM::S27;
1067  case ARM::S28:
1068    return ARM::S29;
1069  case ARM::S30:
1070    return ARM::S31;
1071
1072  case ARM::D0:
1073    return ARM::D1;
1074  case ARM::D2:
1075    return ARM::D3;
1076  case ARM::D4:
1077    return ARM::D5;
1078  case ARM::D6:
1079    return ARM::D7;
1080  case ARM::D8:
1081    return ARM::D9;
1082  case ARM::D10:
1083    return ARM::D11;
1084  case ARM::D12:
1085    return ARM::D13;
1086  case ARM::D14:
1087    return ARM::D15;
1088  case ARM::D16:
1089    return ARM::D17;
1090  case ARM::D18:
1091    return ARM::D19;
1092  case ARM::D20:
1093    return ARM::D21;
1094  case ARM::D22:
1095    return ARM::D23;
1096  case ARM::D24:
1097    return ARM::D25;
1098  case ARM::D26:
1099    return ARM::D27;
1100  case ARM::D28:
1101    return ARM::D29;
1102  case ARM::D30:
1103    return ARM::D31;
1104  }
1105
1106  return 0;
1107}
1108
1109/// emitLoadConstPool - Emits a load from constpool to materialize the
1110/// specified immediate.
1111void ARMBaseRegisterInfo::
1112emitLoadConstPool(MachineBasicBlock &MBB,
1113                  MachineBasicBlock::iterator &MBBI,
1114                  DebugLoc dl,
1115                  unsigned DestReg, unsigned SubIdx, int Val,
1116                  ARMCC::CondCodes Pred,
1117                  unsigned PredReg) const {
1118  MachineFunction &MF = *MBB.getParent();
1119  MachineConstantPool *ConstantPool = MF.getConstantPool();
1120  const Constant *C =
1121        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1122  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1123
1124  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1125    .addReg(DestReg, getDefRegState(true), SubIdx)
1126    .addConstantPoolIndex(Idx)
1127    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1128}
1129
1130bool ARMBaseRegisterInfo::
1131requiresRegisterScavenging(const MachineFunction &MF) const {
1132  return true;
1133}
1134
1135bool ARMBaseRegisterInfo::
1136requiresFrameIndexScavenging(const MachineFunction &MF) const {
1137  return true;
1138}
1139
1140// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1141// not required, we reserve argument space for call sites in the function
1142// immediately on entry to the current function. This eliminates the need for
1143// add/sub sp brackets around call sites. Returns true if the call frame is
1144// included as part of the stack frame.
1145bool ARMBaseRegisterInfo::
1146hasReservedCallFrame(MachineFunction &MF) const {
1147  const MachineFrameInfo *FFI = MF.getFrameInfo();
1148  unsigned CFSize = FFI->getMaxCallFrameSize();
1149  // It's not always a good idea to include the call frame as part of the
1150  // stack frame. ARM (especially Thumb) has small immediate offset to
1151  // address the stack frame. So a large call frame can cause poor codegen
1152  // and may even makes it impossible to scavenge a register.
1153  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1154    return false;
1155
1156  return !MF.getFrameInfo()->hasVarSizedObjects();
1157}
1158
1159// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1160// call frame pseudos can be simplified. Unlike most targets, having a FP
1161// is not sufficient here since we still may reference some objects via SP
1162// even when FP is available in Thumb2 mode.
1163bool ARMBaseRegisterInfo::
1164canSimplifyCallFramePseudos(MachineFunction &MF) const {
1165  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1166}
1167
1168static void
1169emitSPUpdate(bool isARM,
1170             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1171             DebugLoc dl, const ARMBaseInstrInfo &TII,
1172             int NumBytes,
1173             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1174  if (isARM)
1175    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1176                            Pred, PredReg, TII);
1177  else
1178    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1179                           Pred, PredReg, TII);
1180}
1181
1182
1183void ARMBaseRegisterInfo::
1184eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1185                              MachineBasicBlock::iterator I) const {
1186  if (!hasReservedCallFrame(MF)) {
1187    // If we have alloca, convert as follows:
1188    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1189    // ADJCALLSTACKUP   -> add, sp, sp, amount
1190    MachineInstr *Old = I;
1191    DebugLoc dl = Old->getDebugLoc();
1192    unsigned Amount = Old->getOperand(0).getImm();
1193    if (Amount != 0) {
1194      // We need to keep the stack aligned properly.  To do this, we round the
1195      // amount of space needed for the outgoing arguments up to the next
1196      // alignment boundary.
1197      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1198      Amount = (Amount+Align-1)/Align*Align;
1199
1200      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1201      assert(!AFI->isThumb1OnlyFunction() &&
1202             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1203      bool isARM = !AFI->isThumbFunction();
1204
1205      // Replace the pseudo instruction with a new instruction...
1206      unsigned Opc = Old->getOpcode();
1207      int PIdx = Old->findFirstPredOperandIdx();
1208      ARMCC::CondCodes Pred = (PIdx == -1)
1209        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1210      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1211        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1212        unsigned PredReg = Old->getOperand(2).getReg();
1213        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1214      } else {
1215        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1216        unsigned PredReg = Old->getOperand(3).getReg();
1217        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1218        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1219      }
1220    }
1221  }
1222  MBB.erase(I);
1223}
1224
1225unsigned
1226ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1227                                         int SPAdj, FrameIndexValue *Value,
1228                                         RegScavenger *RS) const {
1229  unsigned i = 0;
1230  MachineInstr &MI = *II;
1231  MachineBasicBlock &MBB = *MI.getParent();
1232  MachineFunction &MF = *MBB.getParent();
1233  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1234  assert(!AFI->isThumb1OnlyFunction() &&
1235         "This eliminateFrameIndex does not support Thumb1!");
1236
1237  while (!MI.getOperand(i).isFI()) {
1238    ++i;
1239    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1240  }
1241
1242  int FrameIndex = MI.getOperand(i).getIndex();
1243  unsigned FrameReg;
1244
1245  int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg);
1246  if (FrameReg != ARM::SP)
1247    SPAdj = 0;
1248  Offset += SPAdj;
1249
1250  // Special handling of dbg_value instructions.
1251  if (MI.isDebugValue()) {
1252    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1253    MI.getOperand(i+1).ChangeToImmediate(Offset);
1254    return 0;
1255  }
1256
1257  // Modify MI as necessary to handle as much of 'Offset' as possible
1258  bool Done = false;
1259  if (!AFI->isThumbFunction())
1260    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1261  else {
1262    assert(AFI->isThumb2Function());
1263    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1264  }
1265  if (Done)
1266    return 0;
1267
1268  // If we get here, the immediate doesn't fit into the instruction.  We folded
1269  // as much as possible above, handle the rest, providing a register that is
1270  // SP+LargeImm.
1271  assert((Offset ||
1272          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1273          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1274         "This code isn't needed if offset already handled!");
1275
1276  unsigned ScratchReg = 0;
1277  int PIdx = MI.findFirstPredOperandIdx();
1278  ARMCC::CondCodes Pred = (PIdx == -1)
1279    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1280  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1281  if (Offset == 0)
1282    // Must be addrmode4/6.
1283    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1284  else {
1285    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1286    if (Value) {
1287      Value->first = FrameReg; // use the frame register as a kind indicator
1288      Value->second = Offset;
1289    }
1290    if (!AFI->isThumbFunction())
1291      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1292                              Offset, Pred, PredReg, TII);
1293    else {
1294      assert(AFI->isThumb2Function());
1295      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1296                             Offset, Pred, PredReg, TII);
1297    }
1298    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1299    if (!ReuseFrameIndexVals)
1300      ScratchReg = 0;
1301  }
1302  return ScratchReg;
1303}
1304
1305/// Move iterator past the next bunch of callee save load / store ops for
1306/// the particular spill area (1: integer area 1, 2: integer area 2,
1307/// 3: fp area, 0: don't care).
1308static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1309                                   MachineBasicBlock::iterator &MBBI,
1310                                   int Opc1, int Opc2, unsigned Area,
1311                                   const ARMSubtarget &STI) {
1312  while (MBBI != MBB.end() &&
1313         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1314         MBBI->getOperand(1).isFI()) {
1315    if (Area != 0) {
1316      bool Done = false;
1317      unsigned Category = 0;
1318      switch (MBBI->getOperand(0).getReg()) {
1319      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1320      case ARM::LR:
1321        Category = 1;
1322        break;
1323      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1324        Category = STI.isTargetDarwin() ? 2 : 1;
1325        break;
1326      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1327      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1328        Category = 3;
1329        break;
1330      default:
1331        Done = true;
1332        break;
1333      }
1334      if (Done || Category != Area)
1335        break;
1336    }
1337
1338    ++MBBI;
1339  }
1340}
1341
1342void ARMBaseRegisterInfo::
1343emitPrologue(MachineFunction &MF) const {
1344  MachineBasicBlock &MBB = MF.front();
1345  MachineBasicBlock::iterator MBBI = MBB.begin();
1346  MachineFrameInfo  *MFI = MF.getFrameInfo();
1347  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1348  assert(!AFI->isThumb1OnlyFunction() &&
1349         "This emitPrologue does not support Thumb1!");
1350  bool isARM = !AFI->isThumbFunction();
1351  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1352  unsigned NumBytes = MFI->getStackSize();
1353  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1354  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1355
1356  // Determine the sizes of each callee-save spill areas and record which frame
1357  // belongs to which callee-save spill areas.
1358  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1359  int FramePtrSpillFI = 0;
1360
1361  // Allocate the vararg register save area. This is not counted in NumBytes.
1362  if (VARegSaveSize)
1363    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1364
1365  if (!AFI->hasStackFrame()) {
1366    if (NumBytes != 0)
1367      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1368    return;
1369  }
1370
1371  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1372    unsigned Reg = CSI[i].getReg();
1373    int FI = CSI[i].getFrameIdx();
1374    switch (Reg) {
1375    case ARM::R4:
1376    case ARM::R5:
1377    case ARM::R6:
1378    case ARM::R7:
1379    case ARM::LR:
1380      if (Reg == FramePtr)
1381        FramePtrSpillFI = FI;
1382      AFI->addGPRCalleeSavedArea1Frame(FI);
1383      GPRCS1Size += 4;
1384      break;
1385    case ARM::R8:
1386    case ARM::R9:
1387    case ARM::R10:
1388    case ARM::R11:
1389      if (Reg == FramePtr)
1390        FramePtrSpillFI = FI;
1391      if (STI.isTargetDarwin()) {
1392        AFI->addGPRCalleeSavedArea2Frame(FI);
1393        GPRCS2Size += 4;
1394      } else {
1395        AFI->addGPRCalleeSavedArea1Frame(FI);
1396        GPRCS1Size += 4;
1397      }
1398      break;
1399    default:
1400      AFI->addDPRCalleeSavedAreaFrame(FI);
1401      DPRCSSize += 8;
1402    }
1403  }
1404
1405  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1406  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1407  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1408
1409  // Set FP to point to the stack slot that contains the previous FP.
1410  // For Darwin, FP is R7, which has now been stored in spill area 1.
1411  // Otherwise, if this is not Darwin, all the callee-saved registers go
1412  // into spill area 1, including the FP in R11.  In either case, it is
1413  // now safe to emit this assignment.
1414  if (STI.isTargetDarwin() || hasFP(MF)) {
1415    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1416    MachineInstrBuilder MIB =
1417      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1418      .addFrameIndex(FramePtrSpillFI).addImm(0);
1419    AddDefaultCC(AddDefaultPred(MIB));
1420  }
1421
1422  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1423  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1424
1425  // Build the new SUBri to adjust SP for FP callee-save spill area.
1426  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1427  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1428
1429  // Determine starting offsets of spill areas.
1430  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1431  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1432  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1433  if (STI.isTargetDarwin() || hasFP(MF))
1434    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1435                                NumBytes);
1436  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1437  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1438  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1439
1440  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1441  NumBytes = DPRCSOffset;
1442  if (NumBytes) {
1443    // Adjust SP after all the callee-save spills.
1444    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1445  }
1446
1447  if (STI.isTargetELF() && hasFP(MF)) {
1448    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1449                             AFI->getFramePtrSpillOffset());
1450  }
1451
1452  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1453  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1454  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1455
1456  // If we need dynamic stack realignment, do it here.
1457  if (needsStackRealignment(MF)) {
1458    unsigned MaxAlign = MFI->getMaxAlignment();
1459    assert (!AFI->isThumb1OnlyFunction());
1460    if (!AFI->isThumbFunction()) {
1461      // Emit bic sp, sp, MaxAlign
1462      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1463                                          TII.get(ARM::BICri), ARM::SP)
1464                                  .addReg(ARM::SP, RegState::Kill)
1465                                  .addImm(MaxAlign-1)));
1466    } else {
1467      // We cannot use sp as source/dest register here, thus we're emitting the
1468      // following sequence:
1469      // mov r4, sp
1470      // bic r4, r4, MaxAlign
1471      // mov sp, r4
1472      // FIXME: It will be better just to find spare register here.
1473      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1474        .addReg(ARM::SP, RegState::Kill);
1475      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1476                                          TII.get(ARM::t2BICri), ARM::R4)
1477                                  .addReg(ARM::R4, RegState::Kill)
1478                                  .addImm(MaxAlign-1)));
1479      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1480        .addReg(ARM::R4, RegState::Kill);
1481    }
1482  }
1483}
1484
1485static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1486  for (unsigned i = 0; CSRegs[i]; ++i)
1487    if (Reg == CSRegs[i])
1488      return true;
1489  return false;
1490}
1491
1492static bool isCSRestore(MachineInstr *MI,
1493                        const ARMBaseInstrInfo &TII,
1494                        const unsigned *CSRegs) {
1495  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1496           MI->getOpcode() == (int)ARM::LDR ||
1497           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1498          MI->getOperand(1).isFI() &&
1499          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1500}
1501
1502void ARMBaseRegisterInfo::
1503emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1504  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1505  assert(MBBI->getDesc().isReturn() &&
1506         "Can only insert epilog into returning blocks");
1507  DebugLoc dl = MBBI->getDebugLoc();
1508  MachineFrameInfo *MFI = MF.getFrameInfo();
1509  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1510  assert(!AFI->isThumb1OnlyFunction() &&
1511         "This emitEpilogue does not support Thumb1!");
1512  bool isARM = !AFI->isThumbFunction();
1513
1514  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1515  int NumBytes = (int)MFI->getStackSize();
1516
1517  if (!AFI->hasStackFrame()) {
1518    if (NumBytes != 0)
1519      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1520  } else {
1521    // Unwind MBBI to point to first LDR / VLDRD.
1522    const unsigned *CSRegs = getCalleeSavedRegs();
1523    if (MBBI != MBB.begin()) {
1524      do
1525        --MBBI;
1526      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1527      if (!isCSRestore(MBBI, TII, CSRegs))
1528        ++MBBI;
1529    }
1530
1531    // Move SP to start of FP callee save spill area.
1532    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1533                 AFI->getGPRCalleeSavedArea2Size() +
1534                 AFI->getDPRCalleeSavedAreaSize());
1535
1536    // Darwin ABI requires FP to point to the stack slot that contains the
1537    // previous FP.
1538    bool HasFP = hasFP(MF);
1539    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1540      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1541      // Reset SP based on frame pointer only if the stack frame extends beyond
1542      // frame pointer stack slot or target is ELF and the function has FP.
1543      if (HasFP ||
1544          AFI->getGPRCalleeSavedArea2Size() ||
1545          AFI->getDPRCalleeSavedAreaSize()  ||
1546          AFI->getDPRCalleeSavedAreaOffset()) {
1547        if (NumBytes) {
1548          if (isARM)
1549            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1550                                    ARMCC::AL, 0, TII);
1551          else
1552            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1553                                    ARMCC::AL, 0, TII);
1554        } else {
1555          // Thumb2 or ARM.
1556          if (isARM)
1557            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1558              .addReg(FramePtr)
1559              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1560          else
1561            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1562              .addReg(FramePtr);
1563        }
1564      }
1565    } else if (NumBytes)
1566      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1567
1568    // Move SP to start of integer callee save spill area 2.
1569    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1570    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1571
1572    // Move SP to start of integer callee save spill area 1.
1573    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1574    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1575
1576    // Move SP to SP upon entry to the function.
1577    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1578    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1579  }
1580
1581  if (VARegSaveSize)
1582    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1583}
1584
1585#include "ARMGenRegisterInfo.inc"
1586