ARMBaseRegisterInfo.cpp revision 84e58d03c910aa6ea8557d2f2f9de1f96162cae1 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41using namespace llvm;
42
43static cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46
47static cl::opt<bool>
48ARMDynamicStackAlign("arm-dynamic-stack-alignment", cl::Hidden, cl::init(false),
49          cl::desc("Dynamically re-align the stack as needed"));
50
51unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
52                                                   bool *isSPVFP) {
53  if (isSPVFP)
54    *isSPVFP = false;
55
56  using namespace ARM;
57  switch (RegEnum) {
58  default:
59    llvm_unreachable("Unknown ARM register!");
60  case R0:  case D0:  case Q0:  return 0;
61  case R1:  case D1:  case Q1:  return 1;
62  case R2:  case D2:  case Q2:  return 2;
63  case R3:  case D3:  case Q3:  return 3;
64  case R4:  case D4:  case Q4:  return 4;
65  case R5:  case D5:  case Q5:  return 5;
66  case R6:  case D6:  case Q6:  return 6;
67  case R7:  case D7:  case Q7:  return 7;
68  case R8:  case D8:  case Q8:  return 8;
69  case R9:  case D9:  case Q9:  return 9;
70  case R10: case D10: case Q10: return 10;
71  case R11: case D11: case Q11: return 11;
72  case R12: case D12: case Q12: return 12;
73  case SP:  case D13: case Q13: return 13;
74  case LR:  case D14: case Q14: return 14;
75  case PC:  case D15: case Q15: return 15;
76
77  case D16: return 16;
78  case D17: return 17;
79  case D18: return 18;
80  case D19: return 19;
81  case D20: return 20;
82  case D21: return 21;
83  case D22: return 22;
84  case D23: return 23;
85  case D24: return 24;
86  case D25: return 25;
87  case D26: return 27;
88  case D27: return 27;
89  case D28: return 28;
90  case D29: return 29;
91  case D30: return 30;
92  case D31: return 31;
93
94  case S0: case S1: case S2: case S3:
95  case S4: case S5: case S6: case S7:
96  case S8: case S9: case S10: case S11:
97  case S12: case S13: case S14: case S15:
98  case S16: case S17: case S18: case S19:
99  case S20: case S21: case S22: case S23:
100  case S24: case S25: case S26: case S27:
101  case S28: case S29: case S30: case S31: {
102    if (isSPVFP)
103      *isSPVFP = true;
104    switch (RegEnum) {
105    default: return 0; // Avoid compile time warning.
106    case S0: return 0;
107    case S1: return 1;
108    case S2: return 2;
109    case S3: return 3;
110    case S4: return 4;
111    case S5: return 5;
112    case S6: return 6;
113    case S7: return 7;
114    case S8: return 8;
115    case S9: return 9;
116    case S10: return 10;
117    case S11: return 11;
118    case S12: return 12;
119    case S13: return 13;
120    case S14: return 14;
121    case S15: return 15;
122    case S16: return 16;
123    case S17: return 17;
124    case S18: return 18;
125    case S19: return 19;
126    case S20: return 20;
127    case S21: return 21;
128    case S22: return 22;
129    case S23: return 23;
130    case S24: return 24;
131    case S25: return 25;
132    case S26: return 26;
133    case S27: return 27;
134    case S28: return 28;
135    case S29: return 29;
136    case S30: return 30;
137    case S31: return 31;
138    }
139  }
140  }
141}
142
143ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
144                                         const ARMSubtarget &sti)
145  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
146    TII(tii), STI(sti),
147    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
148}
149
150const unsigned*
151ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
152  static const unsigned CalleeSavedRegs[] = {
153    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
154    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
155
156    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
157    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
158    0
159  };
160
161  static const unsigned DarwinCalleeSavedRegs[] = {
162    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
163    // register.
164    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
165    ARM::R11, ARM::R10, ARM::R8,
166
167    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
168    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
169    0
170  };
171  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
172}
173
174const TargetRegisterClass* const *
175ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
176  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
177    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
179    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
180
181    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
183    0
184  };
185
186  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
189    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
190
191    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
193    0
194  };
195
196  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
197    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
198    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
199    &ARM::GPRRegClass, &ARM::GPRRegClass,
200
201    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
203    0
204  };
205
206  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
207    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
208    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
209    &ARM::GPRRegClass,  &ARM::GPRRegClass,
210
211    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
212    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
213    0
214  };
215
216  if (STI.isThumb1Only()) {
217    return STI.isTargetDarwin()
218      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
219  }
220  return STI.isTargetDarwin()
221    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
222}
223
224BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
225  // FIXME: avoid re-calculating this everytime.
226  BitVector Reserved(getNumRegs());
227  Reserved.set(ARM::SP);
228  Reserved.set(ARM::PC);
229  if (STI.isTargetDarwin() || hasFP(MF))
230    Reserved.set(FramePtr);
231  // Some targets reserve R9.
232  if (STI.isR9Reserved())
233    Reserved.set(ARM::R9);
234  return Reserved;
235}
236
237bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
238                                        unsigned Reg) const {
239  switch (Reg) {
240  default: break;
241  case ARM::SP:
242  case ARM::PC:
243    return true;
244  case ARM::R7:
245  case ARM::R11:
246    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
247      return true;
248    break;
249  case ARM::R9:
250    return STI.isR9Reserved();
251  }
252
253  return false;
254}
255
256const TargetRegisterClass *
257ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
258                                              const TargetRegisterClass *B,
259                                              unsigned SubIdx) const {
260  switch (SubIdx) {
261  default: return 0;
262  case 1:
263  case 2:
264  case 3:
265  case 4:
266    // S sub-registers.
267    if (A->getSize() == 8) {
268      if (A == &ARM::DPR_8RegClass)
269        return A;
270      return &ARM::DPR_VFP2RegClass;
271    }
272
273    assert(A->getSize() == 16 && "Expecting a Q register class!");
274    return &ARM::QPR_VFP2RegClass;
275  case 5:
276  case 6:
277    // D sub-registers.
278    return A;
279  }
280  return 0;
281}
282
283const TargetRegisterClass *
284ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
285  return ARM::GPRRegisterClass;
286}
287
288/// getAllocationOrder - Returns the register allocation order for a specified
289/// register class in the form of a pair of TargetRegisterClass iterators.
290std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
291ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
292                                        unsigned HintType, unsigned HintReg,
293                                        const MachineFunction &MF) const {
294  // Alternative register allocation orders when favoring even / odd registers
295  // of register pairs.
296
297  // No FP, R9 is available.
298  static const unsigned GPREven1[] = {
299    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
300    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
301    ARM::R9, ARM::R11
302  };
303  static const unsigned GPROdd1[] = {
304    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
305    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
306    ARM::R8, ARM::R10
307  };
308
309  // FP is R7, R9 is available.
310  static const unsigned GPREven2[] = {
311    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
312    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
313    ARM::R9, ARM::R11
314  };
315  static const unsigned GPROdd2[] = {
316    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
317    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
318    ARM::R8, ARM::R10
319  };
320
321  // FP is R11, R9 is available.
322  static const unsigned GPREven3[] = {
323    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
324    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
325    ARM::R9
326  };
327  static const unsigned GPROdd3[] = {
328    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
329    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
330    ARM::R8
331  };
332
333  // No FP, R9 is not available.
334  static const unsigned GPREven4[] = {
335    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
336    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
337    ARM::R11
338  };
339  static const unsigned GPROdd4[] = {
340    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
341    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
342    ARM::R10
343  };
344
345  // FP is R7, R9 is not available.
346  static const unsigned GPREven5[] = {
347    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
348    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
349    ARM::R11
350  };
351  static const unsigned GPROdd5[] = {
352    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
353    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
354    ARM::R10
355  };
356
357  // FP is R11, R9 is not available.
358  static const unsigned GPREven6[] = {
359    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
360    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
361  };
362  static const unsigned GPROdd6[] = {
363    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
364    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
365  };
366
367
368  if (HintType == ARMRI::RegPairEven) {
369    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
370      // It's no longer possible to fulfill this hint. Return the default
371      // allocation order.
372      return std::make_pair(RC->allocation_order_begin(MF),
373                            RC->allocation_order_end(MF));
374
375    if (!STI.isTargetDarwin() && !hasFP(MF)) {
376      if (!STI.isR9Reserved())
377        return std::make_pair(GPREven1,
378                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
379      else
380        return std::make_pair(GPREven4,
381                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
382    } else if (FramePtr == ARM::R7) {
383      if (!STI.isR9Reserved())
384        return std::make_pair(GPREven2,
385                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
386      else
387        return std::make_pair(GPREven5,
388                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
389    } else { // FramePtr == ARM::R11
390      if (!STI.isR9Reserved())
391        return std::make_pair(GPREven3,
392                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
393      else
394        return std::make_pair(GPREven6,
395                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
396    }
397  } else if (HintType == ARMRI::RegPairOdd) {
398    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
399      // It's no longer possible to fulfill this hint. Return the default
400      // allocation order.
401      return std::make_pair(RC->allocation_order_begin(MF),
402                            RC->allocation_order_end(MF));
403
404    if (!STI.isTargetDarwin() && !hasFP(MF)) {
405      if (!STI.isR9Reserved())
406        return std::make_pair(GPROdd1,
407                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
408      else
409        return std::make_pair(GPROdd4,
410                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
411    } else if (FramePtr == ARM::R7) {
412      if (!STI.isR9Reserved())
413        return std::make_pair(GPROdd2,
414                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
415      else
416        return std::make_pair(GPROdd5,
417                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
418    } else { // FramePtr == ARM::R11
419      if (!STI.isR9Reserved())
420        return std::make_pair(GPROdd3,
421                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
422      else
423        return std::make_pair(GPROdd6,
424                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
425    }
426  }
427  return std::make_pair(RC->allocation_order_begin(MF),
428                        RC->allocation_order_end(MF));
429}
430
431/// ResolveRegAllocHint - Resolves the specified register allocation hint
432/// to a physical register. Returns the physical register if it is successful.
433unsigned
434ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
435                                         const MachineFunction &MF) const {
436  if (Reg == 0 || !isPhysicalRegister(Reg))
437    return 0;
438  if (Type == 0)
439    return Reg;
440  else if (Type == (unsigned)ARMRI::RegPairOdd)
441    // Odd register.
442    return getRegisterPairOdd(Reg, MF);
443  else if (Type == (unsigned)ARMRI::RegPairEven)
444    // Even register.
445    return getRegisterPairEven(Reg, MF);
446  return 0;
447}
448
449void
450ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
451                                        MachineFunction &MF) const {
452  MachineRegisterInfo *MRI = &MF.getRegInfo();
453  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
454  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
455       Hint.first == (unsigned)ARMRI::RegPairEven) &&
456      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
457    // If 'Reg' is one of the even / odd register pair and it's now changed
458    // (e.g. coalesced) into a different register. The other register of the
459    // pair allocation hint must be updated to reflect the relationship
460    // change.
461    unsigned OtherReg = Hint.second;
462    Hint = MRI->getRegAllocationHint(OtherReg);
463    if (Hint.second == Reg)
464      // Make sure the pair has not already divorced.
465      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
466  }
467}
468
469static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
470  // FIXME: For now, force at least 128-bit alignment. This will push the
471  // nightly tester harder for making sure things work correctly. When
472  // we're ready to enable this for real, this goes back to starting at zero.
473  unsigned MaxAlign = 16;
474//  unsigned MaxAlign = 0;
475
476  for (int i = FFI->getObjectIndexBegin(),
477         e = FFI->getObjectIndexEnd(); i != e; ++i) {
478    if (FFI->isDeadObjectIndex(i))
479      continue;
480
481    unsigned Align = FFI->getObjectAlignment(i);
482    MaxAlign = std::max(MaxAlign, Align);
483  }
484
485  return MaxAlign;
486}
487
488/// hasFP - Return true if the specified function should have a dedicated frame
489/// pointer register.  This is true if the function has variable sized allocas
490/// or if frame pointer elimination is disabled.
491///
492bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
493  const MachineFrameInfo *MFI = MF.getFrameInfo();
494  return (NoFramePointerElim ||
495          needsStackRealignment(MF) ||
496          MFI->hasVarSizedObjects() ||
497          MFI->isFrameAddressTaken());
498}
499
500bool ARMBaseRegisterInfo::
501needsStackRealignment(const MachineFunction &MF) const {
502  // Only do this for ARM if explicitly enabled
503  // FIXME: Once it's passing all the tests, enable by default
504  if (!ARMDynamicStackAlign)
505    return false;
506
507  // FIXME: To force more brutal testing, realign whether we need to or not.
508  // Change this to be more selective when we turn it on for real, of course.
509  const MachineFrameInfo *MFI = MF.getFrameInfo();
510  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
511//  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
512  return (RealignStack &&
513          !AFI->isThumb1OnlyFunction() &&
514//          (MFI->getMaxAlignment() > StackAlign) &&
515          !MFI->hasVarSizedObjects());
516}
517
518bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
519  const MachineFrameInfo *MFI = MF.getFrameInfo();
520  if (NoFramePointerElim && MFI->hasCalls())
521    return true;
522  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
523}
524
525/// estimateStackSize - Estimate and return the size of the frame.
526static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
527  const MachineFrameInfo *FFI = MF.getFrameInfo();
528  int Offset = 0;
529  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
530    int FixedOff = -FFI->getObjectOffset(i);
531    if (FixedOff > Offset) Offset = FixedOff;
532  }
533  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
534    if (FFI->isDeadObjectIndex(i))
535      continue;
536    Offset += FFI->getObjectSize(i);
537    unsigned Align = FFI->getObjectAlignment(i);
538    // Adjust to alignment boundary
539    Offset = (Offset+Align-1)/Align*Align;
540  }
541  return (unsigned)Offset;
542}
543
544/// estimateRSStackSizeLimit - Look at each instruction that references stack
545/// frames and return the stack size limit beyond which some of these
546/// instructions will require scratch register during their expansion later.
547unsigned
548ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
549  unsigned Limit = (1 << 12) - 1;
550  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
551    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
552         I != E; ++I) {
553      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
554        if (!I->getOperand(i).isFI()) continue;
555
556        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
557        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
558        if (AddrMode == ARMII::AddrMode3 ||
559            AddrMode == ARMII::AddrModeT2_i8)
560          return (1 << 8) - 1;
561
562        if (AddrMode == ARMII::AddrMode5 ||
563            AddrMode == ARMII::AddrModeT2_i8s4)
564          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
565
566        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
567          // When the stack offset is negative, we will end up using
568          // the i8 instructions instead.
569          return (1 << 8) - 1;
570        break; // At most one FI per instruction
571      }
572    }
573  }
574
575  return Limit;
576}
577
578void
579ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
580                                                          RegScavenger *RS) const {
581  // This tells PEI to spill the FP as if it is any other callee-save register
582  // to take advantage the eliminateFrameIndex machinery. This also ensures it
583  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
584  // to combine multiple loads / stores.
585  bool CanEliminateFrame = true;
586  bool CS1Spilled = false;
587  bool LRSpilled = false;
588  unsigned NumGPRSpills = 0;
589  SmallVector<unsigned, 4> UnspilledCS1GPRs;
590  SmallVector<unsigned, 4> UnspilledCS2GPRs;
591  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
592
593  MachineFrameInfo *MFI = MF.getFrameInfo();
594
595  // Calculate and set max stack object alignment early, so we can decide
596  // whether we will need stack realignment (and thus FP).
597  if (ARMDynamicStackAlign) {
598    unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
599                                 calculateMaxStackAlignment(MFI));
600    MFI->setMaxAlignment(MaxAlign);
601  }
602
603  // Don't spill FP if the frame can be eliminated. This is determined
604  // by scanning the callee-save registers to see if any is used.
605  const unsigned *CSRegs = getCalleeSavedRegs();
606  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
607  for (unsigned i = 0; CSRegs[i]; ++i) {
608    unsigned Reg = CSRegs[i];
609    bool Spilled = false;
610    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
611      AFI->setCSRegisterIsSpilled(Reg);
612      Spilled = true;
613      CanEliminateFrame = false;
614    } else {
615      // Check alias registers too.
616      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
617        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
618          Spilled = true;
619          CanEliminateFrame = false;
620        }
621      }
622    }
623
624    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
625        CSRegClasses[i] == ARM::tGPRRegisterClass) {
626      if (Spilled) {
627        NumGPRSpills++;
628
629        if (!STI.isTargetDarwin()) {
630          if (Reg == ARM::LR)
631            LRSpilled = true;
632          CS1Spilled = true;
633          continue;
634        }
635
636        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
637        switch (Reg) {
638        case ARM::LR:
639          LRSpilled = true;
640          // Fallthrough
641        case ARM::R4:
642        case ARM::R5:
643        case ARM::R6:
644        case ARM::R7:
645          CS1Spilled = true;
646          break;
647        default:
648          break;
649        }
650      } else {
651        if (!STI.isTargetDarwin()) {
652          UnspilledCS1GPRs.push_back(Reg);
653          continue;
654        }
655
656        switch (Reg) {
657        case ARM::R4:
658        case ARM::R5:
659        case ARM::R6:
660        case ARM::R7:
661        case ARM::LR:
662          UnspilledCS1GPRs.push_back(Reg);
663          break;
664        default:
665          UnspilledCS2GPRs.push_back(Reg);
666          break;
667        }
668      }
669    }
670  }
671
672  bool ForceLRSpill = false;
673  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
674    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
675    // Force LR to be spilled if the Thumb function size is > 2048. This enables
676    // use of BL to implement far jump. If it turns out that it's not needed
677    // then the branch fix up path will undo it.
678    if (FnSize >= (1 << 11)) {
679      CanEliminateFrame = false;
680      ForceLRSpill = true;
681    }
682  }
683
684  bool ExtraCSSpill = false;
685  if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
686    AFI->setHasStackFrame(true);
687
688    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
689    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
690    if (!LRSpilled && CS1Spilled) {
691      MF.getRegInfo().setPhysRegUsed(ARM::LR);
692      AFI->setCSRegisterIsSpilled(ARM::LR);
693      NumGPRSpills++;
694      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
695                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
696      ForceLRSpill = false;
697      ExtraCSSpill = true;
698    }
699
700    // Darwin ABI requires FP to point to the stack slot that contains the
701    // previous FP.
702    if (STI.isTargetDarwin() || hasFP(MF)) {
703      MF.getRegInfo().setPhysRegUsed(FramePtr);
704      NumGPRSpills++;
705    }
706
707    // If stack and double are 8-byte aligned and we are spilling an odd number
708    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
709    // the integer and double callee save areas.
710    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
711    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
712      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
713        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
714          unsigned Reg = UnspilledCS1GPRs[i];
715          // Don't spill high register if the function is thumb1
716          if (!AFI->isThumb1OnlyFunction() ||
717              isARMLowRegister(Reg) || Reg == ARM::LR) {
718            MF.getRegInfo().setPhysRegUsed(Reg);
719            AFI->setCSRegisterIsSpilled(Reg);
720            if (!isReservedReg(MF, Reg))
721              ExtraCSSpill = true;
722            break;
723          }
724        }
725      } else if (!UnspilledCS2GPRs.empty() &&
726                 !AFI->isThumb1OnlyFunction()) {
727        unsigned Reg = UnspilledCS2GPRs.front();
728        MF.getRegInfo().setPhysRegUsed(Reg);
729        AFI->setCSRegisterIsSpilled(Reg);
730        if (!isReservedReg(MF, Reg))
731          ExtraCSSpill = true;
732      }
733    }
734
735    // Estimate if we might need to scavenge a register at some point in order
736    // to materialize a stack offset. If so, either spill one additional
737    // callee-saved register or reserve a special spill slot to facilitate
738    // register scavenging. Thumb1 needs a spill slot for stack pointer
739    // adjustments also, even when the frame itself is small.
740    if (RS && !ExtraCSSpill) {
741      MachineFrameInfo  *MFI = MF.getFrameInfo();
742      // If any of the stack slot references may be out of range of an
743      // immediate offset, make sure a register (or a spill slot) is
744      // available for the register scavenger. Note that if we're indexing
745      // off the frame pointer, the effective stack size is 4 bytes larger
746      // since the FP points to the stack slot of the previous FP.
747      if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
748          >= estimateRSStackSizeLimit(MF)) {
749        // If any non-reserved CS register isn't spilled, just spill one or two
750        // extra. That should take care of it!
751        unsigned NumExtras = TargetAlign / 4;
752        SmallVector<unsigned, 2> Extras;
753        while (NumExtras && !UnspilledCS1GPRs.empty()) {
754          unsigned Reg = UnspilledCS1GPRs.back();
755          UnspilledCS1GPRs.pop_back();
756          if (!isReservedReg(MF, Reg)) {
757            Extras.push_back(Reg);
758            NumExtras--;
759          }
760        }
761        // For non-Thumb1 functions, also check for hi-reg CS registers
762        if (!AFI->isThumb1OnlyFunction()) {
763          while (NumExtras && !UnspilledCS2GPRs.empty()) {
764            unsigned Reg = UnspilledCS2GPRs.back();
765            UnspilledCS2GPRs.pop_back();
766            if (!isReservedReg(MF, Reg)) {
767              Extras.push_back(Reg);
768              NumExtras--;
769            }
770          }
771        }
772        if (Extras.size() && NumExtras == 0) {
773          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
774            MF.getRegInfo().setPhysRegUsed(Extras[i]);
775            AFI->setCSRegisterIsSpilled(Extras[i]);
776          }
777        } else if (!AFI->isThumb1OnlyFunction()) {
778          // note: Thumb1 functions spill to R12, not the stack.
779          // Reserve a slot closest to SP or frame pointer.
780          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
781          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
782                                                           RC->getAlignment()));
783        }
784      }
785    }
786  }
787
788  if (ForceLRSpill) {
789    MF.getRegInfo().setPhysRegUsed(ARM::LR);
790    AFI->setCSRegisterIsSpilled(ARM::LR);
791    AFI->setLRIsSpilledForFarJump(true);
792  }
793}
794
795unsigned ARMBaseRegisterInfo::getRARegister() const {
796  return ARM::LR;
797}
798
799unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
800  if (STI.isTargetDarwin() || hasFP(MF))
801    return FramePtr;
802  return ARM::SP;
803}
804
805unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
806  llvm_unreachable("What is the exception register");
807  return 0;
808}
809
810unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
811  llvm_unreachable("What is the exception handler register");
812  return 0;
813}
814
815int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
816  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
817}
818
819unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
820                                               const MachineFunction &MF) const {
821  switch (Reg) {
822  default: break;
823  // Return 0 if either register of the pair is a special register.
824  // So no R12, etc.
825  case ARM::R1:
826    return ARM::R0;
827  case ARM::R3:
828    return ARM::R2;
829  case ARM::R5:
830    return ARM::R4;
831  case ARM::R7:
832    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
833  case ARM::R9:
834    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
835  case ARM::R11:
836    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
837
838  case ARM::S1:
839    return ARM::S0;
840  case ARM::S3:
841    return ARM::S2;
842  case ARM::S5:
843    return ARM::S4;
844  case ARM::S7:
845    return ARM::S6;
846  case ARM::S9:
847    return ARM::S8;
848  case ARM::S11:
849    return ARM::S10;
850  case ARM::S13:
851    return ARM::S12;
852  case ARM::S15:
853    return ARM::S14;
854  case ARM::S17:
855    return ARM::S16;
856  case ARM::S19:
857    return ARM::S18;
858  case ARM::S21:
859    return ARM::S20;
860  case ARM::S23:
861    return ARM::S22;
862  case ARM::S25:
863    return ARM::S24;
864  case ARM::S27:
865    return ARM::S26;
866  case ARM::S29:
867    return ARM::S28;
868  case ARM::S31:
869    return ARM::S30;
870
871  case ARM::D1:
872    return ARM::D0;
873  case ARM::D3:
874    return ARM::D2;
875  case ARM::D5:
876    return ARM::D4;
877  case ARM::D7:
878    return ARM::D6;
879  case ARM::D9:
880    return ARM::D8;
881  case ARM::D11:
882    return ARM::D10;
883  case ARM::D13:
884    return ARM::D12;
885  case ARM::D15:
886    return ARM::D14;
887  case ARM::D17:
888    return ARM::D16;
889  case ARM::D19:
890    return ARM::D18;
891  case ARM::D21:
892    return ARM::D20;
893  case ARM::D23:
894    return ARM::D22;
895  case ARM::D25:
896    return ARM::D24;
897  case ARM::D27:
898    return ARM::D26;
899  case ARM::D29:
900    return ARM::D28;
901  case ARM::D31:
902    return ARM::D30;
903  }
904
905  return 0;
906}
907
908unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
909                                             const MachineFunction &MF) const {
910  switch (Reg) {
911  default: break;
912  // Return 0 if either register of the pair is a special register.
913  // So no R12, etc.
914  case ARM::R0:
915    return ARM::R1;
916  case ARM::R2:
917    return ARM::R3;
918  case ARM::R4:
919    return ARM::R5;
920  case ARM::R6:
921    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
922  case ARM::R8:
923    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
924  case ARM::R10:
925    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
926
927  case ARM::S0:
928    return ARM::S1;
929  case ARM::S2:
930    return ARM::S3;
931  case ARM::S4:
932    return ARM::S5;
933  case ARM::S6:
934    return ARM::S7;
935  case ARM::S8:
936    return ARM::S9;
937  case ARM::S10:
938    return ARM::S11;
939  case ARM::S12:
940    return ARM::S13;
941  case ARM::S14:
942    return ARM::S15;
943  case ARM::S16:
944    return ARM::S17;
945  case ARM::S18:
946    return ARM::S19;
947  case ARM::S20:
948    return ARM::S21;
949  case ARM::S22:
950    return ARM::S23;
951  case ARM::S24:
952    return ARM::S25;
953  case ARM::S26:
954    return ARM::S27;
955  case ARM::S28:
956    return ARM::S29;
957  case ARM::S30:
958    return ARM::S31;
959
960  case ARM::D0:
961    return ARM::D1;
962  case ARM::D2:
963    return ARM::D3;
964  case ARM::D4:
965    return ARM::D5;
966  case ARM::D6:
967    return ARM::D7;
968  case ARM::D8:
969    return ARM::D9;
970  case ARM::D10:
971    return ARM::D11;
972  case ARM::D12:
973    return ARM::D13;
974  case ARM::D14:
975    return ARM::D15;
976  case ARM::D16:
977    return ARM::D17;
978  case ARM::D18:
979    return ARM::D19;
980  case ARM::D20:
981    return ARM::D21;
982  case ARM::D22:
983    return ARM::D23;
984  case ARM::D24:
985    return ARM::D25;
986  case ARM::D26:
987    return ARM::D27;
988  case ARM::D28:
989    return ARM::D29;
990  case ARM::D30:
991    return ARM::D31;
992  }
993
994  return 0;
995}
996
997/// emitLoadConstPool - Emits a load from constpool to materialize the
998/// specified immediate.
999void ARMBaseRegisterInfo::
1000emitLoadConstPool(MachineBasicBlock &MBB,
1001                  MachineBasicBlock::iterator &MBBI,
1002                  DebugLoc dl,
1003                  unsigned DestReg, unsigned SubIdx, int Val,
1004                  ARMCC::CondCodes Pred,
1005                  unsigned PredReg) const {
1006  MachineFunction &MF = *MBB.getParent();
1007  MachineConstantPool *ConstantPool = MF.getConstantPool();
1008  Constant *C =
1009        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1010  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1011
1012  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1013    .addReg(DestReg, getDefRegState(true), SubIdx)
1014    .addConstantPoolIndex(Idx)
1015    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1016}
1017
1018bool ARMBaseRegisterInfo::
1019requiresRegisterScavenging(const MachineFunction &MF) const {
1020  return true;
1021}
1022
1023bool ARMBaseRegisterInfo::
1024requiresFrameIndexScavenging(const MachineFunction &MF) const {
1025  return true;
1026}
1027
1028// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1029// not required, we reserve argument space for call sites in the function
1030// immediately on entry to the current function. This eliminates the need for
1031// add/sub sp brackets around call sites. Returns true if the call frame is
1032// included as part of the stack frame.
1033bool ARMBaseRegisterInfo::
1034hasReservedCallFrame(MachineFunction &MF) const {
1035  const MachineFrameInfo *FFI = MF.getFrameInfo();
1036  unsigned CFSize = FFI->getMaxCallFrameSize();
1037  // It's not always a good idea to include the call frame as part of the
1038  // stack frame. ARM (especially Thumb) has small immediate offset to
1039  // address the stack frame. So a large call frame can cause poor codegen
1040  // and may even makes it impossible to scavenge a register.
1041  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1042    return false;
1043
1044  return !MF.getFrameInfo()->hasVarSizedObjects();
1045}
1046
1047static void
1048emitSPUpdate(bool isARM,
1049             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1050             DebugLoc dl, const ARMBaseInstrInfo &TII,
1051             int NumBytes,
1052             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1053  if (isARM)
1054    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1055                            Pred, PredReg, TII);
1056  else
1057    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1058                           Pred, PredReg, TII);
1059}
1060
1061
1062void ARMBaseRegisterInfo::
1063eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1064                              MachineBasicBlock::iterator I) const {
1065  if (!hasReservedCallFrame(MF)) {
1066    // If we have alloca, convert as follows:
1067    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1068    // ADJCALLSTACKUP   -> add, sp, sp, amount
1069    MachineInstr *Old = I;
1070    DebugLoc dl = Old->getDebugLoc();
1071    unsigned Amount = Old->getOperand(0).getImm();
1072    if (Amount != 0) {
1073      // We need to keep the stack aligned properly.  To do this, we round the
1074      // amount of space needed for the outgoing arguments up to the next
1075      // alignment boundary.
1076      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1077      Amount = (Amount+Align-1)/Align*Align;
1078
1079      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1080      assert(!AFI->isThumb1OnlyFunction() &&
1081             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
1082      bool isARM = !AFI->isThumbFunction();
1083
1084      // Replace the pseudo instruction with a new instruction...
1085      unsigned Opc = Old->getOpcode();
1086      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1087      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1088      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1089        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1090        unsigned PredReg = Old->getOperand(2).getReg();
1091        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1092      } else {
1093        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1094        unsigned PredReg = Old->getOperand(3).getReg();
1095        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1096        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1097      }
1098    }
1099  }
1100  MBB.erase(I);
1101}
1102
1103unsigned
1104ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1105                                         int SPAdj, int *Value,
1106                                         RegScavenger *RS) const {
1107  unsigned i = 0;
1108  MachineInstr &MI = *II;
1109  MachineBasicBlock &MBB = *MI.getParent();
1110  MachineFunction &MF = *MBB.getParent();
1111  const MachineFrameInfo *MFI = MF.getFrameInfo();
1112  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1113  assert(!AFI->isThumb1OnlyFunction() &&
1114         "This eliminateFrameIndex does not support Thumb1!");
1115
1116  while (!MI.getOperand(i).isFI()) {
1117    ++i;
1118    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1119  }
1120
1121  unsigned FrameReg = ARM::SP;
1122  int FrameIndex = MI.getOperand(i).getIndex();
1123  int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1124
1125  // When doing dynamic stack realignment, all of these need to change(?)
1126  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1127    Offset -= AFI->getGPRCalleeSavedArea1Offset();
1128  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1129    Offset -= AFI->getGPRCalleeSavedArea2Offset();
1130  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1131    Offset -= AFI->getDPRCalleeSavedAreaOffset();
1132  else if (needsStackRealignment(MF)) {
1133    // When dynamically realigning the stack, use the frame pointer for
1134    // parameters, and the stack pointer for locals.
1135    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1136    if (FrameIndex < 0) {
1137      FrameReg = getFrameRegister(MF);
1138      Offset -= AFI->getFramePtrSpillOffset();
1139      // When referencing from the frame pointer, stack pointer adjustments
1140      // don't matter.
1141      SPAdj = 0;
1142    }
1143  } else if (hasFP(MF) && AFI->hasStackFrame()) {
1144    assert(SPAdj == 0 && "Unexpected stack offset!");
1145    // Use frame pointer to reference fixed objects unless this is a
1146    // frameless function.
1147    FrameReg = getFrameRegister(MF);
1148    Offset -= AFI->getFramePtrSpillOffset();
1149  }
1150
1151  // modify MI as necessary to handle as much of 'Offset' as possible
1152  bool Done = false;
1153  if (!AFI->isThumbFunction())
1154    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1155  else {
1156    assert(AFI->isThumb2Function());
1157    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1158  }
1159  if (Done)
1160    return 0;
1161
1162  // If we get here, the immediate doesn't fit into the instruction.  We folded
1163  // as much as possible above, handle the rest, providing a register that is
1164  // SP+LargeImm.
1165  assert((Offset ||
1166          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1167         "This code isn't needed if offset already handled!");
1168
1169  unsigned ScratchReg = 0;
1170  int PIdx = MI.findFirstPredOperandIdx();
1171  ARMCC::CondCodes Pred = (PIdx == -1)
1172    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1173  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1174  if (Offset == 0)
1175    // Must be addrmode4.
1176    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1177  else {
1178    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1179    if (Value) *Value = Offset;
1180    if (!AFI->isThumbFunction())
1181      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1182                              Offset, Pred, PredReg, TII);
1183    else {
1184      assert(AFI->isThumb2Function());
1185      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1186                             Offset, Pred, PredReg, TII);
1187    }
1188    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1189    if (!ReuseFrameIndexVals)
1190      ScratchReg = 0;
1191  }
1192  return ScratchReg;
1193}
1194
1195/// Move iterator pass the next bunch of callee save load / store ops for
1196/// the particular spill area (1: integer area 1, 2: integer area 2,
1197/// 3: fp area, 0: don't care).
1198static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1199                                   MachineBasicBlock::iterator &MBBI,
1200                                   int Opc1, int Opc2, unsigned Area,
1201                                   const ARMSubtarget &STI) {
1202  while (MBBI != MBB.end() &&
1203         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1204         MBBI->getOperand(1).isFI()) {
1205    if (Area != 0) {
1206      bool Done = false;
1207      unsigned Category = 0;
1208      switch (MBBI->getOperand(0).getReg()) {
1209      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1210      case ARM::LR:
1211        Category = 1;
1212        break;
1213      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1214        Category = STI.isTargetDarwin() ? 2 : 1;
1215        break;
1216      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1217      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1218        Category = 3;
1219        break;
1220      default:
1221        Done = true;
1222        break;
1223      }
1224      if (Done || Category != Area)
1225        break;
1226    }
1227
1228    ++MBBI;
1229  }
1230}
1231
1232void ARMBaseRegisterInfo::
1233emitPrologue(MachineFunction &MF) const {
1234  MachineBasicBlock &MBB = MF.front();
1235  MachineBasicBlock::iterator MBBI = MBB.begin();
1236  MachineFrameInfo  *MFI = MF.getFrameInfo();
1237  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1238  assert(!AFI->isThumb1OnlyFunction() &&
1239         "This emitPrologue does not suppor Thumb1!");
1240  bool isARM = !AFI->isThumbFunction();
1241  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1242  unsigned NumBytes = MFI->getStackSize();
1243  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1244  DebugLoc dl = (MBBI != MBB.end() ?
1245                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1246
1247  // Determine the sizes of each callee-save spill areas and record which frame
1248  // belongs to which callee-save spill areas.
1249  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1250  int FramePtrSpillFI = 0;
1251
1252  // Allocate the vararg register save area. This is not counted in NumBytes.
1253  if (VARegSaveSize)
1254    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1255
1256  if (!AFI->hasStackFrame()) {
1257    if (NumBytes != 0)
1258      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1259    return;
1260  }
1261
1262  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1263    unsigned Reg = CSI[i].getReg();
1264    int FI = CSI[i].getFrameIdx();
1265    switch (Reg) {
1266    case ARM::R4:
1267    case ARM::R5:
1268    case ARM::R6:
1269    case ARM::R7:
1270    case ARM::LR:
1271      if (Reg == FramePtr)
1272        FramePtrSpillFI = FI;
1273      AFI->addGPRCalleeSavedArea1Frame(FI);
1274      GPRCS1Size += 4;
1275      break;
1276    case ARM::R8:
1277    case ARM::R9:
1278    case ARM::R10:
1279    case ARM::R11:
1280      if (Reg == FramePtr)
1281        FramePtrSpillFI = FI;
1282      if (STI.isTargetDarwin()) {
1283        AFI->addGPRCalleeSavedArea2Frame(FI);
1284        GPRCS2Size += 4;
1285      } else {
1286        AFI->addGPRCalleeSavedArea1Frame(FI);
1287        GPRCS1Size += 4;
1288      }
1289      break;
1290    default:
1291      AFI->addDPRCalleeSavedAreaFrame(FI);
1292      DPRCSSize += 8;
1293    }
1294  }
1295
1296  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1297  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1298  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1299
1300  // Set FP to point to the stack slot that contains the previous FP.
1301  // For Darwin, FP is R7, which has now been stored in spill area 1.
1302  // Otherwise, if this is not Darwin, all the callee-saved registers go
1303  // into spill area 1, including the FP in R11.  In either case, it is
1304  // now safe to emit this assignment.
1305  if (STI.isTargetDarwin() || hasFP(MF)) {
1306    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1307    MachineInstrBuilder MIB =
1308      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1309      .addFrameIndex(FramePtrSpillFI).addImm(0);
1310    AddDefaultCC(AddDefaultPred(MIB));
1311  }
1312
1313  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1314  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1315
1316  // Build the new SUBri to adjust SP for FP callee-save spill area.
1317  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1318  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1319
1320  // Determine starting offsets of spill areas.
1321  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1322  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1323  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1324  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1325  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1326  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1327  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1328
1329  NumBytes = DPRCSOffset;
1330  if (NumBytes) {
1331    // Insert it after all the callee-save spills.
1332    movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1333    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1334  }
1335
1336  if (STI.isTargetELF() && hasFP(MF)) {
1337    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1338                             AFI->getFramePtrSpillOffset());
1339  }
1340
1341  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1342  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1343  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1344
1345  // If we need dynamic stack realignment, do it here.
1346  if (needsStackRealignment(MF)) {
1347    unsigned Opc;
1348    unsigned MaxAlign = MFI->getMaxAlignment();
1349    assert (!AFI->isThumb1OnlyFunction());
1350    Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
1351
1352    AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP)
1353                                  .addReg(ARM::SP, RegState::Kill)
1354                                  .addImm(MaxAlign-1)));
1355  }
1356}
1357
1358static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1359  for (unsigned i = 0; CSRegs[i]; ++i)
1360    if (Reg == CSRegs[i])
1361      return true;
1362  return false;
1363}
1364
1365static bool isCSRestore(MachineInstr *MI,
1366                        const ARMBaseInstrInfo &TII,
1367                        const unsigned *CSRegs) {
1368  return ((MI->getOpcode() == (int)ARM::FLDD ||
1369           MI->getOpcode() == (int)ARM::LDR ||
1370           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1371          MI->getOperand(1).isFI() &&
1372          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1373}
1374
1375void ARMBaseRegisterInfo::
1376emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1377  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1378  assert(MBBI->getDesc().isReturn() &&
1379         "Can only insert epilog into returning blocks");
1380  DebugLoc dl = MBBI->getDebugLoc();
1381  MachineFrameInfo *MFI = MF.getFrameInfo();
1382  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1383  assert(!AFI->isThumb1OnlyFunction() &&
1384         "This emitEpilogue does not suppor Thumb1!");
1385  bool isARM = !AFI->isThumbFunction();
1386
1387  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1388  int NumBytes = (int)MFI->getStackSize();
1389
1390  if (!AFI->hasStackFrame()) {
1391    if (NumBytes != 0)
1392      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1393  } else {
1394    // Unwind MBBI to point to first LDR / FLDD.
1395    const unsigned *CSRegs = getCalleeSavedRegs();
1396    if (MBBI != MBB.begin()) {
1397      do
1398        --MBBI;
1399      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1400      if (!isCSRestore(MBBI, TII, CSRegs))
1401        ++MBBI;
1402    }
1403
1404    // Move SP to start of FP callee save spill area.
1405    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1406                 AFI->getGPRCalleeSavedArea2Size() +
1407                 AFI->getDPRCalleeSavedAreaSize());
1408
1409    // Darwin ABI requires FP to point to the stack slot that contains the
1410    // previous FP.
1411    bool HasFP = hasFP(MF);
1412    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1413      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1414      // Reset SP based on frame pointer only if the stack frame extends beyond
1415      // frame pointer stack slot or target is ELF and the function has FP.
1416      if (HasFP ||
1417          AFI->getGPRCalleeSavedArea2Size() ||
1418          AFI->getDPRCalleeSavedAreaSize()  ||
1419          AFI->getDPRCalleeSavedAreaOffset()) {
1420        if (NumBytes) {
1421          if (isARM)
1422            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1423                                    ARMCC::AL, 0, TII);
1424          else
1425            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1426                                    ARMCC::AL, 0, TII);
1427        } else {
1428          // Thumb2 or ARM.
1429          if (isARM)
1430            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1431              .addReg(FramePtr)
1432              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1433          else
1434            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1435              .addReg(FramePtr);
1436        }
1437      }
1438    } else if (NumBytes)
1439      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1440
1441    // Move SP to start of integer callee save spill area 2.
1442    movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1443    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1444
1445    // Move SP to start of integer callee save spill area 1.
1446    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1447    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1448
1449    // Move SP to SP upon entry to the function.
1450    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1451    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1452  }
1453
1454  if (VARegSaveSize)
1455    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1456}
1457
1458#include "ARMGenRegisterInfo.inc"
1459