ARMBaseRegisterInfo.cpp revision 8f310d978681b08e2e134a1d7b0433e43aa909f2 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMFrameLowering.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "MCTargetDesc/ARMAddressingModes.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameLowering.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "ARMGenRegisterInfo.inc"
44
45using namespace llvm;
46
47static cl::opt<bool>
48ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
49          cl::desc("Force use of virtual base registers for stack load/store"));
50static cl::opt<bool>
51EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
52          cl::desc("Enable pre-regalloc stack frame index allocation"));
53static cl::opt<bool>
54EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
58                                         const ARMSubtarget &sti)
59  : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
61    BasePtr(ARM::R6) {
62}
63
64const unsigned*
65ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66  static const unsigned CalleeSavedRegs[] = {
67    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
68    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
69
70    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
71    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
72    0
73  };
74
75  static const unsigned DarwinCalleeSavedRegs[] = {
76    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
77    // register.
78    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
79    ARM::R11, ARM::R10, ARM::R8,
80
81    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
82    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
83    0
84  };
85  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
86}
87
88BitVector ARMBaseRegisterInfo::
89getReservedRegs(const MachineFunction &MF) const {
90  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91
92  // FIXME: avoid re-calculating this every time.
93  BitVector Reserved(getNumRegs());
94  Reserved.set(ARM::SP);
95  Reserved.set(ARM::PC);
96  Reserved.set(ARM::FPSCR);
97  if (TFI->hasFP(MF))
98    Reserved.set(FramePtr);
99  if (hasBasePointer(MF))
100    Reserved.set(BasePtr);
101  // Some targets reserve R9.
102  if (STI.isR9Reserved())
103    Reserved.set(ARM::R9);
104  // Reserve D16-D31 if the subtarget doesn't support them.
105  if (!STI.hasVFP3() || STI.hasD16()) {
106    assert(ARM::D31 == ARM::D16 + 15);
107    for (unsigned i = 0; i != 16; ++i)
108      Reserved.set(ARM::D16 + i);
109  }
110  return Reserved;
111}
112
113bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
114                                        unsigned Reg) const {
115  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
116
117  switch (Reg) {
118  default: break;
119  case ARM::SP:
120  case ARM::PC:
121    return true;
122  case ARM::R6:
123    if (hasBasePointer(MF))
124      return true;
125    break;
126  case ARM::R7:
127  case ARM::R11:
128    if (FramePtr == Reg && TFI->hasFP(MF))
129      return true;
130    break;
131  case ARM::R9:
132    return STI.isR9Reserved();
133  }
134
135  return false;
136}
137
138const TargetRegisterClass *
139ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
140                                              const TargetRegisterClass *B,
141                                              unsigned SubIdx) const {
142  switch (SubIdx) {
143  default: return 0;
144  case ARM::ssub_0:
145  case ARM::ssub_1:
146  case ARM::ssub_2:
147  case ARM::ssub_3: {
148    // S sub-registers.
149    if (A->getSize() == 8) {
150      if (B == &ARM::SPR_8RegClass)
151        return &ARM::DPR_8RegClass;
152      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
153      if (A == &ARM::DPR_8RegClass)
154        return A;
155      return &ARM::DPR_VFP2RegClass;
156    }
157
158    if (A->getSize() == 16) {
159      if (B == &ARM::SPR_8RegClass)
160        return &ARM::QPR_8RegClass;
161      return &ARM::QPR_VFP2RegClass;
162    }
163
164    if (A->getSize() == 32) {
165      if (B == &ARM::SPR_8RegClass)
166        return 0;  // Do not allow coalescing!
167      return &ARM::QQPR_VFP2RegClass;
168    }
169
170    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
171    return 0;  // Do not allow coalescing!
172  }
173  case ARM::dsub_0:
174  case ARM::dsub_1:
175  case ARM::dsub_2:
176  case ARM::dsub_3: {
177    // D sub-registers.
178    if (A->getSize() == 16) {
179      if (B == &ARM::DPR_VFP2RegClass)
180        return &ARM::QPR_VFP2RegClass;
181      if (B == &ARM::DPR_8RegClass)
182        return 0;  // Do not allow coalescing!
183      return A;
184    }
185
186    if (A->getSize() == 32) {
187      if (B == &ARM::DPR_VFP2RegClass)
188        return &ARM::QQPR_VFP2RegClass;
189      if (B == &ARM::DPR_8RegClass)
190        return 0;  // Do not allow coalescing!
191      return A;
192    }
193
194    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
195    if (B != &ARM::DPRRegClass)
196      return 0;  // Do not allow coalescing!
197    return A;
198  }
199  case ARM::dsub_4:
200  case ARM::dsub_5:
201  case ARM::dsub_6:
202  case ARM::dsub_7: {
203    // D sub-registers of QQQQ registers.
204    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
205      return A;
206    return 0;  // Do not allow coalescing!
207  }
208
209  case ARM::qsub_0:
210  case ARM::qsub_1: {
211    // Q sub-registers.
212    if (A->getSize() == 32) {
213      if (B == &ARM::QPR_VFP2RegClass)
214        return &ARM::QQPR_VFP2RegClass;
215      if (B == &ARM::QPR_8RegClass)
216        return 0;  // Do not allow coalescing!
217      return A;
218    }
219
220    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
221    if (B == &ARM::QPRRegClass)
222      return A;
223    return 0;  // Do not allow coalescing!
224  }
225  case ARM::qsub_2:
226  case ARM::qsub_3: {
227    // Q sub-registers of QQQQ registers.
228    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
229      return A;
230    return 0;  // Do not allow coalescing!
231  }
232  }
233  return 0;
234}
235
236bool
237ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
238                                          SmallVectorImpl<unsigned> &SubIndices,
239                                          unsigned &NewSubIdx) const {
240
241  unsigned Size = RC->getSize() * 8;
242  if (Size < 6)
243    return 0;
244
245  NewSubIdx = 0;  // Whole register.
246  unsigned NumRegs = SubIndices.size();
247  if (NumRegs == 8) {
248    // 8 D registers -> 1 QQQQ register.
249    return (Size == 512 &&
250            SubIndices[0] == ARM::dsub_0 &&
251            SubIndices[1] == ARM::dsub_1 &&
252            SubIndices[2] == ARM::dsub_2 &&
253            SubIndices[3] == ARM::dsub_3 &&
254            SubIndices[4] == ARM::dsub_4 &&
255            SubIndices[5] == ARM::dsub_5 &&
256            SubIndices[6] == ARM::dsub_6 &&
257            SubIndices[7] == ARM::dsub_7);
258  } else if (NumRegs == 4) {
259    if (SubIndices[0] == ARM::qsub_0) {
260      // 4 Q registers -> 1 QQQQ register.
261      return (Size == 512 &&
262              SubIndices[1] == ARM::qsub_1 &&
263              SubIndices[2] == ARM::qsub_2 &&
264              SubIndices[3] == ARM::qsub_3);
265    } else if (SubIndices[0] == ARM::dsub_0) {
266      // 4 D registers -> 1 QQ register.
267      if (Size >= 256 &&
268          SubIndices[1] == ARM::dsub_1 &&
269          SubIndices[2] == ARM::dsub_2 &&
270          SubIndices[3] == ARM::dsub_3) {
271        if (Size == 512)
272          NewSubIdx = ARM::qqsub_0;
273        return true;
274      }
275    } else if (SubIndices[0] == ARM::dsub_4) {
276      // 4 D registers -> 1 QQ register (2nd).
277      if (Size == 512 &&
278          SubIndices[1] == ARM::dsub_5 &&
279          SubIndices[2] == ARM::dsub_6 &&
280          SubIndices[3] == ARM::dsub_7) {
281        NewSubIdx = ARM::qqsub_1;
282        return true;
283      }
284    } else if (SubIndices[0] == ARM::ssub_0) {
285      // 4 S registers -> 1 Q register.
286      if (Size >= 128 &&
287          SubIndices[1] == ARM::ssub_1 &&
288          SubIndices[2] == ARM::ssub_2 &&
289          SubIndices[3] == ARM::ssub_3) {
290        if (Size >= 256)
291          NewSubIdx = ARM::qsub_0;
292        return true;
293      }
294    }
295  } else if (NumRegs == 2) {
296    if (SubIndices[0] == ARM::qsub_0) {
297      // 2 Q registers -> 1 QQ register.
298      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
299        if (Size == 512)
300          NewSubIdx = ARM::qqsub_0;
301        return true;
302      }
303    } else if (SubIndices[0] == ARM::qsub_2) {
304      // 2 Q registers -> 1 QQ register (2nd).
305      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
306        NewSubIdx = ARM::qqsub_1;
307        return true;
308      }
309    } else if (SubIndices[0] == ARM::dsub_0) {
310      // 2 D registers -> 1 Q register.
311      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
312        if (Size >= 256)
313          NewSubIdx = ARM::qsub_0;
314        return true;
315      }
316    } else if (SubIndices[0] == ARM::dsub_2) {
317      // 2 D registers -> 1 Q register (2nd).
318      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
319        NewSubIdx = ARM::qsub_1;
320        return true;
321      }
322    } else if (SubIndices[0] == ARM::dsub_4) {
323      // 2 D registers -> 1 Q register (3rd).
324      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
325        NewSubIdx = ARM::qsub_2;
326        return true;
327      }
328    } else if (SubIndices[0] == ARM::dsub_6) {
329      // 2 D registers -> 1 Q register (3rd).
330      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
331        NewSubIdx = ARM::qsub_3;
332        return true;
333      }
334    } else if (SubIndices[0] == ARM::ssub_0) {
335      // 2 S registers -> 1 D register.
336      if (SubIndices[1] == ARM::ssub_1) {
337        if (Size >= 128)
338          NewSubIdx = ARM::dsub_0;
339        return true;
340      }
341    } else if (SubIndices[0] == ARM::ssub_2) {
342      // 2 S registers -> 1 D register (2nd).
343      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
344        NewSubIdx = ARM::dsub_1;
345        return true;
346      }
347    }
348  }
349  return false;
350}
351
352const TargetRegisterClass*
353ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
354                                                                         const {
355  const TargetRegisterClass *Super = RC;
356  TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
357  do {
358    switch (Super->getID()) {
359    case ARM::GPRRegClassID:
360    case ARM::SPRRegClassID:
361    case ARM::DPRRegClassID:
362    case ARM::QPRRegClassID:
363    case ARM::QQPRRegClassID:
364    case ARM::QQQQPRRegClassID:
365      return Super;
366    }
367    Super = *I++;
368  } while (Super);
369  return RC;
370}
371
372const TargetRegisterClass *
373ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
374  return ARM::GPRRegisterClass;
375}
376
377const TargetRegisterClass *
378ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
379  if (RC == &ARM::CCRRegClass)
380    return 0;  // Can't copy CCR registers.
381  return RC;
382}
383
384unsigned
385ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
386                                         MachineFunction &MF) const {
387  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
388
389  switch (RC->getID()) {
390  default:
391    return 0;
392  case ARM::tGPRRegClassID:
393    return TFI->hasFP(MF) ? 4 : 5;
394  case ARM::GPRRegClassID: {
395    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
396    return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
397  }
398  case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
399  case ARM::DPRRegClassID:
400    return 32 - 10;
401  }
402}
403
404/// getRawAllocationOrder - Returns the register allocation order for a
405/// specified register class with a target-dependent hint.
406ArrayRef<unsigned>
407ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
408                                           unsigned HintType, unsigned HintReg,
409                                           const MachineFunction &MF) const {
410  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
411  // Alternative register allocation orders when favoring even / odd registers
412  // of register pairs.
413
414  // No FP, R9 is available.
415  static const unsigned GPREven1[] = {
416    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
417    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
418    ARM::R9, ARM::R11
419  };
420  static const unsigned GPROdd1[] = {
421    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
422    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
423    ARM::R8, ARM::R10
424  };
425
426  // FP is R7, R9 is available.
427  static const unsigned GPREven2[] = {
428    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
429    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
430    ARM::R9, ARM::R11
431  };
432  static const unsigned GPROdd2[] = {
433    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
434    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
435    ARM::R8, ARM::R10
436  };
437
438  // FP is R11, R9 is available.
439  static const unsigned GPREven3[] = {
440    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
441    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
442    ARM::R9
443  };
444  static const unsigned GPROdd3[] = {
445    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
446    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
447    ARM::R8
448  };
449
450  // No FP, R9 is not available.
451  static const unsigned GPREven4[] = {
452    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
453    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
454    ARM::R11
455  };
456  static const unsigned GPROdd4[] = {
457    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
458    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
459    ARM::R10
460  };
461
462  // FP is R7, R9 is not available.
463  static const unsigned GPREven5[] = {
464    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
465    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
466    ARM::R11
467  };
468  static const unsigned GPROdd5[] = {
469    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
470    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
471    ARM::R10
472  };
473
474  // FP is R11, R9 is not available.
475  static const unsigned GPREven6[] = {
476    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
477    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
478  };
479  static const unsigned GPROdd6[] = {
480    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
481    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
482  };
483
484  // We only support even/odd hints for GPR and rGPR.
485  if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
486    return RC->getRawAllocationOrder(MF);
487
488  if (HintType == ARMRI::RegPairEven) {
489    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
490      // It's no longer possible to fulfill this hint. Return the default
491      // allocation order.
492      return RC->getRawAllocationOrder(MF);
493
494    if (!TFI->hasFP(MF)) {
495      if (!STI.isR9Reserved())
496        return makeArrayRef(GPREven1);
497      else
498        return makeArrayRef(GPREven4);
499    } else if (FramePtr == ARM::R7) {
500      if (!STI.isR9Reserved())
501        return makeArrayRef(GPREven2);
502      else
503        return makeArrayRef(GPREven5);
504    } else { // FramePtr == ARM::R11
505      if (!STI.isR9Reserved())
506        return makeArrayRef(GPREven3);
507      else
508        return makeArrayRef(GPREven6);
509    }
510  } else if (HintType == ARMRI::RegPairOdd) {
511    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
512      // It's no longer possible to fulfill this hint. Return the default
513      // allocation order.
514      return RC->getRawAllocationOrder(MF);
515
516    if (!TFI->hasFP(MF)) {
517      if (!STI.isR9Reserved())
518        return makeArrayRef(GPROdd1);
519      else
520        return makeArrayRef(GPROdd4);
521    } else if (FramePtr == ARM::R7) {
522      if (!STI.isR9Reserved())
523        return makeArrayRef(GPROdd2);
524      else
525        return makeArrayRef(GPROdd5);
526    } else { // FramePtr == ARM::R11
527      if (!STI.isR9Reserved())
528        return makeArrayRef(GPROdd3);
529      else
530        return makeArrayRef(GPROdd6);
531    }
532  }
533  return RC->getRawAllocationOrder(MF);
534}
535
536/// ResolveRegAllocHint - Resolves the specified register allocation hint
537/// to a physical register. Returns the physical register if it is successful.
538unsigned
539ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
540                                         const MachineFunction &MF) const {
541  if (Reg == 0 || !isPhysicalRegister(Reg))
542    return 0;
543  if (Type == 0)
544    return Reg;
545  else if (Type == (unsigned)ARMRI::RegPairOdd)
546    // Odd register.
547    return getRegisterPairOdd(Reg, MF);
548  else if (Type == (unsigned)ARMRI::RegPairEven)
549    // Even register.
550    return getRegisterPairEven(Reg, MF);
551  return 0;
552}
553
554void
555ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
556                                        MachineFunction &MF) const {
557  MachineRegisterInfo *MRI = &MF.getRegInfo();
558  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
559  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
560       Hint.first == (unsigned)ARMRI::RegPairEven) &&
561      TargetRegisterInfo::isVirtualRegister(Hint.second)) {
562    // If 'Reg' is one of the even / odd register pair and it's now changed
563    // (e.g. coalesced) into a different register. The other register of the
564    // pair allocation hint must be updated to reflect the relationship
565    // change.
566    unsigned OtherReg = Hint.second;
567    Hint = MRI->getRegAllocationHint(OtherReg);
568    if (Hint.second == Reg)
569      // Make sure the pair has not already divorced.
570      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
571  }
572}
573
574bool
575ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
576  // CortexA9 has a Write-after-write hazard for NEON registers.
577  if (!STI.isCortexA9())
578    return false;
579
580  switch (RC->getID()) {
581  case ARM::DPRRegClassID:
582  case ARM::DPR_8RegClassID:
583  case ARM::DPR_VFP2RegClassID:
584  case ARM::QPRRegClassID:
585  case ARM::QPR_8RegClassID:
586  case ARM::QPR_VFP2RegClassID:
587  case ARM::SPRRegClassID:
588  case ARM::SPR_8RegClassID:
589    // Avoid reusing S, D, and Q registers.
590    // Don't increase register pressure for QQ and QQQQ.
591    return true;
592  default:
593    return false;
594  }
595}
596
597bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
598  const MachineFrameInfo *MFI = MF.getFrameInfo();
599  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
600
601  if (!EnableBasePointer)
602    return false;
603
604  if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
605    return true;
606
607  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
608  // negative range for ldr/str (255), and thumb1 is positive offsets only.
609  // It's going to be better to use the SP or Base Pointer instead. When there
610  // are variable sized objects, we can't reference off of the SP, so we
611  // reserve a Base Pointer.
612  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
613    // Conservatively estimate whether the negative offset from the frame
614    // pointer will be sufficient to reach. If a function has a smallish
615    // frame, it's less likely to have lots of spills and callee saved
616    // space, so it's all more likely to be within range of the frame pointer.
617    // If it's wrong, the scavenger will still enable access to work, it just
618    // won't be optimal.
619    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
620      return false;
621    return true;
622  }
623
624  return false;
625}
626
627bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
628  const MachineFrameInfo *MFI = MF.getFrameInfo();
629  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
630  // We can't realign the stack if:
631  // 1. Dynamic stack realignment is explicitly disabled,
632  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
633  // 3. There are VLAs in the function and the base pointer is disabled.
634  return (RealignStack && !AFI->isThumb1OnlyFunction() &&
635          (!MFI->hasVarSizedObjects() || EnableBasePointer));
636}
637
638bool ARMBaseRegisterInfo::
639needsStackRealignment(const MachineFunction &MF) const {
640  const MachineFrameInfo *MFI = MF.getFrameInfo();
641  const Function *F = MF.getFunction();
642  unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
643  bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
644                               F->hasFnAttr(Attribute::StackAlignment));
645
646  return requiresRealignment && canRealignStack(MF);
647}
648
649bool ARMBaseRegisterInfo::
650cannotEliminateFrame(const MachineFunction &MF) const {
651  const MachineFrameInfo *MFI = MF.getFrameInfo();
652  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
653    return true;
654  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
655    || needsStackRealignment(MF);
656}
657
658unsigned
659ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
660  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
661
662  if (TFI->hasFP(MF))
663    return FramePtr;
664  return ARM::SP;
665}
666
667unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
668  llvm_unreachable("What is the exception register");
669  return 0;
670}
671
672unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
673  llvm_unreachable("What is the exception handler register");
674  return 0;
675}
676
677unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
678                                              const MachineFunction &MF) const {
679  switch (Reg) {
680  default: break;
681  // Return 0 if either register of the pair is a special register.
682  // So no R12, etc.
683  case ARM::R1: return ARM::R0;
684  case ARM::R3: return ARM::R2;
685  case ARM::R5: return ARM::R4;
686  case ARM::R7:
687    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
688      ? 0 : ARM::R6;
689  case ARM::R9: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
690  case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
691
692  case ARM::S1: return ARM::S0;
693  case ARM::S3: return ARM::S2;
694  case ARM::S5: return ARM::S4;
695  case ARM::S7: return ARM::S6;
696  case ARM::S9: return ARM::S8;
697  case ARM::S11: return ARM::S10;
698  case ARM::S13: return ARM::S12;
699  case ARM::S15: return ARM::S14;
700  case ARM::S17: return ARM::S16;
701  case ARM::S19: return ARM::S18;
702  case ARM::S21: return ARM::S20;
703  case ARM::S23: return ARM::S22;
704  case ARM::S25: return ARM::S24;
705  case ARM::S27: return ARM::S26;
706  case ARM::S29: return ARM::S28;
707  case ARM::S31: return ARM::S30;
708
709  case ARM::D1: return ARM::D0;
710  case ARM::D3: return ARM::D2;
711  case ARM::D5: return ARM::D4;
712  case ARM::D7: return ARM::D6;
713  case ARM::D9: return ARM::D8;
714  case ARM::D11: return ARM::D10;
715  case ARM::D13: return ARM::D12;
716  case ARM::D15: return ARM::D14;
717  case ARM::D17: return ARM::D16;
718  case ARM::D19: return ARM::D18;
719  case ARM::D21: return ARM::D20;
720  case ARM::D23: return ARM::D22;
721  case ARM::D25: return ARM::D24;
722  case ARM::D27: return ARM::D26;
723  case ARM::D29: return ARM::D28;
724  case ARM::D31: return ARM::D30;
725  }
726
727  return 0;
728}
729
730unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
731                                             const MachineFunction &MF) const {
732  switch (Reg) {
733  default: break;
734  // Return 0 if either register of the pair is a special register.
735  // So no R12, etc.
736  case ARM::R0: return ARM::R1;
737  case ARM::R2: return ARM::R3;
738  case ARM::R4: return ARM::R5;
739  case ARM::R6:
740    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
741      ? 0 : ARM::R7;
742  case ARM::R8: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
743  case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
744
745  case ARM::S0: return ARM::S1;
746  case ARM::S2: return ARM::S3;
747  case ARM::S4: return ARM::S5;
748  case ARM::S6: return ARM::S7;
749  case ARM::S8: return ARM::S9;
750  case ARM::S10: return ARM::S11;
751  case ARM::S12: return ARM::S13;
752  case ARM::S14: return ARM::S15;
753  case ARM::S16: return ARM::S17;
754  case ARM::S18: return ARM::S19;
755  case ARM::S20: return ARM::S21;
756  case ARM::S22: return ARM::S23;
757  case ARM::S24: return ARM::S25;
758  case ARM::S26: return ARM::S27;
759  case ARM::S28: return ARM::S29;
760  case ARM::S30: return ARM::S31;
761
762  case ARM::D0: return ARM::D1;
763  case ARM::D2: return ARM::D3;
764  case ARM::D4: return ARM::D5;
765  case ARM::D6: return ARM::D7;
766  case ARM::D8: return ARM::D9;
767  case ARM::D10: return ARM::D11;
768  case ARM::D12: return ARM::D13;
769  case ARM::D14: return ARM::D15;
770  case ARM::D16: return ARM::D17;
771  case ARM::D18: return ARM::D19;
772  case ARM::D20: return ARM::D21;
773  case ARM::D22: return ARM::D23;
774  case ARM::D24: return ARM::D25;
775  case ARM::D26: return ARM::D27;
776  case ARM::D28: return ARM::D29;
777  case ARM::D30: return ARM::D31;
778  }
779
780  return 0;
781}
782
783/// emitLoadConstPool - Emits a load from constpool to materialize the
784/// specified immediate.
785void ARMBaseRegisterInfo::
786emitLoadConstPool(MachineBasicBlock &MBB,
787                  MachineBasicBlock::iterator &MBBI,
788                  DebugLoc dl,
789                  unsigned DestReg, unsigned SubIdx, int Val,
790                  ARMCC::CondCodes Pred,
791                  unsigned PredReg, unsigned MIFlags) const {
792  MachineFunction &MF = *MBB.getParent();
793  MachineConstantPool *ConstantPool = MF.getConstantPool();
794  const Constant *C =
795        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
796  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
797
798  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
799    .addReg(DestReg, getDefRegState(true), SubIdx)
800    .addConstantPoolIndex(Idx)
801    .addImm(0).addImm(Pred).addReg(PredReg)
802    .setMIFlags(MIFlags);
803}
804
805bool ARMBaseRegisterInfo::
806requiresRegisterScavenging(const MachineFunction &MF) const {
807  return true;
808}
809
810bool ARMBaseRegisterInfo::
811requiresFrameIndexScavenging(const MachineFunction &MF) const {
812  return true;
813}
814
815bool ARMBaseRegisterInfo::
816requiresVirtualBaseRegisters(const MachineFunction &MF) const {
817  return EnableLocalStackAlloc;
818}
819
820static void
821emitSPUpdate(bool isARM,
822             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
823             DebugLoc dl, const ARMBaseInstrInfo &TII,
824             int NumBytes,
825             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
826  if (isARM)
827    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
828                            Pred, PredReg, TII);
829  else
830    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
831                           Pred, PredReg, TII);
832}
833
834
835void ARMBaseRegisterInfo::
836eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
837                              MachineBasicBlock::iterator I) const {
838  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
839  if (!TFI->hasReservedCallFrame(MF)) {
840    // If we have alloca, convert as follows:
841    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
842    // ADJCALLSTACKUP   -> add, sp, sp, amount
843    MachineInstr *Old = I;
844    DebugLoc dl = Old->getDebugLoc();
845    unsigned Amount = Old->getOperand(0).getImm();
846    if (Amount != 0) {
847      // We need to keep the stack aligned properly.  To do this, we round the
848      // amount of space needed for the outgoing arguments up to the next
849      // alignment boundary.
850      unsigned Align = TFI->getStackAlignment();
851      Amount = (Amount+Align-1)/Align*Align;
852
853      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
854      assert(!AFI->isThumb1OnlyFunction() &&
855             "This eliminateCallFramePseudoInstr does not support Thumb1!");
856      bool isARM = !AFI->isThumbFunction();
857
858      // Replace the pseudo instruction with a new instruction...
859      unsigned Opc = Old->getOpcode();
860      int PIdx = Old->findFirstPredOperandIdx();
861      ARMCC::CondCodes Pred = (PIdx == -1)
862        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
863      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
864        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
865        unsigned PredReg = Old->getOperand(2).getReg();
866        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
867      } else {
868        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
869        unsigned PredReg = Old->getOperand(3).getReg();
870        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
871        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
872      }
873    }
874  }
875  MBB.erase(I);
876}
877
878int64_t ARMBaseRegisterInfo::
879getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
880  const MCInstrDesc &Desc = MI->getDesc();
881  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
882  int64_t InstrOffs = 0;;
883  int Scale = 1;
884  unsigned ImmIdx = 0;
885  switch (AddrMode) {
886  case ARMII::AddrModeT2_i8:
887  case ARMII::AddrModeT2_i12:
888  case ARMII::AddrMode_i12:
889    InstrOffs = MI->getOperand(Idx+1).getImm();
890    Scale = 1;
891    break;
892  case ARMII::AddrMode5: {
893    // VFP address mode.
894    const MachineOperand &OffOp = MI->getOperand(Idx+1);
895    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
896    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
897      InstrOffs = -InstrOffs;
898    Scale = 4;
899    break;
900  }
901  case ARMII::AddrMode2: {
902    ImmIdx = Idx+2;
903    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
904    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
905      InstrOffs = -InstrOffs;
906    break;
907  }
908  case ARMII::AddrMode3: {
909    ImmIdx = Idx+2;
910    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
911    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
912      InstrOffs = -InstrOffs;
913    break;
914  }
915  case ARMII::AddrModeT1_s: {
916    ImmIdx = Idx+1;
917    InstrOffs = MI->getOperand(ImmIdx).getImm();
918    Scale = 4;
919    break;
920  }
921  default:
922    llvm_unreachable("Unsupported addressing mode!");
923    break;
924  }
925
926  return InstrOffs * Scale;
927}
928
929/// needsFrameBaseReg - Returns true if the instruction's frame index
930/// reference would be better served by a base register other than FP
931/// or SP. Used by LocalStackFrameAllocation to determine which frame index
932/// references it should create new base registers for.
933bool ARMBaseRegisterInfo::
934needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
935  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
936    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
937  }
938
939  // It's the load/store FI references that cause issues, as it can be difficult
940  // to materialize the offset if it won't fit in the literal field. Estimate
941  // based on the size of the local frame and some conservative assumptions
942  // about the rest of the stack frame (note, this is pre-regalloc, so
943  // we don't know everything for certain yet) whether this offset is likely
944  // to be out of range of the immediate. Return true if so.
945
946  // We only generate virtual base registers for loads and stores, so
947  // return false for everything else.
948  unsigned Opc = MI->getOpcode();
949  switch (Opc) {
950  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
951  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
952  case ARM::t2LDRi12: case ARM::t2LDRi8:
953  case ARM::t2STRi12: case ARM::t2STRi8:
954  case ARM::VLDRS: case ARM::VLDRD:
955  case ARM::VSTRS: case ARM::VSTRD:
956  case ARM::tSTRspi: case ARM::tLDRspi:
957    if (ForceAllBaseRegAlloc)
958      return true;
959    break;
960  default:
961    return false;
962  }
963
964  // Without a virtual base register, if the function has variable sized
965  // objects, all fixed-size local references will be via the frame pointer,
966  // Approximate the offset and see if it's legal for the instruction.
967  // Note that the incoming offset is based on the SP value at function entry,
968  // so it'll be negative.
969  MachineFunction &MF = *MI->getParent()->getParent();
970  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
971  MachineFrameInfo *MFI = MF.getFrameInfo();
972  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
973
974  // Estimate an offset from the frame pointer.
975  // Conservatively assume all callee-saved registers get pushed. R4-R6
976  // will be earlier than the FP, so we ignore those.
977  // R7, LR
978  int64_t FPOffset = Offset - 8;
979  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
980  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
981    FPOffset -= 80;
982  // Estimate an offset from the stack pointer.
983  // The incoming offset is relating to the SP at the start of the function,
984  // but when we access the local it'll be relative to the SP after local
985  // allocation, so adjust our SP-relative offset by that allocation size.
986  Offset = -Offset;
987  Offset += MFI->getLocalFrameSize();
988  // Assume that we'll have at least some spill slots allocated.
989  // FIXME: This is a total SWAG number. We should run some statistics
990  //        and pick a real one.
991  Offset += 128; // 128 bytes of spill slots
992
993  // If there is a frame pointer, try using it.
994  // The FP is only available if there is no dynamic realignment. We
995  // don't know for sure yet whether we'll need that, so we guess based
996  // on whether there are any local variables that would trigger it.
997  unsigned StackAlign = TFI->getStackAlignment();
998  if (TFI->hasFP(MF) &&
999      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1000    if (isFrameOffsetLegal(MI, FPOffset))
1001      return false;
1002  }
1003  // If we can reference via the stack pointer, try that.
1004  // FIXME: This (and the code that resolves the references) can be improved
1005  //        to only disallow SP relative references in the live range of
1006  //        the VLA(s). In practice, it's unclear how much difference that
1007  //        would make, but it may be worth doing.
1008  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1009    return false;
1010
1011  // The offset likely isn't legal, we want to allocate a virtual base register.
1012  return true;
1013}
1014
1015/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
1016/// be a pointer to FrameIdx at the beginning of the basic block.
1017void ARMBaseRegisterInfo::
1018materializeFrameBaseRegister(MachineBasicBlock *MBB,
1019                             unsigned BaseReg, int FrameIdx,
1020                             int64_t Offset) const {
1021  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
1022  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1023    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1024
1025  MachineBasicBlock::iterator Ins = MBB->begin();
1026  DebugLoc DL;                  // Defaults to "unknown"
1027  if (Ins != MBB->end())
1028    DL = Ins->getDebugLoc();
1029
1030  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1031  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1032  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
1033
1034  MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1035    .addFrameIndex(FrameIdx).addImm(Offset));
1036
1037  if (!AFI->isThumb1OnlyFunction())
1038    AddDefaultCC(MIB);
1039}
1040
1041void
1042ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1043                                       unsigned BaseReg, int64_t Offset) const {
1044  MachineInstr &MI = *I;
1045  MachineBasicBlock &MBB = *MI.getParent();
1046  MachineFunction &MF = *MBB.getParent();
1047  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1048  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1049  unsigned i = 0;
1050
1051  assert(!AFI->isThumb1OnlyFunction() &&
1052         "This resolveFrameIndex does not support Thumb1!");
1053
1054  while (!MI.getOperand(i).isFI()) {
1055    ++i;
1056    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1057  }
1058  bool Done = false;
1059  if (!AFI->isThumbFunction())
1060    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1061  else {
1062    assert(AFI->isThumb2Function());
1063    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1064  }
1065  assert (Done && "Unable to resolve frame index!");
1066  (void)Done;
1067}
1068
1069bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1070                                             int64_t Offset) const {
1071  const MCInstrDesc &Desc = MI->getDesc();
1072  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1073  unsigned i = 0;
1074
1075  while (!MI->getOperand(i).isFI()) {
1076    ++i;
1077    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1078  }
1079
1080  // AddrMode4 and AddrMode6 cannot handle any offset.
1081  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1082    return Offset == 0;
1083
1084  unsigned NumBits = 0;
1085  unsigned Scale = 1;
1086  bool isSigned = true;
1087  switch (AddrMode) {
1088  case ARMII::AddrModeT2_i8:
1089  case ARMII::AddrModeT2_i12:
1090    // i8 supports only negative, and i12 supports only positive, so
1091    // based on Offset sign, consider the appropriate instruction
1092    Scale = 1;
1093    if (Offset < 0) {
1094      NumBits = 8;
1095      Offset = -Offset;
1096    } else {
1097      NumBits = 12;
1098    }
1099    break;
1100  case ARMII::AddrMode5:
1101    // VFP address mode.
1102    NumBits = 8;
1103    Scale = 4;
1104    break;
1105  case ARMII::AddrMode_i12:
1106  case ARMII::AddrMode2:
1107    NumBits = 12;
1108    break;
1109  case ARMII::AddrMode3:
1110    NumBits = 8;
1111    break;
1112  case ARMII::AddrModeT1_s:
1113    NumBits = 5;
1114    Scale = 4;
1115    isSigned = false;
1116    break;
1117  default:
1118    llvm_unreachable("Unsupported addressing mode!");
1119    break;
1120  }
1121
1122  Offset += getFrameIndexInstrOffset(MI, i);
1123  // Make sure the offset is encodable for instructions that scale the
1124  // immediate.
1125  if ((Offset & (Scale-1)) != 0)
1126    return false;
1127
1128  if (isSigned && Offset < 0)
1129    Offset = -Offset;
1130
1131  unsigned Mask = (1 << NumBits) - 1;
1132  if ((unsigned)Offset <= Mask * Scale)
1133    return true;
1134
1135  return false;
1136}
1137
1138void
1139ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1140                                         int SPAdj, RegScavenger *RS) const {
1141  unsigned i = 0;
1142  MachineInstr &MI = *II;
1143  MachineBasicBlock &MBB = *MI.getParent();
1144  MachineFunction &MF = *MBB.getParent();
1145  const ARMFrameLowering *TFI =
1146    static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1147  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1148  assert(!AFI->isThumb1OnlyFunction() &&
1149         "This eliminateFrameIndex does not support Thumb1!");
1150
1151  while (!MI.getOperand(i).isFI()) {
1152    ++i;
1153    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1154  }
1155
1156  int FrameIndex = MI.getOperand(i).getIndex();
1157  unsigned FrameReg;
1158
1159  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1160
1161  // Special handling of dbg_value instructions.
1162  if (MI.isDebugValue()) {
1163    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1164    MI.getOperand(i+1).ChangeToImmediate(Offset);
1165    return;
1166  }
1167
1168  // Modify MI as necessary to handle as much of 'Offset' as possible
1169  bool Done = false;
1170  if (!AFI->isThumbFunction())
1171    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1172  else {
1173    assert(AFI->isThumb2Function());
1174    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1175  }
1176  if (Done)
1177    return;
1178
1179  // If we get here, the immediate doesn't fit into the instruction.  We folded
1180  // as much as possible above, handle the rest, providing a register that is
1181  // SP+LargeImm.
1182  assert((Offset ||
1183          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1184          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1185         "This code isn't needed if offset already handled!");
1186
1187  unsigned ScratchReg = 0;
1188  int PIdx = MI.findFirstPredOperandIdx();
1189  ARMCC::CondCodes Pred = (PIdx == -1)
1190    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1191  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1192  if (Offset == 0)
1193    // Must be addrmode4/6.
1194    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1195  else {
1196    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1197    if (!AFI->isThumbFunction())
1198      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1199                              Offset, Pred, PredReg, TII);
1200    else {
1201      assert(AFI->isThumb2Function());
1202      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1203                             Offset, Pred, PredReg, TII);
1204    }
1205    // Update the original instruction to use the scratch register.
1206    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1207  }
1208}
1209