ARMBaseRegisterInfo.cpp revision 9adc0abad3c3ed40a268ccbcee0c74cb9e1359fe 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/SmallVector.h"
39using namespace llvm;
40
41unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
42  using namespace ARM;
43  switch (RegEnum) {
44  case R0:  case S0:  case D0:  return 0;
45  case R1:  case S1:  case D1:  return 1;
46  case R2:  case S2:  case D2:  return 2;
47  case R3:  case S3:  case D3:  return 3;
48  case R4:  case S4:  case D4:  return 4;
49  case R5:  case S5:  case D5:  return 5;
50  case R6:  case S6:  case D6:  return 6;
51  case R7:  case S7:  case D7:  return 7;
52  case R8:  case S8:  case D8:  return 8;
53  case R9:  case S9:  case D9:  return 9;
54  case R10: case S10: case D10: return 10;
55  case R11: case S11: case D11: return 11;
56  case R12: case S12: case D12: return 12;
57  case SP:  case S13: case D13: return 13;
58  case LR:  case S14: case D14: return 14;
59  case PC:  case S15: case D15: return 15;
60  case S16: return 16;
61  case S17: return 17;
62  case S18: return 18;
63  case S19: return 19;
64  case S20: return 20;
65  case S21: return 21;
66  case S22: return 22;
67  case S23: return 23;
68  case S24: return 24;
69  case S25: return 25;
70  case S26: return 26;
71  case S27: return 27;
72  case S28: return 28;
73  case S29: return 29;
74  case S30: return 30;
75  case S31: return 31;
76  default:
77    llvm_unreachable("Unknown ARM register!");
78  }
79}
80
81unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
82                                                   bool &isSPVFP) {
83  isSPVFP = false;
84
85  using namespace ARM;
86  switch (RegEnum) {
87  default:
88    llvm_unreachable("Unknown ARM register!");
89  case R0:  case D0:  return 0;
90  case R1:  case D1:  return 1;
91  case R2:  case D2:  return 2;
92  case R3:  case D3:  return 3;
93  case R4:  case D4:  return 4;
94  case R5:  case D5:  return 5;
95  case R6:  case D6:  return 6;
96  case R7:  case D7:  return 7;
97  case R8:  case D8:  return 8;
98  case R9:  case D9:  return 9;
99  case R10: case D10: return 10;
100  case R11: case D11: return 11;
101  case R12: case D12: return 12;
102  case SP:  case D13: return 13;
103  case LR:  case D14: return 14;
104  case PC:  case D15: return 15;
105
106  case S0: case S1: case S2: case S3:
107  case S4: case S5: case S6: case S7:
108  case S8: case S9: case S10: case S11:
109  case S12: case S13: case S14: case S15:
110  case S16: case S17: case S18: case S19:
111  case S20: case S21: case S22: case S23:
112  case S24: case S25: case S26: case S27:
113  case S28: case S29: case S30: case S31:  {
114    isSPVFP = true;
115    switch (RegEnum) {
116    default: return 0; // Avoid compile time warning.
117    case S0: return 0;
118    case S1: return 1;
119    case S2: return 2;
120    case S3: return 3;
121    case S4: return 4;
122    case S5: return 5;
123    case S6: return 6;
124    case S7: return 7;
125    case S8: return 8;
126    case S9: return 9;
127    case S10: return 10;
128    case S11: return 11;
129    case S12: return 12;
130    case S13: return 13;
131    case S14: return 14;
132    case S15: return 15;
133    case S16: return 16;
134    case S17: return 17;
135    case S18: return 18;
136    case S19: return 19;
137    case S20: return 20;
138    case S21: return 21;
139    case S22: return 22;
140    case S23: return 23;
141    case S24: return 24;
142    case S25: return 25;
143    case S26: return 26;
144    case S27: return 27;
145    case S28: return 28;
146    case S29: return 29;
147    case S30: return 30;
148    case S31: return 31;
149    }
150  }
151  }
152}
153
154ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
155                                         const ARMSubtarget &sti)
156  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
157    TII(tii), STI(sti),
158    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
159}
160
161unsigned ARMBaseRegisterInfo::
162getOpcode(int Op) const {
163  return TII.getOpcode((ARMII::Op)Op);
164}
165
166const unsigned*
167ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
168  static const unsigned CalleeSavedRegs[] = {
169    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
170    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
171
172    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
173    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
174    0
175  };
176
177  static const unsigned DarwinCalleeSavedRegs[] = {
178    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
179    // register.
180    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
181    ARM::R11, ARM::R10, ARM::R8,
182
183    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
184    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
185    0
186  };
187  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
188}
189
190const TargetRegisterClass* const *
191ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
192  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
193    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
194    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
195    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
196
197    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
198    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
199    0
200  };
201
202  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
203    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
204    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
205    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
206
207    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
208    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
209    0
210  };
211
212  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
213    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
214    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
215    &ARM::GPRRegClass, &ARM::GPRRegClass,
216
217    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
218    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
219    0
220  };
221
222  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
223    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
224    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
225    &ARM::GPRRegClass,  &ARM::GPRRegClass,
226
227    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
228    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
229    0
230  };
231
232  if (STI.isThumb1Only()) {
233    return STI.isTargetDarwin()
234      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
235  }
236  return STI.isTargetDarwin()
237    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
238}
239
240BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
241  // FIXME: avoid re-calculating this everytime.
242  BitVector Reserved(getNumRegs());
243  Reserved.set(ARM::SP);
244  Reserved.set(ARM::PC);
245  if (STI.isTargetDarwin() || hasFP(MF))
246    Reserved.set(FramePtr);
247  // Some targets reserve R9.
248  if (STI.isR9Reserved())
249    Reserved.set(ARM::R9);
250  return Reserved;
251}
252
253bool
254ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
255  switch (Reg) {
256  default: break;
257  case ARM::SP:
258  case ARM::PC:
259    return true;
260  case ARM::R7:
261  case ARM::R11:
262    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
263      return true;
264    break;
265  case ARM::R9:
266    return STI.isR9Reserved();
267  }
268
269  return false;
270}
271
272const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const {
273  return &ARM::GPRRegClass;
274}
275
276/// getAllocationOrder - Returns the register allocation order for a specified
277/// register class in the form of a pair of TargetRegisterClass iterators.
278std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
279ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
280                                        unsigned HintType, unsigned HintReg,
281                                        const MachineFunction &MF) const {
282  // Alternative register allocation orders when favoring even / odd registers
283  // of register pairs.
284
285  // No FP, R9 is available.
286  static const unsigned GPREven1[] = {
287    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
288    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
289    ARM::R9, ARM::R11
290  };
291  static const unsigned GPROdd1[] = {
292    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
293    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
294    ARM::R8, ARM::R10
295  };
296
297  // FP is R7, R9 is available.
298  static const unsigned GPREven2[] = {
299    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
300    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
301    ARM::R9, ARM::R11
302  };
303  static const unsigned GPROdd2[] = {
304    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
305    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
306    ARM::R8, ARM::R10
307  };
308
309  // FP is R11, R9 is available.
310  static const unsigned GPREven3[] = {
311    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
312    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
313    ARM::R9
314  };
315  static const unsigned GPROdd3[] = {
316    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
317    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
318    ARM::R8
319  };
320
321  // No FP, R9 is not available.
322  static const unsigned GPREven4[] = {
323    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
324    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
325    ARM::R11
326  };
327  static const unsigned GPROdd4[] = {
328    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
329    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
330    ARM::R10
331  };
332
333  // FP is R7, R9 is not available.
334  static const unsigned GPREven5[] = {
335    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
336    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
337    ARM::R11
338  };
339  static const unsigned GPROdd5[] = {
340    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
341    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
342    ARM::R10
343  };
344
345  // FP is R11, R9 is not available.
346  static const unsigned GPREven6[] = {
347    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
348    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
349  };
350  static const unsigned GPROdd6[] = {
351    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
352    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
353  };
354
355
356  if (HintType == ARMRI::RegPairEven) {
357    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
358      // It's no longer possible to fulfill this hint. Return the default
359      // allocation order.
360      return std::make_pair(RC->allocation_order_begin(MF),
361                            RC->allocation_order_end(MF));
362
363    if (!STI.isTargetDarwin() && !hasFP(MF)) {
364      if (!STI.isR9Reserved())
365        return std::make_pair(GPREven1,
366                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
367      else
368        return std::make_pair(GPREven4,
369                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
370    } else if (FramePtr == ARM::R7) {
371      if (!STI.isR9Reserved())
372        return std::make_pair(GPREven2,
373                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
374      else
375        return std::make_pair(GPREven5,
376                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
377    } else { // FramePtr == ARM::R11
378      if (!STI.isR9Reserved())
379        return std::make_pair(GPREven3,
380                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
381      else
382        return std::make_pair(GPREven6,
383                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
384    }
385  } else if (HintType == ARMRI::RegPairOdd) {
386    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
387      // It's no longer possible to fulfill this hint. Return the default
388      // allocation order.
389      return std::make_pair(RC->allocation_order_begin(MF),
390                            RC->allocation_order_end(MF));
391
392    if (!STI.isTargetDarwin() && !hasFP(MF)) {
393      if (!STI.isR9Reserved())
394        return std::make_pair(GPROdd1,
395                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
396      else
397        return std::make_pair(GPROdd4,
398                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
399    } else if (FramePtr == ARM::R7) {
400      if (!STI.isR9Reserved())
401        return std::make_pair(GPROdd2,
402                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
403      else
404        return std::make_pair(GPROdd5,
405                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
406    } else { // FramePtr == ARM::R11
407      if (!STI.isR9Reserved())
408        return std::make_pair(GPROdd3,
409                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
410      else
411        return std::make_pair(GPROdd6,
412                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
413    }
414  }
415  return std::make_pair(RC->allocation_order_begin(MF),
416                        RC->allocation_order_end(MF));
417}
418
419/// ResolveRegAllocHint - Resolves the specified register allocation hint
420/// to a physical register. Returns the physical register if it is successful.
421unsigned
422ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
423                                         const MachineFunction &MF) const {
424  if (Reg == 0 || !isPhysicalRegister(Reg))
425    return 0;
426  if (Type == 0)
427    return Reg;
428  else if (Type == (unsigned)ARMRI::RegPairOdd)
429    // Odd register.
430    return getRegisterPairOdd(Reg, MF);
431  else if (Type == (unsigned)ARMRI::RegPairEven)
432    // Even register.
433    return getRegisterPairEven(Reg, MF);
434  return 0;
435}
436
437void
438ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
439                                        MachineFunction &MF) const {
440  MachineRegisterInfo *MRI = &MF.getRegInfo();
441  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
442  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
443       Hint.first == (unsigned)ARMRI::RegPairEven) &&
444      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
445    // If 'Reg' is one of the even / odd register pair and it's now changed
446    // (e.g. coalesced) into a different register. The other register of the
447    // pair allocation hint must be updated to reflect the relationship
448    // change.
449    unsigned OtherReg = Hint.second;
450    Hint = MRI->getRegAllocationHint(OtherReg);
451    if (Hint.second == Reg)
452      // Make sure the pair has not already divorced.
453      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
454  }
455}
456
457/// hasFP - Return true if the specified function should have a dedicated frame
458/// pointer register.  This is true if the function has variable sized allocas
459/// or if frame pointer elimination is disabled.
460///
461bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
462  const MachineFrameInfo *MFI = MF.getFrameInfo();
463  return (NoFramePointerElim ||
464          MFI->hasVarSizedObjects() ||
465          MFI->isFrameAddressTaken());
466}
467
468static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
469  const MachineFrameInfo *FFI = MF.getFrameInfo();
470  int Offset = 0;
471  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
472    int FixedOff = -FFI->getObjectOffset(i);
473    if (FixedOff > Offset) Offset = FixedOff;
474  }
475  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
476    if (FFI->isDeadObjectIndex(i))
477      continue;
478    Offset += FFI->getObjectSize(i);
479    unsigned Align = FFI->getObjectAlignment(i);
480    // Adjust to alignment boundary
481    Offset = (Offset+Align-1)/Align*Align;
482  }
483  return (unsigned)Offset;
484}
485
486void
487ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
488                                                          RegScavenger *RS) const {
489  // This tells PEI to spill the FP as if it is any other callee-save register
490  // to take advantage the eliminateFrameIndex machinery. This also ensures it
491  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
492  // to combine multiple loads / stores.
493  bool CanEliminateFrame = true;
494  bool CS1Spilled = false;
495  bool LRSpilled = false;
496  unsigned NumGPRSpills = 0;
497  SmallVector<unsigned, 4> UnspilledCS1GPRs;
498  SmallVector<unsigned, 4> UnspilledCS2GPRs;
499  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
500
501  // Don't spill FP if the frame can be eliminated. This is determined
502  // by scanning the callee-save registers to see if any is used.
503  const unsigned *CSRegs = getCalleeSavedRegs();
504  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
505  for (unsigned i = 0; CSRegs[i]; ++i) {
506    unsigned Reg = CSRegs[i];
507    bool Spilled = false;
508    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
509      AFI->setCSRegisterIsSpilled(Reg);
510      Spilled = true;
511      CanEliminateFrame = false;
512    } else {
513      // Check alias registers too.
514      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
515        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
516          Spilled = true;
517          CanEliminateFrame = false;
518        }
519      }
520    }
521
522    if (CSRegClasses[i] == &ARM::GPRRegClass) {
523      if (Spilled) {
524        NumGPRSpills++;
525
526        if (!STI.isTargetDarwin()) {
527          if (Reg == ARM::LR)
528            LRSpilled = true;
529          CS1Spilled = true;
530          continue;
531        }
532
533        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
534        switch (Reg) {
535        case ARM::LR:
536          LRSpilled = true;
537          // Fallthrough
538        case ARM::R4:
539        case ARM::R5:
540        case ARM::R6:
541        case ARM::R7:
542          CS1Spilled = true;
543          break;
544        default:
545          break;
546        }
547      } else {
548        if (!STI.isTargetDarwin()) {
549          UnspilledCS1GPRs.push_back(Reg);
550          continue;
551        }
552
553        switch (Reg) {
554        case ARM::R4:
555        case ARM::R5:
556        case ARM::R6:
557        case ARM::R7:
558        case ARM::LR:
559          UnspilledCS1GPRs.push_back(Reg);
560          break;
561        default:
562          UnspilledCS2GPRs.push_back(Reg);
563          break;
564        }
565      }
566    }
567  }
568
569  bool ForceLRSpill = false;
570  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
571    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
572    // Force LR to be spilled if the Thumb function size is > 2048. This enables
573    // use of BL to implement far jump. If it turns out that it's not needed
574    // then the branch fix up path will undo it.
575    if (FnSize >= (1 << 11)) {
576      CanEliminateFrame = false;
577      ForceLRSpill = true;
578    }
579  }
580
581  bool ExtraCSSpill = false;
582  if (!CanEliminateFrame || hasFP(MF)) {
583    AFI->setHasStackFrame(true);
584
585    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
586    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
587    if (!LRSpilled && CS1Spilled) {
588      MF.getRegInfo().setPhysRegUsed(ARM::LR);
589      AFI->setCSRegisterIsSpilled(ARM::LR);
590      NumGPRSpills++;
591      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
592                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
593      ForceLRSpill = false;
594      ExtraCSSpill = true;
595    }
596
597    // Darwin ABI requires FP to point to the stack slot that contains the
598    // previous FP.
599    if (STI.isTargetDarwin() || hasFP(MF)) {
600      MF.getRegInfo().setPhysRegUsed(FramePtr);
601      NumGPRSpills++;
602    }
603
604    // If stack and double are 8-byte aligned and we are spilling an odd number
605    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
606    // the integer and double callee save areas.
607    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
608    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
609      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
610        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
611          unsigned Reg = UnspilledCS1GPRs[i];
612          // Don't spill high register if the function is thumb1
613          if (!AFI->isThumb1OnlyFunction() ||
614              isARMLowRegister(Reg) || Reg == ARM::LR) {
615            MF.getRegInfo().setPhysRegUsed(Reg);
616            AFI->setCSRegisterIsSpilled(Reg);
617            if (!isReservedReg(MF, Reg))
618              ExtraCSSpill = true;
619            break;
620          }
621        }
622      } else if (!UnspilledCS2GPRs.empty() &&
623                 !AFI->isThumb1OnlyFunction()) {
624        unsigned Reg = UnspilledCS2GPRs.front();
625        MF.getRegInfo().setPhysRegUsed(Reg);
626        AFI->setCSRegisterIsSpilled(Reg);
627        if (!isReservedReg(MF, Reg))
628          ExtraCSSpill = true;
629      }
630    }
631
632    // Estimate if we might need to scavenge a register at some point in order
633    // to materialize a stack offset. If so, either spill one additional
634    // callee-saved register or reserve a special spill slot to facilitate
635    // register scavenging.
636    if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) {
637      MachineFrameInfo  *MFI = MF.getFrameInfo();
638      unsigned Size = estimateStackSize(MF, MFI);
639      unsigned Limit = (1 << 12) - 1;
640      for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
641        for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
642          for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
643            if (I->getOperand(i).isFI()) {
644              unsigned Opcode = I->getOpcode();
645              const TargetInstrDesc &Desc = TII.get(Opcode);
646              unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
647              if (AddrMode == ARMII::AddrMode3) {
648                Limit = (1 << 8) - 1;
649                goto DoneEstimating;
650              } else if (AddrMode == ARMII::AddrMode5) {
651                unsigned ThisLimit = ((1 << 8) - 1) * 4;
652                if (ThisLimit < Limit)
653                  Limit = ThisLimit;
654              }
655            }
656        }
657    DoneEstimating:
658      if (Size >= Limit) {
659        // If any non-reserved CS register isn't spilled, just spill one or two
660        // extra. That should take care of it!
661        unsigned NumExtras = TargetAlign / 4;
662        SmallVector<unsigned, 2> Extras;
663        while (NumExtras && !UnspilledCS1GPRs.empty()) {
664          unsigned Reg = UnspilledCS1GPRs.back();
665          UnspilledCS1GPRs.pop_back();
666          if (!isReservedReg(MF, Reg)) {
667            Extras.push_back(Reg);
668            NumExtras--;
669          }
670        }
671        while (NumExtras && !UnspilledCS2GPRs.empty()) {
672          unsigned Reg = UnspilledCS2GPRs.back();
673          UnspilledCS2GPRs.pop_back();
674          if (!isReservedReg(MF, Reg)) {
675            Extras.push_back(Reg);
676            NumExtras--;
677          }
678        }
679        if (Extras.size() && NumExtras == 0) {
680          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
681            MF.getRegInfo().setPhysRegUsed(Extras[i]);
682            AFI->setCSRegisterIsSpilled(Extras[i]);
683          }
684        } else {
685          // Reserve a slot closest to SP or frame pointer.
686          const TargetRegisterClass *RC = &ARM::GPRRegClass;
687          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
688                                                           RC->getAlignment()));
689        }
690      }
691    }
692  }
693
694  if (ForceLRSpill) {
695    MF.getRegInfo().setPhysRegUsed(ARM::LR);
696    AFI->setCSRegisterIsSpilled(ARM::LR);
697    AFI->setLRIsSpilledForFarJump(true);
698  }
699}
700
701unsigned ARMBaseRegisterInfo::getRARegister() const {
702  return ARM::LR;
703}
704
705unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
706  if (STI.isTargetDarwin() || hasFP(MF))
707    return FramePtr;
708  return ARM::SP;
709}
710
711unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
712  llvm_unreachable("What is the exception register");
713  return 0;
714}
715
716unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
717  llvm_unreachable("What is the exception handler register");
718  return 0;
719}
720
721int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
722  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
723}
724
725unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
726                                               const MachineFunction &MF) const {
727  switch (Reg) {
728  default: break;
729  // Return 0 if either register of the pair is a special register.
730  // So no R12, etc.
731  case ARM::R1:
732    return ARM::R0;
733  case ARM::R3:
734    // FIXME!
735    return STI.isThumb1Only() ? 0 : ARM::R2;
736  case ARM::R5:
737    return ARM::R4;
738  case ARM::R7:
739    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
740  case ARM::R9:
741    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
742  case ARM::R11:
743    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
744
745  case ARM::S1:
746    return ARM::S0;
747  case ARM::S3:
748    return ARM::S2;
749  case ARM::S5:
750    return ARM::S4;
751  case ARM::S7:
752    return ARM::S6;
753  case ARM::S9:
754    return ARM::S8;
755  case ARM::S11:
756    return ARM::S10;
757  case ARM::S13:
758    return ARM::S12;
759  case ARM::S15:
760    return ARM::S14;
761  case ARM::S17:
762    return ARM::S16;
763  case ARM::S19:
764    return ARM::S18;
765  case ARM::S21:
766    return ARM::S20;
767  case ARM::S23:
768    return ARM::S22;
769  case ARM::S25:
770    return ARM::S24;
771  case ARM::S27:
772    return ARM::S26;
773  case ARM::S29:
774    return ARM::S28;
775  case ARM::S31:
776    return ARM::S30;
777
778  case ARM::D1:
779    return ARM::D0;
780  case ARM::D3:
781    return ARM::D2;
782  case ARM::D5:
783    return ARM::D4;
784  case ARM::D7:
785    return ARM::D6;
786  case ARM::D9:
787    return ARM::D8;
788  case ARM::D11:
789    return ARM::D10;
790  case ARM::D13:
791    return ARM::D12;
792  case ARM::D15:
793    return ARM::D14;
794  }
795
796  return 0;
797}
798
799unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
800                                             const MachineFunction &MF) const {
801  switch (Reg) {
802  default: break;
803  // Return 0 if either register of the pair is a special register.
804  // So no R12, etc.
805  case ARM::R0:
806    return ARM::R1;
807  case ARM::R2:
808    // FIXME!
809    return STI.isThumb1Only() ? 0 : ARM::R3;
810  case ARM::R4:
811    return ARM::R5;
812  case ARM::R6:
813    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
814  case ARM::R8:
815    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
816  case ARM::R10:
817    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
818
819  case ARM::S0:
820    return ARM::S1;
821  case ARM::S2:
822    return ARM::S3;
823  case ARM::S4:
824    return ARM::S5;
825  case ARM::S6:
826    return ARM::S7;
827  case ARM::S8:
828    return ARM::S9;
829  case ARM::S10:
830    return ARM::S11;
831  case ARM::S12:
832    return ARM::S13;
833  case ARM::S14:
834    return ARM::S15;
835  case ARM::S16:
836    return ARM::S17;
837  case ARM::S18:
838    return ARM::S19;
839  case ARM::S20:
840    return ARM::S21;
841  case ARM::S22:
842    return ARM::S23;
843  case ARM::S24:
844    return ARM::S25;
845  case ARM::S26:
846    return ARM::S27;
847  case ARM::S28:
848    return ARM::S29;
849  case ARM::S30:
850    return ARM::S31;
851
852  case ARM::D0:
853    return ARM::D1;
854  case ARM::D2:
855    return ARM::D3;
856  case ARM::D4:
857    return ARM::D5;
858  case ARM::D6:
859    return ARM::D7;
860  case ARM::D8:
861    return ARM::D9;
862  case ARM::D10:
863    return ARM::D11;
864  case ARM::D12:
865    return ARM::D13;
866  case ARM::D14:
867    return ARM::D15;
868  }
869
870  return 0;
871}
872
873// FIXME: Dup in ARMBaseInstrInfo.cpp
874static inline
875const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
876  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
877}
878
879static inline
880const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
881  return MIB.addReg(0);
882}
883
884/// emitLoadConstPool - Emits a load from constpool to materialize the
885/// specified immediate.
886void ARMBaseRegisterInfo::
887emitLoadConstPool(MachineBasicBlock &MBB,
888                  MachineBasicBlock::iterator &MBBI,
889                  DebugLoc dl,
890                  unsigned DestReg, int Val,
891                  ARMCC::CondCodes Pred,
892                  unsigned PredReg) const {
893  MachineFunction &MF = *MBB.getParent();
894  MachineConstantPool *ConstantPool = MF.getConstantPool();
895  Constant *C =
896             MF.getFunction()->getContext()->getConstantInt(Type::Int32Ty, Val);
897  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
898
899  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp), DestReg)
900    .addConstantPoolIndex(Idx)
901    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
902}
903
904bool ARMBaseRegisterInfo::
905requiresRegisterScavenging(const MachineFunction &MF) const {
906  return true;
907}
908
909// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
910// not required, we reserve argument space for call sites in the function
911// immediately on entry to the current function. This eliminates the need for
912// add/sub sp brackets around call sites. Returns true if the call frame is
913// included as part of the stack frame.
914bool ARMBaseRegisterInfo::
915hasReservedCallFrame(MachineFunction &MF) const {
916  const MachineFrameInfo *FFI = MF.getFrameInfo();
917  unsigned CFSize = FFI->getMaxCallFrameSize();
918  // It's not always a good idea to include the call frame as part of the
919  // stack frame. ARM (especially Thumb) has small immediate offset to
920  // address the stack frame. So a large call frame can cause poor codegen
921  // and may even makes it impossible to scavenge a register.
922  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
923    return false;
924
925  return !MF.getFrameInfo()->hasVarSizedObjects();
926}
927
928/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
929/// a destreg = basereg + immediate in ARM code.
930static
931void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
932                             MachineBasicBlock::iterator &MBBI,
933                             unsigned DestReg, unsigned BaseReg, int NumBytes,
934                             ARMCC::CondCodes Pred, unsigned PredReg,
935                             const ARMBaseInstrInfo &TII,
936                             DebugLoc dl) {
937  bool isSub = NumBytes < 0;
938  if (isSub) NumBytes = -NumBytes;
939
940  while (NumBytes) {
941    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
942    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
943    assert(ThisVal && "Didn't extract field correctly");
944
945    // We will handle these bits from offset, clear them.
946    NumBytes &= ~ThisVal;
947
948    assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
949
950    // Build the new ADD / SUB.
951    BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg)
952      .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
953      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
954    BaseReg = DestReg;
955  }
956}
957
958static void
959emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
960             const ARMBaseInstrInfo &TII, DebugLoc dl,
961             int NumBytes,
962             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
963  emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
964                          Pred, PredReg, TII, dl);
965}
966
967void ARMBaseRegisterInfo::
968eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
969                              MachineBasicBlock::iterator I) const {
970  if (!hasReservedCallFrame(MF)) {
971    // If we have alloca, convert as follows:
972    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
973    // ADJCALLSTACKUP   -> add, sp, sp, amount
974    MachineInstr *Old = I;
975    DebugLoc dl = Old->getDebugLoc();
976    unsigned Amount = Old->getOperand(0).getImm();
977    if (Amount != 0) {
978      // We need to keep the stack aligned properly.  To do this, we round the
979      // amount of space needed for the outgoing arguments up to the next
980      // alignment boundary.
981      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
982      Amount = (Amount+Align-1)/Align*Align;
983
984      // Replace the pseudo instruction with a new instruction...
985      unsigned Opc = Old->getOpcode();
986      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
987      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
988        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
989        unsigned PredReg = Old->getOperand(2).getReg();
990        emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
991      } else {
992        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
993        unsigned PredReg = Old->getOperand(3).getReg();
994        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
995        emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
996      }
997    }
998  }
999  MBB.erase(I);
1000}
1001
1002/// findScratchRegister - Find a 'free' ARM register. If register scavenger
1003/// is not being used, R12 is available. Otherwise, try for a call-clobbered
1004/// register first and then a spilled callee-saved register if that fails.
1005static
1006unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
1007                             ARMFunctionInfo *AFI) {
1008  unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
1009  assert (!AFI->isThumb1OnlyFunction());
1010  if (Reg == 0)
1011    // Try a already spilled CS register.
1012    Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
1013
1014  return Reg;
1015}
1016
1017void ARMBaseRegisterInfo::
1018eliminateFrameIndex(MachineBasicBlock::iterator II,
1019                    int SPAdj, RegScavenger *RS) const{
1020  unsigned i = 0;
1021  MachineInstr &MI = *II;
1022  MachineBasicBlock &MBB = *MI.getParent();
1023  MachineFunction &MF = *MBB.getParent();
1024  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1025  DebugLoc dl = MI.getDebugLoc();
1026
1027  while (!MI.getOperand(i).isFI()) {
1028    ++i;
1029    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1030  }
1031
1032  unsigned FrameReg = ARM::SP;
1033  int FrameIndex = MI.getOperand(i).getIndex();
1034  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1035               MF.getFrameInfo()->getStackSize() + SPAdj;
1036
1037  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1038    Offset -= AFI->getGPRCalleeSavedArea1Offset();
1039  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1040    Offset -= AFI->getGPRCalleeSavedArea2Offset();
1041  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1042    Offset -= AFI->getDPRCalleeSavedAreaOffset();
1043  else if (hasFP(MF)) {
1044    assert(SPAdj == 0 && "Unexpected");
1045    // There is alloca()'s in this function, must reference off the frame
1046    // pointer instead.
1047    FrameReg = getFrameRegister(MF);
1048    Offset -= AFI->getFramePtrSpillOffset();
1049  }
1050
1051  unsigned Opcode = MI.getOpcode();
1052  const TargetInstrDesc &Desc = MI.getDesc();
1053  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1054  bool isSub = false;
1055
1056  // Memory operands in inline assembly always use AddrMode2.
1057  if (Opcode == ARM::INLINEASM)
1058    AddrMode = ARMII::AddrMode2;
1059
1060  if (Opcode == getOpcode(ARMII::ADDri)) {
1061    Offset += MI.getOperand(i+1).getImm();
1062    if (Offset == 0) {
1063      // Turn it into a move.
1064      MI.setDesc(TII.get(getOpcode(ARMII::MOVr)));
1065      MI.getOperand(i).ChangeToRegister(FrameReg, false);
1066      MI.RemoveOperand(i+1);
1067      return;
1068    } else if (Offset < 0) {
1069      Offset = -Offset;
1070      isSub = true;
1071      MI.setDesc(TII.get(getOpcode(ARMII::SUBri)));
1072    }
1073
1074    // Common case: small offset, fits into instruction.
1075    if (ARM_AM::getSOImmVal(Offset) != -1) {
1076      // Replace the FrameIndex with sp / fp
1077      MI.getOperand(i).ChangeToRegister(FrameReg, false);
1078      MI.getOperand(i+1).ChangeToImmediate(Offset);
1079      return;
1080    }
1081
1082    // Otherwise, we fallback to common code below to form the imm offset with
1083    // a sequence of ADDri instructions.  First though, pull as much of the imm
1084    // into this ADDri as possible.
1085    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1086    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1087
1088    // We will handle these bits from offset, clear them.
1089    Offset &= ~ThisImmVal;
1090
1091    // Get the properly encoded SOImmVal field.
1092    assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1093           "Bit extraction didn't work?");
1094    MI.getOperand(i+1).ChangeToImmediate(ThisImmVal);
1095  } else {
1096    unsigned ImmIdx = 0;
1097    int InstrOffs = 0;
1098    unsigned NumBits = 0;
1099    unsigned Scale = 1;
1100    switch (AddrMode) {
1101    case ARMII::AddrMode2: {
1102      ImmIdx = i+2;
1103      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1104      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1105        InstrOffs *= -1;
1106      NumBits = 12;
1107      break;
1108    }
1109    case ARMII::AddrMode3: {
1110      ImmIdx = i+2;
1111      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1112      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1113        InstrOffs *= -1;
1114      NumBits = 8;
1115      break;
1116    }
1117    case ARMII::AddrMode5: {
1118      ImmIdx = i+1;
1119      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1120      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1121        InstrOffs *= -1;
1122      NumBits = 8;
1123      Scale = 4;
1124      break;
1125    }
1126    case ARMII::AddrModeT2_i12: {
1127      ImmIdx = i+1;
1128      InstrOffs = MI.getOperand(ImmIdx).getImm();
1129      NumBits = 12;
1130      break;
1131    }
1132    case ARMII::AddrModeT2_i8: {
1133      ImmIdx = i+1;
1134      InstrOffs = MI.getOperand(ImmIdx).getImm();
1135      NumBits = 8;
1136      break;
1137    }
1138    case ARMII::AddrModeT2_so: {
1139      ImmIdx = i+2;
1140      InstrOffs = MI.getOperand(ImmIdx).getImm();
1141      break;
1142    }
1143    default:
1144      llvm_unreachable("Unsupported addressing mode!");
1145      break;
1146    }
1147
1148    Offset += InstrOffs * Scale;
1149    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1150    if (Offset < 0) {
1151      Offset = -Offset;
1152      isSub = true;
1153    }
1154
1155    // Common case: small offset, fits into instruction.
1156    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1157    int ImmedOffset = Offset / Scale;
1158    unsigned Mask = (1 << NumBits) - 1;
1159    if ((unsigned)Offset <= Mask * Scale) {
1160      // Replace the FrameIndex with sp
1161      MI.getOperand(i).ChangeToRegister(FrameReg, false);
1162      if (isSub)
1163        ImmedOffset |= 1 << NumBits;
1164      ImmOp.ChangeToImmediate(ImmedOffset);
1165      return;
1166    }
1167
1168    // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1169    ImmedOffset = ImmedOffset & Mask;
1170    if (isSub)
1171      ImmedOffset |= 1 << NumBits;
1172    ImmOp.ChangeToImmediate(ImmedOffset);
1173    Offset &= ~(Mask*Scale);
1174  }
1175
1176  // If we get here, the immediate doesn't fit into the instruction.  We folded
1177  // as much as possible above, handle the rest, providing a register that is
1178  // SP+LargeImm.
1179  assert(Offset && "This code isn't needed if offset already handled!");
1180
1181  // Insert a set of r12 with the full address: r12 = sp + offset
1182  // If the offset we have is too large to fit into the instruction, we need
1183  // to form it with a series of ADDri's.  Do this by taking 8-bit chunks
1184  // out of 'Offset'.
1185  unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1186  if (ScratchReg == 0)
1187    // No register is "free". Scavenge a register.
1188    ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1189  int PIdx = MI.findFirstPredOperandIdx();
1190  ARMCC::CondCodes Pred = (PIdx == -1)
1191    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1192  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1193  emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1194                          isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
1195  MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1196}
1197
1198/// Move iterator pass the next bunch of callee save load / store ops for
1199/// the particular spill area (1: integer area 1, 2: integer area 2,
1200/// 3: fp area, 0: don't care).
1201static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1202                                   MachineBasicBlock::iterator &MBBI,
1203                                   int Opc, unsigned Area,
1204                                   const ARMSubtarget &STI) {
1205  while (MBBI != MBB.end() &&
1206         MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1207    if (Area != 0) {
1208      bool Done = false;
1209      unsigned Category = 0;
1210      switch (MBBI->getOperand(0).getReg()) {
1211      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1212      case ARM::LR:
1213        Category = 1;
1214        break;
1215      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1216        Category = STI.isTargetDarwin() ? 2 : 1;
1217        break;
1218      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1219      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1220        Category = 3;
1221        break;
1222      default:
1223        Done = true;
1224        break;
1225      }
1226      if (Done || Category != Area)
1227        break;
1228    }
1229
1230    ++MBBI;
1231  }
1232}
1233
1234void ARMBaseRegisterInfo::
1235emitPrologue(MachineFunction &MF) const {
1236  MachineBasicBlock &MBB = MF.front();
1237  MachineBasicBlock::iterator MBBI = MBB.begin();
1238  MachineFrameInfo  *MFI = MF.getFrameInfo();
1239  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1240  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1241  unsigned NumBytes = MFI->getStackSize();
1242  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1243  DebugLoc dl = (MBBI != MBB.end() ?
1244                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1245
1246  // Determine the sizes of each callee-save spill areas and record which frame
1247  // belongs to which callee-save spill areas.
1248  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1249  int FramePtrSpillFI = 0;
1250
1251  if (VARegSaveSize)
1252    emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
1253
1254  if (!AFI->hasStackFrame()) {
1255    if (NumBytes != 0)
1256      emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1257    return;
1258  }
1259
1260  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1261    unsigned Reg = CSI[i].getReg();
1262    int FI = CSI[i].getFrameIdx();
1263    switch (Reg) {
1264    case ARM::R4:
1265    case ARM::R5:
1266    case ARM::R6:
1267    case ARM::R7:
1268    case ARM::LR:
1269      if (Reg == FramePtr)
1270        FramePtrSpillFI = FI;
1271      AFI->addGPRCalleeSavedArea1Frame(FI);
1272      GPRCS1Size += 4;
1273      break;
1274    case ARM::R8:
1275    case ARM::R9:
1276    case ARM::R10:
1277    case ARM::R11:
1278      if (Reg == FramePtr)
1279        FramePtrSpillFI = FI;
1280      if (STI.isTargetDarwin()) {
1281        AFI->addGPRCalleeSavedArea2Frame(FI);
1282        GPRCS2Size += 4;
1283      } else {
1284        AFI->addGPRCalleeSavedArea1Frame(FI);
1285        GPRCS1Size += 4;
1286      }
1287      break;
1288    default:
1289      AFI->addDPRCalleeSavedAreaFrame(FI);
1290      DPRCSSize += 8;
1291    }
1292  }
1293
1294  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1295  emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
1296  movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 1, STI);
1297
1298  // Darwin ABI requires FP to point to the stack slot that contains the
1299  // previous FP.
1300  if (STI.isTargetDarwin() || hasFP(MF)) {
1301    MachineInstrBuilder MIB =
1302      BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::ADDri)), FramePtr)
1303      .addFrameIndex(FramePtrSpillFI).addImm(0);
1304    AddDefaultCC(AddDefaultPred(MIB));
1305  }
1306
1307  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1308  emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
1309
1310  // Build the new SUBri to adjust SP for FP callee-save spill area.
1311  movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 2, STI);
1312  emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
1313
1314  // Determine starting offsets of spill areas.
1315  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1316  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1317  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1318  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1319  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1320  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1321  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1322
1323  NumBytes = DPRCSOffset;
1324  if (NumBytes) {
1325    // Insert it after all the callee-save spills.
1326    movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FSTD), 3, STI);
1327    emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1328  }
1329
1330  if (STI.isTargetELF() && hasFP(MF)) {
1331    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1332                             AFI->getFramePtrSpillOffset());
1333  }
1334
1335  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1336  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1337  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1338}
1339
1340static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1341  for (unsigned i = 0; CSRegs[i]; ++i)
1342    if (Reg == CSRegs[i])
1343      return true;
1344  return false;
1345}
1346
1347static bool isCSRestore(MachineInstr *MI,
1348                        const ARMBaseInstrInfo &TII,
1349                        const unsigned *CSRegs) {
1350  return ((MI->getOpcode() == (int)TII.getOpcode(ARMII::FLDD) ||
1351           MI->getOpcode() == (int)TII.getOpcode(ARMII::LDR)) &&
1352          MI->getOperand(1).isFI() &&
1353          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1354}
1355
1356void ARMBaseRegisterInfo::
1357emitEpilogue(MachineFunction &MF,
1358             MachineBasicBlock &MBB) const {
1359  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1360  assert(MBBI->getOpcode() == (int)getOpcode(ARMII::BX_RET) &&
1361         "Can only insert epilog into returning blocks");
1362  DebugLoc dl = MBBI->getDebugLoc();
1363  MachineFrameInfo *MFI = MF.getFrameInfo();
1364  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1365  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1366  int NumBytes = (int)MFI->getStackSize();
1367
1368  if (!AFI->hasStackFrame()) {
1369    if (NumBytes != 0)
1370      emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1371  } else {
1372    // Unwind MBBI to point to first LDR / FLDD.
1373    const unsigned *CSRegs = getCalleeSavedRegs();
1374    if (MBBI != MBB.begin()) {
1375      do
1376        --MBBI;
1377      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1378      if (!isCSRestore(MBBI, TII, CSRegs))
1379        ++MBBI;
1380    }
1381
1382    // Move SP to start of FP callee save spill area.
1383    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1384                 AFI->getGPRCalleeSavedArea2Size() +
1385                 AFI->getDPRCalleeSavedAreaSize());
1386
1387    // Darwin ABI requires FP to point to the stack slot that contains the
1388    // previous FP.
1389    if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1390      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1391      // Reset SP based on frame pointer only if the stack frame extends beyond
1392      // frame pointer stack slot or target is ELF and the function has FP.
1393      if (AFI->getGPRCalleeSavedArea2Size() ||
1394          AFI->getDPRCalleeSavedAreaSize()  ||
1395          AFI->getDPRCalleeSavedAreaOffset()||
1396          hasFP(MF)) {
1397        if (NumBytes)
1398          BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::SUBri)), ARM::SP).addReg(FramePtr)
1399            .addImm(NumBytes)
1400            .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1401        else
1402          BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::MOVr)), ARM::SP).addReg(FramePtr)
1403            .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1404      }
1405    } else if (NumBytes) {
1406      emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1407    }
1408
1409    // Move SP to start of integer callee save spill area 2.
1410    movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FLDD), 3, STI);
1411    emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
1412
1413    // Move SP to start of integer callee save spill area 1.
1414    movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 2, STI);
1415    emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
1416
1417    // Move SP to SP upon entry to the function.
1418    movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 1, STI);
1419    emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
1420  }
1421
1422  if (VARegSaveSize)
1423    emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);
1424
1425}
1426
1427#include "ARMGenRegisterInfo.inc"
1428