ARMBaseRegisterInfo.cpp revision bba9390fc6c0d536172c6bb4a9c93db557c1aff4
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/ADT/BitVector.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/RegisterScavenging.h" 29#include "llvm/CodeGen/VirtRegMap.h" 30#include "llvm/IR/Constants.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/Function.h" 33#include "llvm/IR/LLVMContext.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetFrameLowering.h" 38#include "llvm/Target/TargetMachine.h" 39#include "llvm/Target/TargetOptions.h" 40 41#define GET_REGINFO_TARGET_DESC 42#include "ARMGenRegisterInfo.inc" 43 44using namespace llvm; 45 46ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) 47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), 48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 49 BasePtr(ARM::R6) { 50} 51 52const uint16_t* 53ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 54 const uint16_t *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 55 ? CSR_iOS_SaveList 56 : CSR_AAPCS_SaveList; 57 58 if (!MF) return RegList; 59 60 const Function *F = MF->getFunction(); 61 if (F->getCallingConv() == CallingConv::GHC) { 62 // GHC set of callee saved regs is empty as all those regs are 63 // used for passing STG regs around 64 return CSR_NoRegs_SaveList; 65 } else if (F->hasFnAttribute("interrupt")) { 66 if (STI.isMClass()) { 67 // M-class CPUs have hardware which saves the registers needed to allow a 68 // function conforming to the AAPCS to function as a handler. 69 return CSR_AAPCS_SaveList; 70 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 71 // Fast interrupt mode gives the handler a private copy of R8-R14, so less 72 // need to be saved to restore user-mode state. 73 return CSR_FIQ_SaveList; 74 } else { 75 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 76 // exception handling. 77 return CSR_GenericInt_SaveList; 78 } 79 } 80 81 return RegList; 82} 83 84const uint32_t* 85ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 86 if (CC == CallingConv::GHC) 87 // This is academic becase all GHC calls are (supposed to be) tail calls 88 return CSR_NoRegs_RegMask; 89 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 90 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 91} 92 93const uint32_t* 94ARMBaseRegisterInfo::getNoPreservedMask() const { 95 return CSR_NoRegs_RegMask; 96} 97 98const uint32_t* 99ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { 100 // This should return a register mask that is the same as that returned by 101 // getCallPreservedMask but that additionally preserves the register used for 102 // the first i32 argument (which must also be the register used to return a 103 // single i32 return value) 104 // 105 // In case that the calling convention does not use the same register for 106 // both or otherwise does not want to enable this optimization, the function 107 // should return NULL 108 if (CC == CallingConv::GHC) 109 // This is academic becase all GHC calls are (supposed to be) tail calls 110 return NULL; 111 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 112 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask; 113} 114 115BitVector ARMBaseRegisterInfo:: 116getReservedRegs(const MachineFunction &MF) const { 117 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 118 119 // FIXME: avoid re-calculating this every time. 120 BitVector Reserved(getNumRegs()); 121 Reserved.set(ARM::SP); 122 Reserved.set(ARM::PC); 123 Reserved.set(ARM::FPSCR); 124 Reserved.set(ARM::APSR_NZCV); 125 if (TFI->hasFP(MF)) 126 Reserved.set(FramePtr); 127 if (hasBasePointer(MF)) 128 Reserved.set(BasePtr); 129 // Some targets reserve R9. 130 if (STI.isR9Reserved()) 131 Reserved.set(ARM::R9); 132 // Reserve D16-D31 if the subtarget doesn't support them. 133 if (!STI.hasVFP3() || STI.hasD16()) { 134 assert(ARM::D31 == ARM::D16 + 15); 135 for (unsigned i = 0; i != 16; ++i) 136 Reserved.set(ARM::D16 + i); 137 } 138 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 139 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 140 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 141 if (Reserved.test(*SI)) Reserved.set(*I); 142 143 return Reserved; 144} 145 146const TargetRegisterClass* 147ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 148 const { 149 const TargetRegisterClass *Super = RC; 150 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 151 do { 152 switch (Super->getID()) { 153 case ARM::GPRRegClassID: 154 case ARM::SPRRegClassID: 155 case ARM::DPRRegClassID: 156 case ARM::QPRRegClassID: 157 case ARM::QQPRRegClassID: 158 case ARM::QQQQPRRegClassID: 159 case ARM::GPRPairRegClassID: 160 return Super; 161 } 162 Super = *I++; 163 } while (Super); 164 return RC; 165} 166 167const TargetRegisterClass * 168ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 169 const { 170 return &ARM::GPRRegClass; 171} 172 173const TargetRegisterClass * 174ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 175 if (RC == &ARM::CCRRegClass) 176 return 0; // Can't copy CCR registers. 177 return RC; 178} 179 180unsigned 181ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 182 MachineFunction &MF) const { 183 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 184 185 switch (RC->getID()) { 186 default: 187 return 0; 188 case ARM::tGPRRegClassID: 189 return TFI->hasFP(MF) ? 4 : 5; 190 case ARM::GPRRegClassID: { 191 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 192 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 193 } 194 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 195 case ARM::DPRRegClassID: 196 return 32 - 10; 197 } 198} 199 200// Get the other register in a GPRPair. 201static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 202 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 203 if (ARM::GPRPairRegClass.contains(*Supers)) 204 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 205 return 0; 206} 207 208// Resolve the RegPairEven / RegPairOdd register allocator hints. 209void 210ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 211 ArrayRef<MCPhysReg> Order, 212 SmallVectorImpl<MCPhysReg> &Hints, 213 const MachineFunction &MF, 214 const VirtRegMap *VRM) const { 215 const MachineRegisterInfo &MRI = MF.getRegInfo(); 216 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 217 218 unsigned Odd; 219 switch (Hint.first) { 220 case ARMRI::RegPairEven: 221 Odd = 0; 222 break; 223 case ARMRI::RegPairOdd: 224 Odd = 1; 225 break; 226 default: 227 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 228 return; 229 } 230 231 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 232 // Check if the other part of the pair has already been assigned, and provide 233 // the paired register as the first hint. 234 unsigned PairedPhys = 0; 235 if (VRM && VRM->hasPhys(Hint.second)) { 236 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 237 if (PairedPhys && MRI.isReserved(PairedPhys)) 238 PairedPhys = 0; 239 } 240 241 // First prefer the paired physreg. 242 if (PairedPhys && 243 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 244 Hints.push_back(PairedPhys); 245 246 // Then prefer even or odd registers. 247 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 248 unsigned Reg = Order[I]; 249 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 250 continue; 251 // Don't provide hints that are paired to a reserved register. 252 unsigned Paired = getPairedGPR(Reg, !Odd, this); 253 if (!Paired || MRI.isReserved(Paired)) 254 continue; 255 Hints.push_back(Reg); 256 } 257} 258 259void 260ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 261 MachineFunction &MF) const { 262 MachineRegisterInfo *MRI = &MF.getRegInfo(); 263 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 264 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 265 Hint.first == (unsigned)ARMRI::RegPairEven) && 266 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 267 // If 'Reg' is one of the even / odd register pair and it's now changed 268 // (e.g. coalesced) into a different register. The other register of the 269 // pair allocation hint must be updated to reflect the relationship 270 // change. 271 unsigned OtherReg = Hint.second; 272 Hint = MRI->getRegAllocationHint(OtherReg); 273 if (Hint.second == Reg) 274 // Make sure the pair has not already divorced. 275 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 276 } 277} 278 279bool 280ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 281 // CortexA9 has a Write-after-write hazard for NEON registers. 282 if (!STI.isLikeA9()) 283 return false; 284 285 switch (RC->getID()) { 286 case ARM::DPRRegClassID: 287 case ARM::DPR_8RegClassID: 288 case ARM::DPR_VFP2RegClassID: 289 case ARM::QPRRegClassID: 290 case ARM::QPR_8RegClassID: 291 case ARM::QPR_VFP2RegClassID: 292 case ARM::SPRRegClassID: 293 case ARM::SPR_8RegClassID: 294 // Avoid reusing S, D, and Q registers. 295 // Don't increase register pressure for QQ and QQQQ. 296 return true; 297 default: 298 return false; 299 } 300} 301 302bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 303 const MachineFrameInfo *MFI = MF.getFrameInfo(); 304 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 305 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 306 307 // When outgoing call frames are so large that we adjust the stack pointer 308 // around the call, we can no longer use the stack pointer to reach the 309 // emergency spill slot. 310 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 311 return true; 312 313 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 314 // negative range for ldr/str (255), and thumb1 is positive offsets only. 315 // It's going to be better to use the SP or Base Pointer instead. When there 316 // are variable sized objects, we can't reference off of the SP, so we 317 // reserve a Base Pointer. 318 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 319 // Conservatively estimate whether the negative offset from the frame 320 // pointer will be sufficient to reach. If a function has a smallish 321 // frame, it's less likely to have lots of spills and callee saved 322 // space, so it's all more likely to be within range of the frame pointer. 323 // If it's wrong, the scavenger will still enable access to work, it just 324 // won't be optimal. 325 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 326 return false; 327 return true; 328 } 329 330 return false; 331} 332 333bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 334 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 335 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 336 // We can't realign the stack if: 337 // 1. Dynamic stack realignment is explicitly disabled, 338 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 339 // 3. There are VLAs in the function and the base pointer is disabled. 340 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 341 return false; 342 if (AFI->isThumb1OnlyFunction()) 343 return false; 344 // Stack realignment requires a frame pointer. If we already started 345 // register allocation with frame pointer elimination, it is too late now. 346 if (!MRI->canReserveReg(FramePtr)) 347 return false; 348 // We may also need a base pointer if there are dynamic allocas or stack 349 // pointer adjustments around calls. 350 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 351 return true; 352 // A base pointer is required and allowed. Check that it isn't too late to 353 // reserve it. 354 return MRI->canReserveReg(BasePtr); 355} 356 357bool ARMBaseRegisterInfo:: 358needsStackRealignment(const MachineFunction &MF) const { 359 const MachineFrameInfo *MFI = MF.getFrameInfo(); 360 const Function *F = MF.getFunction(); 361 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 362 bool requiresRealignment = 363 ((MFI->getMaxAlignment() > StackAlign) || 364 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 365 Attribute::StackAlignment)); 366 367 return requiresRealignment && canRealignStack(MF); 368} 369 370bool ARMBaseRegisterInfo:: 371cannotEliminateFrame(const MachineFunction &MF) const { 372 const MachineFrameInfo *MFI = MF.getFrameInfo(); 373 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 374 return true; 375 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 376 || needsStackRealignment(MF); 377} 378 379unsigned 380ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 381 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 382 383 if (TFI->hasFP(MF)) 384 return FramePtr; 385 return ARM::SP; 386} 387 388unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 389 llvm_unreachable("What is the exception register"); 390} 391 392unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 393 llvm_unreachable("What is the exception handler register"); 394} 395 396/// emitLoadConstPool - Emits a load from constpool to materialize the 397/// specified immediate. 398void ARMBaseRegisterInfo:: 399emitLoadConstPool(MachineBasicBlock &MBB, 400 MachineBasicBlock::iterator &MBBI, 401 DebugLoc dl, 402 unsigned DestReg, unsigned SubIdx, int Val, 403 ARMCC::CondCodes Pred, 404 unsigned PredReg, unsigned MIFlags) const { 405 MachineFunction &MF = *MBB.getParent(); 406 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 407 MachineConstantPool *ConstantPool = MF.getConstantPool(); 408 const Constant *C = 409 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 410 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 411 412 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 413 .addReg(DestReg, getDefRegState(true), SubIdx) 414 .addConstantPoolIndex(Idx) 415 .addImm(0).addImm(Pred).addReg(PredReg) 416 .setMIFlags(MIFlags); 417} 418 419bool ARMBaseRegisterInfo:: 420requiresRegisterScavenging(const MachineFunction &MF) const { 421 return true; 422} 423 424bool ARMBaseRegisterInfo:: 425trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 426 return true; 427} 428 429bool ARMBaseRegisterInfo:: 430requiresFrameIndexScavenging(const MachineFunction &MF) const { 431 return true; 432} 433 434bool ARMBaseRegisterInfo:: 435requiresVirtualBaseRegisters(const MachineFunction &MF) const { 436 return true; 437} 438 439int64_t ARMBaseRegisterInfo:: 440getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 441 const MCInstrDesc &Desc = MI->getDesc(); 442 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 443 int64_t InstrOffs = 0; 444 int Scale = 1; 445 unsigned ImmIdx = 0; 446 switch (AddrMode) { 447 case ARMII::AddrModeT2_i8: 448 case ARMII::AddrModeT2_i12: 449 case ARMII::AddrMode_i12: 450 InstrOffs = MI->getOperand(Idx+1).getImm(); 451 Scale = 1; 452 break; 453 case ARMII::AddrMode5: { 454 // VFP address mode. 455 const MachineOperand &OffOp = MI->getOperand(Idx+1); 456 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 457 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 458 InstrOffs = -InstrOffs; 459 Scale = 4; 460 break; 461 } 462 case ARMII::AddrMode2: { 463 ImmIdx = Idx+2; 464 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 465 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 466 InstrOffs = -InstrOffs; 467 break; 468 } 469 case ARMII::AddrMode3: { 470 ImmIdx = Idx+2; 471 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 472 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 473 InstrOffs = -InstrOffs; 474 break; 475 } 476 case ARMII::AddrModeT1_s: { 477 ImmIdx = Idx+1; 478 InstrOffs = MI->getOperand(ImmIdx).getImm(); 479 Scale = 4; 480 break; 481 } 482 default: 483 llvm_unreachable("Unsupported addressing mode!"); 484 } 485 486 return InstrOffs * Scale; 487} 488 489/// needsFrameBaseReg - Returns true if the instruction's frame index 490/// reference would be better served by a base register other than FP 491/// or SP. Used by LocalStackFrameAllocation to determine which frame index 492/// references it should create new base registers for. 493bool ARMBaseRegisterInfo:: 494needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 495 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 496 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 497 } 498 499 // It's the load/store FI references that cause issues, as it can be difficult 500 // to materialize the offset if it won't fit in the literal field. Estimate 501 // based on the size of the local frame and some conservative assumptions 502 // about the rest of the stack frame (note, this is pre-regalloc, so 503 // we don't know everything for certain yet) whether this offset is likely 504 // to be out of range of the immediate. Return true if so. 505 506 // We only generate virtual base registers for loads and stores, so 507 // return false for everything else. 508 unsigned Opc = MI->getOpcode(); 509 switch (Opc) { 510 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 511 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 512 case ARM::t2LDRi12: case ARM::t2LDRi8: 513 case ARM::t2STRi12: case ARM::t2STRi8: 514 case ARM::VLDRS: case ARM::VLDRD: 515 case ARM::VSTRS: case ARM::VSTRD: 516 case ARM::tSTRspi: case ARM::tLDRspi: 517 break; 518 default: 519 return false; 520 } 521 522 // Without a virtual base register, if the function has variable sized 523 // objects, all fixed-size local references will be via the frame pointer, 524 // Approximate the offset and see if it's legal for the instruction. 525 // Note that the incoming offset is based on the SP value at function entry, 526 // so it'll be negative. 527 MachineFunction &MF = *MI->getParent()->getParent(); 528 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 529 MachineFrameInfo *MFI = MF.getFrameInfo(); 530 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 531 532 // Estimate an offset from the frame pointer. 533 // Conservatively assume all callee-saved registers get pushed. R4-R6 534 // will be earlier than the FP, so we ignore those. 535 // R7, LR 536 int64_t FPOffset = Offset - 8; 537 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 538 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 539 FPOffset -= 80; 540 // Estimate an offset from the stack pointer. 541 // The incoming offset is relating to the SP at the start of the function, 542 // but when we access the local it'll be relative to the SP after local 543 // allocation, so adjust our SP-relative offset by that allocation size. 544 Offset = -Offset; 545 Offset += MFI->getLocalFrameSize(); 546 // Assume that we'll have at least some spill slots allocated. 547 // FIXME: This is a total SWAG number. We should run some statistics 548 // and pick a real one. 549 Offset += 128; // 128 bytes of spill slots 550 551 // If there is a frame pointer, try using it. 552 // The FP is only available if there is no dynamic realignment. We 553 // don't know for sure yet whether we'll need that, so we guess based 554 // on whether there are any local variables that would trigger it. 555 unsigned StackAlign = TFI->getStackAlignment(); 556 if (TFI->hasFP(MF) && 557 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 558 if (isFrameOffsetLegal(MI, FPOffset)) 559 return false; 560 } 561 // If we can reference via the stack pointer, try that. 562 // FIXME: This (and the code that resolves the references) can be improved 563 // to only disallow SP relative references in the live range of 564 // the VLA(s). In practice, it's unclear how much difference that 565 // would make, but it may be worth doing. 566 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 567 return false; 568 569 // The offset likely isn't legal, we want to allocate a virtual base register. 570 return true; 571} 572 573/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 574/// be a pointer to FrameIdx at the beginning of the basic block. 575void ARMBaseRegisterInfo:: 576materializeFrameBaseRegister(MachineBasicBlock *MBB, 577 unsigned BaseReg, int FrameIdx, 578 int64_t Offset) const { 579 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 580 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 581 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 582 583 MachineBasicBlock::iterator Ins = MBB->begin(); 584 DebugLoc DL; // Defaults to "unknown" 585 if (Ins != MBB->end()) 586 DL = Ins->getDebugLoc(); 587 588 const MachineFunction &MF = *MBB->getParent(); 589 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 590 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 591 const MCInstrDesc &MCID = TII.get(ADDriOpc); 592 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 593 594 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 595 .addFrameIndex(FrameIdx).addImm(Offset)); 596 597 if (!AFI->isThumb1OnlyFunction()) 598 AddDefaultCC(MIB); 599} 600 601void 602ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 603 unsigned BaseReg, int64_t Offset) const { 604 MachineInstr &MI = *I; 605 MachineBasicBlock &MBB = *MI.getParent(); 606 MachineFunction &MF = *MBB.getParent(); 607 const ARMBaseInstrInfo &TII = 608 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 609 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 610 int Off = Offset; // ARM doesn't need the general 64-bit offsets 611 unsigned i = 0; 612 613 assert(!AFI->isThumb1OnlyFunction() && 614 "This resolveFrameIndex does not support Thumb1!"); 615 616 while (!MI.getOperand(i).isFI()) { 617 ++i; 618 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 619 } 620 bool Done = false; 621 if (!AFI->isThumbFunction()) 622 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 623 else { 624 assert(AFI->isThumb2Function()); 625 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 626 } 627 assert (Done && "Unable to resolve frame index!"); 628 (void)Done; 629} 630 631bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 632 int64_t Offset) const { 633 const MCInstrDesc &Desc = MI->getDesc(); 634 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 635 unsigned i = 0; 636 637 while (!MI->getOperand(i).isFI()) { 638 ++i; 639 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 640 } 641 642 // AddrMode4 and AddrMode6 cannot handle any offset. 643 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 644 return Offset == 0; 645 646 unsigned NumBits = 0; 647 unsigned Scale = 1; 648 bool isSigned = true; 649 switch (AddrMode) { 650 case ARMII::AddrModeT2_i8: 651 case ARMII::AddrModeT2_i12: 652 // i8 supports only negative, and i12 supports only positive, so 653 // based on Offset sign, consider the appropriate instruction 654 Scale = 1; 655 if (Offset < 0) { 656 NumBits = 8; 657 Offset = -Offset; 658 } else { 659 NumBits = 12; 660 } 661 break; 662 case ARMII::AddrMode5: 663 // VFP address mode. 664 NumBits = 8; 665 Scale = 4; 666 break; 667 case ARMII::AddrMode_i12: 668 case ARMII::AddrMode2: 669 NumBits = 12; 670 break; 671 case ARMII::AddrMode3: 672 NumBits = 8; 673 break; 674 case ARMII::AddrModeT1_s: 675 NumBits = 5; 676 Scale = 4; 677 isSigned = false; 678 break; 679 default: 680 llvm_unreachable("Unsupported addressing mode!"); 681 } 682 683 Offset += getFrameIndexInstrOffset(MI, i); 684 // Make sure the offset is encodable for instructions that scale the 685 // immediate. 686 if ((Offset & (Scale-1)) != 0) 687 return false; 688 689 if (isSigned && Offset < 0) 690 Offset = -Offset; 691 692 unsigned Mask = (1 << NumBits) - 1; 693 if ((unsigned)Offset <= Mask * Scale) 694 return true; 695 696 return false; 697} 698 699void 700ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 701 int SPAdj, unsigned FIOperandNum, 702 RegScavenger *RS) const { 703 MachineInstr &MI = *II; 704 MachineBasicBlock &MBB = *MI.getParent(); 705 MachineFunction &MF = *MBB.getParent(); 706 const ARMBaseInstrInfo &TII = 707 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 708 const ARMFrameLowering *TFI = 709 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 710 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 711 assert(!AFI->isThumb1OnlyFunction() && 712 "This eliminateFrameIndex does not support Thumb1!"); 713 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 714 unsigned FrameReg; 715 716 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 717 718 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 719 // call frame setup/destroy instructions have already been eliminated. That 720 // means the stack pointer cannot be used to access the emergency spill slot 721 // when !hasReservedCallFrame(). 722#ifndef NDEBUG 723 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 724 assert(TFI->hasReservedCallFrame(MF) && 725 "Cannot use SP to access the emergency spill slot in " 726 "functions without a reserved call frame"); 727 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 728 "Cannot use SP to access the emergency spill slot in " 729 "functions with variable sized frame objects"); 730 } 731#endif // NDEBUG 732 733 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 734 735 // Modify MI as necessary to handle as much of 'Offset' as possible 736 bool Done = false; 737 if (!AFI->isThumbFunction()) 738 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 739 else { 740 assert(AFI->isThumb2Function()); 741 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 742 } 743 if (Done) 744 return; 745 746 // If we get here, the immediate doesn't fit into the instruction. We folded 747 // as much as possible above, handle the rest, providing a register that is 748 // SP+LargeImm. 749 assert((Offset || 750 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 751 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 752 "This code isn't needed if offset already handled!"); 753 754 unsigned ScratchReg = 0; 755 int PIdx = MI.findFirstPredOperandIdx(); 756 ARMCC::CondCodes Pred = (PIdx == -1) 757 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 758 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 759 if (Offset == 0) 760 // Must be addrmode4/6. 761 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 762 else { 763 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 764 if (!AFI->isThumbFunction()) 765 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 766 Offset, Pred, PredReg, TII); 767 else { 768 assert(AFI->isThumb2Function()); 769 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 770 Offset, Pred, PredReg, TII); 771 } 772 // Update the original instruction to use the scratch register. 773 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 774 } 775} 776