ARMBaseRegisterInfo.cpp revision c140c4803dc3e10e08138670829bc0494986abe9 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMInstrInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineLocation.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/RegisterScavenging.h"
29#include "llvm/Target/TargetFrameInfo.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/ADT/BitVector.h"
33#include "llvm/ADT/SmallVector.h"
34using namespace llvm;
35
36unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
37  using namespace ARM;
38  switch (RegEnum) {
39  case R0:  case S0:  case D0:  return 0;
40  case R1:  case S1:  case D1:  return 1;
41  case R2:  case S2:  case D2:  return 2;
42  case R3:  case S3:  case D3:  return 3;
43  case R4:  case S4:  case D4:  return 4;
44  case R5:  case S5:  case D5:  return 5;
45  case R6:  case S6:  case D6:  return 6;
46  case R7:  case S7:  case D7:  return 7;
47  case R8:  case S8:  case D8:  return 8;
48  case R9:  case S9:  case D9:  return 9;
49  case R10: case S10: case D10: return 10;
50  case R11: case S11: case D11: return 11;
51  case R12: case S12: case D12: return 12;
52  case SP:  case S13: case D13: return 13;
53  case LR:  case S14: case D14: return 14;
54  case PC:  case S15: case D15: return 15;
55  case S16: return 16;
56  case S17: return 17;
57  case S18: return 18;
58  case S19: return 19;
59  case S20: return 20;
60  case S21: return 21;
61  case S22: return 22;
62  case S23: return 23;
63  case S24: return 24;
64  case S25: return 25;
65  case S26: return 26;
66  case S27: return 27;
67  case S28: return 28;
68  case S29: return 29;
69  case S30: return 30;
70  case S31: return 31;
71  default:
72    assert(0 && "Unknown ARM register!");
73    abort();
74  }
75}
76
77unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
78                                                   bool &isSPVFP) {
79  isSPVFP = false;
80
81  using namespace ARM;
82  switch (RegEnum) {
83  default:
84    assert(0 && "Unknown ARM register!");
85    abort();
86  case R0:  case D0:  return 0;
87  case R1:  case D1:  return 1;
88  case R2:  case D2:  return 2;
89  case R3:  case D3:  return 3;
90  case R4:  case D4:  return 4;
91  case R5:  case D5:  return 5;
92  case R6:  case D6:  return 6;
93  case R7:  case D7:  return 7;
94  case R8:  case D8:  return 8;
95  case R9:  case D9:  return 9;
96  case R10: case D10: return 10;
97  case R11: case D11: return 11;
98  case R12: case D12: return 12;
99  case SP:  case D13: return 13;
100  case LR:  case D14: return 14;
101  case PC:  case D15: return 15;
102
103  case S0: case S1: case S2: case S3:
104  case S4: case S5: case S6: case S7:
105  case S8: case S9: case S10: case S11:
106  case S12: case S13: case S14: case S15:
107  case S16: case S17: case S18: case S19:
108  case S20: case S21: case S22: case S23:
109  case S24: case S25: case S26: case S27:
110  case S28: case S29: case S30: case S31:  {
111    isSPVFP = true;
112    switch (RegEnum) {
113    default: return 0; // Avoid compile time warning.
114    case S0: return 0;
115    case S1: return 1;
116    case S2: return 2;
117    case S3: return 3;
118    case S4: return 4;
119    case S5: return 5;
120    case S6: return 6;
121    case S7: return 7;
122    case S8: return 8;
123    case S9: return 9;
124    case S10: return 10;
125    case S11: return 11;
126    case S12: return 12;
127    case S13: return 13;
128    case S14: return 14;
129    case S15: return 15;
130    case S16: return 16;
131    case S17: return 17;
132    case S18: return 18;
133    case S19: return 19;
134    case S20: return 20;
135    case S21: return 21;
136    case S22: return 22;
137    case S23: return 23;
138    case S24: return 24;
139    case S25: return 25;
140    case S26: return 26;
141    case S27: return 27;
142    case S28: return 28;
143    case S29: return 29;
144    case S30: return 30;
145    case S31: return 31;
146    }
147  }
148  }
149}
150
151ARMBaseRegisterInfo::ARMBaseRegisterInfo(const TargetInstrInfo &tii,
152                                         const ARMSubtarget &sti)
153  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
154    TII(tii), STI(sti),
155    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
156}
157
158const unsigned*
159ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160  static const unsigned CalleeSavedRegs[] = {
161    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
162    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
163
164    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
165    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
166    0
167  };
168
169  static const unsigned DarwinCalleeSavedRegs[] = {
170    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
171    // register.
172    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
173    ARM::R11, ARM::R10, ARM::R8,
174
175    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
176    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
177    0
178  };
179  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
180}
181
182const TargetRegisterClass* const *
183ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
184  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
185    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
186    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188
189    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
190    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
191    0
192  };
193
194  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
195    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
196    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
197    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
198
199    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
200    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
201    0
202  };
203
204  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
205    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
206    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
207    &ARM::GPRRegClass, &ARM::GPRRegClass,
208
209    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
210    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
211    0
212  };
213
214  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
215    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
216    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
217    &ARM::GPRRegClass,  &ARM::GPRRegClass,
218
219    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
220    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
221    0
222  };
223
224  if (STI.isThumb()) {
225    return STI.isTargetDarwin()
226      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
227  }
228  return STI.isTargetDarwin()
229    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
230}
231
232BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
233  // FIXME: avoid re-calculating this everytime.
234  BitVector Reserved(getNumRegs());
235  Reserved.set(ARM::SP);
236  Reserved.set(ARM::PC);
237  if (STI.isTargetDarwin() || hasFP(MF))
238    Reserved.set(FramePtr);
239  // Some targets reserve R9.
240  if (STI.isR9Reserved())
241    Reserved.set(ARM::R9);
242  return Reserved;
243}
244
245bool
246ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
247  switch (Reg) {
248  default: break;
249  case ARM::SP:
250  case ARM::PC:
251    return true;
252  case ARM::R7:
253  case ARM::R11:
254    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
255      return true;
256    break;
257  case ARM::R9:
258    return STI.isR9Reserved();
259  }
260
261  return false;
262}
263
264const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const {
265  return &ARM::GPRRegClass;
266}
267
268/// getAllocationOrder - Returns the register allocation order for a specified
269/// register class in the form of a pair of TargetRegisterClass iterators.
270std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
271ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
272                                        unsigned HintType, unsigned HintReg,
273                                        const MachineFunction &MF) const {
274  // Alternative register allocation orders when favoring even / odd registers
275  // of register pairs.
276
277  // No FP, R9 is available.
278  static const unsigned GPREven1[] = {
279    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
280    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
281    ARM::R9, ARM::R11
282  };
283  static const unsigned GPROdd1[] = {
284    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
285    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
286    ARM::R8, ARM::R10
287  };
288
289  // FP is R7, R9 is available.
290  static const unsigned GPREven2[] = {
291    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
292    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
293    ARM::R9, ARM::R11
294  };
295  static const unsigned GPROdd2[] = {
296    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
297    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
298    ARM::R8, ARM::R10
299  };
300
301  // FP is R11, R9 is available.
302  static const unsigned GPREven3[] = {
303    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
304    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
305    ARM::R9
306  };
307  static const unsigned GPROdd3[] = {
308    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
309    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
310    ARM::R8
311  };
312
313  // No FP, R9 is not available.
314  static const unsigned GPREven4[] = {
315    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
316    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
317    ARM::R11
318  };
319  static const unsigned GPROdd4[] = {
320    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
321    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
322    ARM::R10
323  };
324
325  // FP is R7, R9 is not available.
326  static const unsigned GPREven5[] = {
327    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
328    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
329    ARM::R11
330  };
331  static const unsigned GPROdd5[] = {
332    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
333    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
334    ARM::R10
335  };
336
337  // FP is R11, R9 is not available.
338  static const unsigned GPREven6[] = {
339    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
340    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
341  };
342  static const unsigned GPROdd6[] = {
343    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
344    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
345  };
346
347
348  if (HintType == ARMRI::RegPairEven) {
349    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
350      // It's no longer possible to fulfill this hint. Return the default
351      // allocation order.
352      return std::make_pair(RC->allocation_order_begin(MF),
353                            RC->allocation_order_end(MF));
354
355    if (!STI.isTargetDarwin() && !hasFP(MF)) {
356      if (!STI.isR9Reserved())
357        return std::make_pair(GPREven1,
358                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
359      else
360        return std::make_pair(GPREven4,
361                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
362    } else if (FramePtr == ARM::R7) {
363      if (!STI.isR9Reserved())
364        return std::make_pair(GPREven2,
365                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
366      else
367        return std::make_pair(GPREven5,
368                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
369    } else { // FramePtr == ARM::R11
370      if (!STI.isR9Reserved())
371        return std::make_pair(GPREven3,
372                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
373      else
374        return std::make_pair(GPREven6,
375                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
376    }
377  } else if (HintType == ARMRI::RegPairOdd) {
378    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
379      // It's no longer possible to fulfill this hint. Return the default
380      // allocation order.
381      return std::make_pair(RC->allocation_order_begin(MF),
382                            RC->allocation_order_end(MF));
383
384    if (!STI.isTargetDarwin() && !hasFP(MF)) {
385      if (!STI.isR9Reserved())
386        return std::make_pair(GPROdd1,
387                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
388      else
389        return std::make_pair(GPROdd4,
390                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
391    } else if (FramePtr == ARM::R7) {
392      if (!STI.isR9Reserved())
393        return std::make_pair(GPROdd2,
394                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
395      else
396        return std::make_pair(GPROdd5,
397                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
398    } else { // FramePtr == ARM::R11
399      if (!STI.isR9Reserved())
400        return std::make_pair(GPROdd3,
401                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
402      else
403        return std::make_pair(GPROdd6,
404                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
405    }
406  }
407  return std::make_pair(RC->allocation_order_begin(MF),
408                        RC->allocation_order_end(MF));
409}
410
411/// ResolveRegAllocHint - Resolves the specified register allocation hint
412/// to a physical register. Returns the physical register if it is successful.
413unsigned
414ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
415                                         const MachineFunction &MF) const {
416  if (Reg == 0 || !isPhysicalRegister(Reg))
417    return 0;
418  if (Type == 0)
419    return Reg;
420  else if (Type == (unsigned)ARMRI::RegPairOdd)
421    // Odd register.
422    return getRegisterPairOdd(Reg, MF);
423  else if (Type == (unsigned)ARMRI::RegPairEven)
424    // Even register.
425    return getRegisterPairEven(Reg, MF);
426  return 0;
427}
428
429void
430ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
431                                        MachineFunction &MF) const {
432  MachineRegisterInfo *MRI = &MF.getRegInfo();
433  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
434  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
435       Hint.first == (unsigned)ARMRI::RegPairEven) &&
436      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
437    // If 'Reg' is one of the even / odd register pair and it's now changed
438    // (e.g. coalesced) into a different register. The other register of the
439    // pair allocation hint must be updated to reflect the relationship
440    // change.
441    unsigned OtherReg = Hint.second;
442    Hint = MRI->getRegAllocationHint(OtherReg);
443    if (Hint.second == Reg)
444      // Make sure the pair has not already divorced.
445      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
446  }
447}
448
449/// hasFP - Return true if the specified function should have a dedicated frame
450/// pointer register.  This is true if the function has variable sized allocas
451/// or if frame pointer elimination is disabled.
452///
453bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
454  const MachineFrameInfo *MFI = MF.getFrameInfo();
455  return (NoFramePointerElim ||
456          MFI->hasVarSizedObjects() ||
457          MFI->isFrameAddressTaken());
458}
459
460static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
461  const MachineFrameInfo *FFI = MF.getFrameInfo();
462  int Offset = 0;
463  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
464    int FixedOff = -FFI->getObjectOffset(i);
465    if (FixedOff > Offset) Offset = FixedOff;
466  }
467  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
468    if (FFI->isDeadObjectIndex(i))
469      continue;
470    Offset += FFI->getObjectSize(i);
471    unsigned Align = FFI->getObjectAlignment(i);
472    // Adjust to alignment boundary
473    Offset = (Offset+Align-1)/Align*Align;
474  }
475  return (unsigned)Offset;
476}
477
478void
479ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
480                                                          RegScavenger *RS) const {
481  // This tells PEI to spill the FP as if it is any other callee-save register
482  // to take advantage the eliminateFrameIndex machinery. This also ensures it
483  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
484  // to combine multiple loads / stores.
485  bool CanEliminateFrame = true;
486  bool CS1Spilled = false;
487  bool LRSpilled = false;
488  unsigned NumGPRSpills = 0;
489  SmallVector<unsigned, 4> UnspilledCS1GPRs;
490  SmallVector<unsigned, 4> UnspilledCS2GPRs;
491  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
492
493  // Don't spill FP if the frame can be eliminated. This is determined
494  // by scanning the callee-save registers to see if any is used.
495  const unsigned *CSRegs = getCalleeSavedRegs();
496  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
497  for (unsigned i = 0; CSRegs[i]; ++i) {
498    unsigned Reg = CSRegs[i];
499    bool Spilled = false;
500    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
501      AFI->setCSRegisterIsSpilled(Reg);
502      Spilled = true;
503      CanEliminateFrame = false;
504    } else {
505      // Check alias registers too.
506      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
507        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
508          Spilled = true;
509          CanEliminateFrame = false;
510        }
511      }
512    }
513
514    if (CSRegClasses[i] == &ARM::GPRRegClass) {
515      if (Spilled) {
516        NumGPRSpills++;
517
518        if (!STI.isTargetDarwin()) {
519          if (Reg == ARM::LR)
520            LRSpilled = true;
521          CS1Spilled = true;
522          continue;
523        }
524
525        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
526        switch (Reg) {
527        case ARM::LR:
528          LRSpilled = true;
529          // Fallthrough
530        case ARM::R4:
531        case ARM::R5:
532        case ARM::R6:
533        case ARM::R7:
534          CS1Spilled = true;
535          break;
536        default:
537          break;
538        }
539      } else {
540        if (!STI.isTargetDarwin()) {
541          UnspilledCS1GPRs.push_back(Reg);
542          continue;
543        }
544
545        switch (Reg) {
546        case ARM::R4:
547        case ARM::R5:
548        case ARM::R6:
549        case ARM::R7:
550        case ARM::LR:
551          UnspilledCS1GPRs.push_back(Reg);
552          break;
553        default:
554          UnspilledCS2GPRs.push_back(Reg);
555          break;
556        }
557      }
558    }
559  }
560
561  bool ForceLRSpill = false;
562  if (!LRSpilled && AFI->isThumbFunction()) {
563    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
564    // Force LR to be spilled if the Thumb function size is > 2048. This enables
565    // use of BL to implement far jump. If it turns out that it's not needed
566    // then the branch fix up path will undo it.
567    if (FnSize >= (1 << 11)) {
568      CanEliminateFrame = false;
569      ForceLRSpill = true;
570    }
571  }
572
573  bool ExtraCSSpill = false;
574  if (!CanEliminateFrame || hasFP(MF)) {
575    AFI->setHasStackFrame(true);
576
577    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
578    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
579    if (!LRSpilled && CS1Spilled) {
580      MF.getRegInfo().setPhysRegUsed(ARM::LR);
581      AFI->setCSRegisterIsSpilled(ARM::LR);
582      NumGPRSpills++;
583      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
584                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
585      ForceLRSpill = false;
586      ExtraCSSpill = true;
587    }
588
589    // Darwin ABI requires FP to point to the stack slot that contains the
590    // previous FP.
591    if (STI.isTargetDarwin() || hasFP(MF)) {
592      MF.getRegInfo().setPhysRegUsed(FramePtr);
593      NumGPRSpills++;
594    }
595
596    // If stack and double are 8-byte aligned and we are spilling an odd number
597    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
598    // the integer and double callee save areas.
599    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
600    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
601      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
602        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
603          unsigned Reg = UnspilledCS1GPRs[i];
604          // Don't spiil high register if the function is thumb
605          if (!AFI->isThumbFunction() ||
606              isARMLowRegister(Reg) || Reg == ARM::LR) {
607            MF.getRegInfo().setPhysRegUsed(Reg);
608            AFI->setCSRegisterIsSpilled(Reg);
609            if (!isReservedReg(MF, Reg))
610              ExtraCSSpill = true;
611            break;
612          }
613        }
614      } else if (!UnspilledCS2GPRs.empty() &&
615                 !AFI->isThumbFunction()) {
616        unsigned Reg = UnspilledCS2GPRs.front();
617        MF.getRegInfo().setPhysRegUsed(Reg);
618        AFI->setCSRegisterIsSpilled(Reg);
619        if (!isReservedReg(MF, Reg))
620          ExtraCSSpill = true;
621      }
622    }
623
624    // Estimate if we might need to scavenge a register at some point in order
625    // to materialize a stack offset. If so, either spill one additional
626    // callee-saved register or reserve a special spill slot to facilitate
627    // register scavenging.
628    if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
629      MachineFrameInfo  *MFI = MF.getFrameInfo();
630      unsigned Size = estimateStackSize(MF, MFI);
631      unsigned Limit = (1 << 12) - 1;
632      for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
633        for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
634          for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
635            if (I->getOperand(i).isFI()) {
636              unsigned Opcode = I->getOpcode();
637              const TargetInstrDesc &Desc = TII.get(Opcode);
638              unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
639              if (AddrMode == ARMII::AddrMode3) {
640                Limit = (1 << 8) - 1;
641                goto DoneEstimating;
642              } else if (AddrMode == ARMII::AddrMode5) {
643                unsigned ThisLimit = ((1 << 8) - 1) * 4;
644                if (ThisLimit < Limit)
645                  Limit = ThisLimit;
646              }
647            }
648        }
649    DoneEstimating:
650      if (Size >= Limit) {
651        // If any non-reserved CS register isn't spilled, just spill one or two
652        // extra. That should take care of it!
653        unsigned NumExtras = TargetAlign / 4;
654        SmallVector<unsigned, 2> Extras;
655        while (NumExtras && !UnspilledCS1GPRs.empty()) {
656          unsigned Reg = UnspilledCS1GPRs.back();
657          UnspilledCS1GPRs.pop_back();
658          if (!isReservedReg(MF, Reg)) {
659            Extras.push_back(Reg);
660            NumExtras--;
661          }
662        }
663        while (NumExtras && !UnspilledCS2GPRs.empty()) {
664          unsigned Reg = UnspilledCS2GPRs.back();
665          UnspilledCS2GPRs.pop_back();
666          if (!isReservedReg(MF, Reg)) {
667            Extras.push_back(Reg);
668            NumExtras--;
669          }
670        }
671        if (Extras.size() && NumExtras == 0) {
672          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
673            MF.getRegInfo().setPhysRegUsed(Extras[i]);
674            AFI->setCSRegisterIsSpilled(Extras[i]);
675          }
676        } else {
677          // Reserve a slot closest to SP or frame pointer.
678          const TargetRegisterClass *RC = &ARM::GPRRegClass;
679          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
680                                                           RC->getAlignment()));
681        }
682      }
683    }
684  }
685
686  if (ForceLRSpill) {
687    MF.getRegInfo().setPhysRegUsed(ARM::LR);
688    AFI->setCSRegisterIsSpilled(ARM::LR);
689    AFI->setLRIsSpilledForFarJump(true);
690  }
691}
692
693unsigned ARMBaseRegisterInfo::getRARegister() const {
694  return ARM::LR;
695}
696
697unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
698  if (STI.isTargetDarwin() || hasFP(MF))
699    return FramePtr;
700  return ARM::SP;
701}
702
703unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
704  assert(0 && "What is the exception register");
705  return 0;
706}
707
708unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
709  assert(0 && "What is the exception handler register");
710  return 0;
711}
712
713int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
714  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
715}
716
717unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
718                                               const MachineFunction &MF) const {
719  switch (Reg) {
720  default: break;
721  // Return 0 if either register of the pair is a special register.
722  // So no R12, etc.
723  case ARM::R1:
724    return ARM::R0;
725  case ARM::R3:
726    // FIXME!
727    return STI.isThumb() ? 0 : ARM::R2;
728  case ARM::R5:
729    return ARM::R4;
730  case ARM::R7:
731    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
732  case ARM::R9:
733    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
734  case ARM::R11:
735    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
736
737  case ARM::S1:
738    return ARM::S0;
739  case ARM::S3:
740    return ARM::S2;
741  case ARM::S5:
742    return ARM::S4;
743  case ARM::S7:
744    return ARM::S6;
745  case ARM::S9:
746    return ARM::S8;
747  case ARM::S11:
748    return ARM::S10;
749  case ARM::S13:
750    return ARM::S12;
751  case ARM::S15:
752    return ARM::S14;
753  case ARM::S17:
754    return ARM::S16;
755  case ARM::S19:
756    return ARM::S18;
757  case ARM::S21:
758    return ARM::S20;
759  case ARM::S23:
760    return ARM::S22;
761  case ARM::S25:
762    return ARM::S24;
763  case ARM::S27:
764    return ARM::S26;
765  case ARM::S29:
766    return ARM::S28;
767  case ARM::S31:
768    return ARM::S30;
769
770  case ARM::D1:
771    return ARM::D0;
772  case ARM::D3:
773    return ARM::D2;
774  case ARM::D5:
775    return ARM::D4;
776  case ARM::D7:
777    return ARM::D6;
778  case ARM::D9:
779    return ARM::D8;
780  case ARM::D11:
781    return ARM::D10;
782  case ARM::D13:
783    return ARM::D12;
784  case ARM::D15:
785    return ARM::D14;
786  }
787
788  return 0;
789}
790
791unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
792                                             const MachineFunction &MF) const {
793  switch (Reg) {
794  default: break;
795  // Return 0 if either register of the pair is a special register.
796  // So no R12, etc.
797  case ARM::R0:
798    return ARM::R1;
799  case ARM::R2:
800    // FIXME!
801    return STI.isThumb() ? 0 : ARM::R3;
802  case ARM::R4:
803    return ARM::R5;
804  case ARM::R6:
805    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
806  case ARM::R8:
807    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
808  case ARM::R10:
809    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
810
811  case ARM::S0:
812    return ARM::S1;
813  case ARM::S2:
814    return ARM::S3;
815  case ARM::S4:
816    return ARM::S5;
817  case ARM::S6:
818    return ARM::S7;
819  case ARM::S8:
820    return ARM::S9;
821  case ARM::S10:
822    return ARM::S11;
823  case ARM::S12:
824    return ARM::S13;
825  case ARM::S14:
826    return ARM::S15;
827  case ARM::S16:
828    return ARM::S17;
829  case ARM::S18:
830    return ARM::S19;
831  case ARM::S20:
832    return ARM::S21;
833  case ARM::S22:
834    return ARM::S23;
835  case ARM::S24:
836    return ARM::S25;
837  case ARM::S26:
838    return ARM::S27;
839  case ARM::S28:
840    return ARM::S29;
841  case ARM::S30:
842    return ARM::S31;
843
844  case ARM::D0:
845    return ARM::D1;
846  case ARM::D2:
847    return ARM::D3;
848  case ARM::D4:
849    return ARM::D5;
850  case ARM::D6:
851    return ARM::D7;
852  case ARM::D8:
853    return ARM::D9;
854  case ARM::D10:
855    return ARM::D11;
856  case ARM::D12:
857    return ARM::D13;
858  case ARM::D14:
859    return ARM::D15;
860  }
861
862  return 0;
863}
864
865#include "ARMGenRegisterInfo.inc"
866