ARMBaseRegisterInfo.cpp revision cf453ee70a1ae03cc641686fd5db0f8a7d8ce250
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMBaseRegisterInfo.h" 18#include "ARMInstrInfo.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMSubtarget.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/RegisterScavenging.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetFrameInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/BitVector.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/Support/CommandLine.h" 41using namespace llvm; 42 43static cl::opt<bool> 44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true), 45 cl::desc("Reuse repeated frame index values")); 46 47unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 48 bool *isSPVFP) { 49 if (isSPVFP) 50 *isSPVFP = false; 51 52 using namespace ARM; 53 switch (RegEnum) { 54 default: 55 llvm_unreachable("Unknown ARM register!"); 56 case R0: case D0: case Q0: return 0; 57 case R1: case D1: case Q1: return 1; 58 case R2: case D2: case Q2: return 2; 59 case R3: case D3: case Q3: return 3; 60 case R4: case D4: case Q4: return 4; 61 case R5: case D5: case Q5: return 5; 62 case R6: case D6: case Q6: return 6; 63 case R7: case D7: case Q7: return 7; 64 case R8: case D8: case Q8: return 8; 65 case R9: case D9: case Q9: return 9; 66 case R10: case D10: case Q10: return 10; 67 case R11: case D11: case Q11: return 11; 68 case R12: case D12: case Q12: return 12; 69 case SP: case D13: case Q13: return 13; 70 case LR: case D14: case Q14: return 14; 71 case PC: case D15: case Q15: return 15; 72 73 case D16: return 16; 74 case D17: return 17; 75 case D18: return 18; 76 case D19: return 19; 77 case D20: return 20; 78 case D21: return 21; 79 case D22: return 22; 80 case D23: return 23; 81 case D24: return 24; 82 case D25: return 25; 83 case D26: return 27; 84 case D27: return 27; 85 case D28: return 28; 86 case D29: return 29; 87 case D30: return 30; 88 case D31: return 31; 89 90 case S0: case S1: case S2: case S3: 91 case S4: case S5: case S6: case S7: 92 case S8: case S9: case S10: case S11: 93 case S12: case S13: case S14: case S15: 94 case S16: case S17: case S18: case S19: 95 case S20: case S21: case S22: case S23: 96 case S24: case S25: case S26: case S27: 97 case S28: case S29: case S30: case S31: { 98 if (isSPVFP) 99 *isSPVFP = true; 100 switch (RegEnum) { 101 default: return 0; // Avoid compile time warning. 102 case S0: return 0; 103 case S1: return 1; 104 case S2: return 2; 105 case S3: return 3; 106 case S4: return 4; 107 case S5: return 5; 108 case S6: return 6; 109 case S7: return 7; 110 case S8: return 8; 111 case S9: return 9; 112 case S10: return 10; 113 case S11: return 11; 114 case S12: return 12; 115 case S13: return 13; 116 case S14: return 14; 117 case S15: return 15; 118 case S16: return 16; 119 case S17: return 17; 120 case S18: return 18; 121 case S19: return 19; 122 case S20: return 20; 123 case S21: return 21; 124 case S22: return 22; 125 case S23: return 23; 126 case S24: return 24; 127 case S25: return 25; 128 case S26: return 26; 129 case S27: return 27; 130 case S28: return 28; 131 case S29: return 29; 132 case S30: return 30; 133 case S31: return 31; 134 } 135 } 136 } 137} 138 139ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 140 const ARMSubtarget &sti) 141 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 142 TII(tii), STI(sti), 143 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 144} 145 146const unsigned* 147ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 148 static const unsigned CalleeSavedRegs[] = { 149 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 150 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 151 152 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 153 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 154 0 155 }; 156 157 static const unsigned DarwinCalleeSavedRegs[] = { 158 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 159 // register. 160 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 161 ARM::R11, ARM::R10, ARM::R8, 162 163 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 164 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 165 0 166 }; 167 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 168} 169 170const TargetRegisterClass* const * 171ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 172 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 173 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 174 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 175 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 176 177 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 178 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 179 0 180 }; 181 182 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 183 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 184 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 185 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 186 187 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 188 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 189 0 190 }; 191 192 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 193 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 194 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 195 &ARM::GPRRegClass, &ARM::GPRRegClass, 196 197 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 198 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 199 0 200 }; 201 202 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 203 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, 204 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, 205 &ARM::GPRRegClass, &ARM::GPRRegClass, 206 207 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 208 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 209 0 210 }; 211 212 if (STI.isThumb1Only()) { 213 return STI.isTargetDarwin() 214 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 215 } 216 return STI.isTargetDarwin() 217 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 218} 219 220BitVector ARMBaseRegisterInfo:: 221getReservedRegs(const MachineFunction &MF) const { 222 // FIXME: avoid re-calculating this everytime. 223 BitVector Reserved(getNumRegs()); 224 Reserved.set(ARM::SP); 225 Reserved.set(ARM::PC); 226 if (STI.isTargetDarwin() || hasFP(MF)) 227 Reserved.set(FramePtr); 228 // Some targets reserve R9. 229 if (STI.isR9Reserved()) 230 Reserved.set(ARM::R9); 231 return Reserved; 232} 233 234bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 235 unsigned Reg) const { 236 switch (Reg) { 237 default: break; 238 case ARM::SP: 239 case ARM::PC: 240 return true; 241 case ARM::R7: 242 case ARM::R11: 243 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 244 return true; 245 break; 246 case ARM::R9: 247 return STI.isR9Reserved(); 248 } 249 250 return false; 251} 252 253const TargetRegisterClass * 254ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 255 const TargetRegisterClass *B, 256 unsigned SubIdx) const { 257 switch (SubIdx) { 258 default: return 0; 259 case 1: 260 case 2: 261 case 3: 262 case 4: 263 // S sub-registers. 264 if (A->getSize() == 8) { 265 if (B == &ARM::SPR_8RegClass) 266 return &ARM::DPR_8RegClass; 267 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 268 if (A == &ARM::DPR_8RegClass) 269 return A; 270 return &ARM::DPR_VFP2RegClass; 271 } 272 273 assert(A->getSize() == 16 && "Expecting a Q register class!"); 274 if (B == &ARM::SPR_8RegClass) 275 return &ARM::QPR_8RegClass; 276 return &ARM::QPR_VFP2RegClass; 277 case 5: 278 case 6: 279 // D sub-registers. 280 if (B == &ARM::DPR_VFP2RegClass) 281 return &ARM::QPR_VFP2RegClass; 282 if (B == &ARM::DPR_8RegClass) 283 return &ARM::QPR_8RegClass; 284 return A; 285 } 286 return 0; 287} 288 289const TargetRegisterClass * 290ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 291 return ARM::GPRRegisterClass; 292} 293 294/// getAllocationOrder - Returns the register allocation order for a specified 295/// register class in the form of a pair of TargetRegisterClass iterators. 296std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 297ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 298 unsigned HintType, unsigned HintReg, 299 const MachineFunction &MF) const { 300 // Alternative register allocation orders when favoring even / odd registers 301 // of register pairs. 302 303 // No FP, R9 is available. 304 static const unsigned GPREven1[] = { 305 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 306 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 307 ARM::R9, ARM::R11 308 }; 309 static const unsigned GPROdd1[] = { 310 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 311 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 312 ARM::R8, ARM::R10 313 }; 314 315 // FP is R7, R9 is available. 316 static const unsigned GPREven2[] = { 317 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 318 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 319 ARM::R9, ARM::R11 320 }; 321 static const unsigned GPROdd2[] = { 322 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 323 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 324 ARM::R8, ARM::R10 325 }; 326 327 // FP is R11, R9 is available. 328 static const unsigned GPREven3[] = { 329 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 330 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 331 ARM::R9 332 }; 333 static const unsigned GPROdd3[] = { 334 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 335 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 336 ARM::R8 337 }; 338 339 // No FP, R9 is not available. 340 static const unsigned GPREven4[] = { 341 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 342 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 343 ARM::R11 344 }; 345 static const unsigned GPROdd4[] = { 346 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 347 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 348 ARM::R10 349 }; 350 351 // FP is R7, R9 is not available. 352 static const unsigned GPREven5[] = { 353 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 354 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 355 ARM::R11 356 }; 357 static const unsigned GPROdd5[] = { 358 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 359 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 360 ARM::R10 361 }; 362 363 // FP is R11, R9 is not available. 364 static const unsigned GPREven6[] = { 365 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 366 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 367 }; 368 static const unsigned GPROdd6[] = { 369 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 370 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 371 }; 372 373 374 if (HintType == ARMRI::RegPairEven) { 375 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 376 // It's no longer possible to fulfill this hint. Return the default 377 // allocation order. 378 return std::make_pair(RC->allocation_order_begin(MF), 379 RC->allocation_order_end(MF)); 380 381 if (!STI.isTargetDarwin() && !hasFP(MF)) { 382 if (!STI.isR9Reserved()) 383 return std::make_pair(GPREven1, 384 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 385 else 386 return std::make_pair(GPREven4, 387 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 388 } else if (FramePtr == ARM::R7) { 389 if (!STI.isR9Reserved()) 390 return std::make_pair(GPREven2, 391 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 392 else 393 return std::make_pair(GPREven5, 394 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 395 } else { // FramePtr == ARM::R11 396 if (!STI.isR9Reserved()) 397 return std::make_pair(GPREven3, 398 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 399 else 400 return std::make_pair(GPREven6, 401 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 402 } 403 } else if (HintType == ARMRI::RegPairOdd) { 404 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 405 // It's no longer possible to fulfill this hint. Return the default 406 // allocation order. 407 return std::make_pair(RC->allocation_order_begin(MF), 408 RC->allocation_order_end(MF)); 409 410 if (!STI.isTargetDarwin() && !hasFP(MF)) { 411 if (!STI.isR9Reserved()) 412 return std::make_pair(GPROdd1, 413 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 414 else 415 return std::make_pair(GPROdd4, 416 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 417 } else if (FramePtr == ARM::R7) { 418 if (!STI.isR9Reserved()) 419 return std::make_pair(GPROdd2, 420 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 421 else 422 return std::make_pair(GPROdd5, 423 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 424 } else { // FramePtr == ARM::R11 425 if (!STI.isR9Reserved()) 426 return std::make_pair(GPROdd3, 427 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 428 else 429 return std::make_pair(GPROdd6, 430 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 431 } 432 } 433 return std::make_pair(RC->allocation_order_begin(MF), 434 RC->allocation_order_end(MF)); 435} 436 437/// ResolveRegAllocHint - Resolves the specified register allocation hint 438/// to a physical register. Returns the physical register if it is successful. 439unsigned 440ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 441 const MachineFunction &MF) const { 442 if (Reg == 0 || !isPhysicalRegister(Reg)) 443 return 0; 444 if (Type == 0) 445 return Reg; 446 else if (Type == (unsigned)ARMRI::RegPairOdd) 447 // Odd register. 448 return getRegisterPairOdd(Reg, MF); 449 else if (Type == (unsigned)ARMRI::RegPairEven) 450 // Even register. 451 return getRegisterPairEven(Reg, MF); 452 return 0; 453} 454 455void 456ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 457 MachineFunction &MF) const { 458 MachineRegisterInfo *MRI = &MF.getRegInfo(); 459 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 460 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 461 Hint.first == (unsigned)ARMRI::RegPairEven) && 462 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 463 // If 'Reg' is one of the even / odd register pair and it's now changed 464 // (e.g. coalesced) into a different register. The other register of the 465 // pair allocation hint must be updated to reflect the relationship 466 // change. 467 unsigned OtherReg = Hint.second; 468 Hint = MRI->getRegAllocationHint(OtherReg); 469 if (Hint.second == Reg) 470 // Make sure the pair has not already divorced. 471 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 472 } 473} 474 475/// hasFP - Return true if the specified function should have a dedicated frame 476/// pointer register. This is true if the function has variable sized allocas 477/// or if frame pointer elimination is disabled. 478/// 479bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 480 const MachineFrameInfo *MFI = MF.getFrameInfo(); 481 return ((NoFramePointerElim && MFI->hasCalls())|| 482 needsStackRealignment(MF) || 483 MFI->hasVarSizedObjects() || 484 MFI->isFrameAddressTaken()); 485} 486 487bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 488 const MachineFrameInfo *MFI = MF.getFrameInfo(); 489 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 490 return (RealignStack && 491 !AFI->isThumb1OnlyFunction() && 492 !MFI->hasVarSizedObjects()); 493} 494 495bool ARMBaseRegisterInfo:: 496needsStackRealignment(const MachineFunction &MF) const { 497 const MachineFrameInfo *MFI = MF.getFrameInfo(); 498 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 499 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 500 return (RealignStack && 501 !AFI->isThumb1OnlyFunction() && 502 (MFI->getMaxAlignment() > StackAlign) && 503 !MFI->hasVarSizedObjects()); 504} 505 506bool ARMBaseRegisterInfo:: 507cannotEliminateFrame(const MachineFunction &MF) const { 508 const MachineFrameInfo *MFI = MF.getFrameInfo(); 509 if (NoFramePointerElim && MFI->hasCalls()) 510 return true; 511 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 512 || needsStackRealignment(MF); 513} 514 515/// estimateStackSize - Estimate and return the size of the frame. 516static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 517 const MachineFrameInfo *FFI = MF.getFrameInfo(); 518 int Offset = 0; 519 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 520 int FixedOff = -FFI->getObjectOffset(i); 521 if (FixedOff > Offset) Offset = FixedOff; 522 } 523 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 524 if (FFI->isDeadObjectIndex(i)) 525 continue; 526 Offset += FFI->getObjectSize(i); 527 unsigned Align = FFI->getObjectAlignment(i); 528 // Adjust to alignment boundary 529 Offset = (Offset+Align-1)/Align*Align; 530 } 531 return (unsigned)Offset; 532} 533 534/// estimateRSStackSizeLimit - Look at each instruction that references stack 535/// frames and return the stack size limit beyond which some of these 536/// instructions will require a scratch register during their expansion later. 537unsigned 538ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 539 unsigned Limit = (1 << 12) - 1; 540 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 541 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 542 I != E; ++I) { 543 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 544 if (!I->getOperand(i).isFI()) continue; 545 546 const TargetInstrDesc &Desc = TII.get(I->getOpcode()); 547 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 548 if (AddrMode == ARMII::AddrMode3 || 549 AddrMode == ARMII::AddrModeT2_i8) 550 return (1 << 8) - 1; 551 552 if (AddrMode == ARMII::AddrMode5 || 553 AddrMode == ARMII::AddrModeT2_i8s4) 554 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 555 556 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF)) 557 // When the stack offset is negative, we will end up using 558 // the i8 instructions instead. 559 return (1 << 8) - 1; 560 561 if (AddrMode == ARMII::AddrMode6) 562 return 0; 563 break; // At most one FI per instruction 564 } 565 } 566 } 567 568 return Limit; 569} 570 571void 572ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 573 RegScavenger *RS) const { 574 // This tells PEI to spill the FP as if it is any other callee-save register 575 // to take advantage the eliminateFrameIndex machinery. This also ensures it 576 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 577 // to combine multiple loads / stores. 578 bool CanEliminateFrame = true; 579 bool CS1Spilled = false; 580 bool LRSpilled = false; 581 unsigned NumGPRSpills = 0; 582 SmallVector<unsigned, 4> UnspilledCS1GPRs; 583 SmallVector<unsigned, 4> UnspilledCS2GPRs; 584 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 585 586 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 587 // scratch register. 588 // FIXME: It will be better just to find spare register here. 589 if (needsStackRealignment(MF) && 590 AFI->isThumb2Function()) 591 MF.getRegInfo().setPhysRegUsed(ARM::R4); 592 593 // Don't spill FP if the frame can be eliminated. This is determined 594 // by scanning the callee-save registers to see if any is used. 595 const unsigned *CSRegs = getCalleeSavedRegs(); 596 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 597 for (unsigned i = 0; CSRegs[i]; ++i) { 598 unsigned Reg = CSRegs[i]; 599 bool Spilled = false; 600 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 601 AFI->setCSRegisterIsSpilled(Reg); 602 Spilled = true; 603 CanEliminateFrame = false; 604 } else { 605 // Check alias registers too. 606 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 607 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 608 Spilled = true; 609 CanEliminateFrame = false; 610 } 611 } 612 } 613 614 if (CSRegClasses[i] == ARM::GPRRegisterClass || 615 CSRegClasses[i] == ARM::tGPRRegisterClass) { 616 if (Spilled) { 617 NumGPRSpills++; 618 619 if (!STI.isTargetDarwin()) { 620 if (Reg == ARM::LR) 621 LRSpilled = true; 622 CS1Spilled = true; 623 continue; 624 } 625 626 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 627 switch (Reg) { 628 case ARM::LR: 629 LRSpilled = true; 630 // Fallthrough 631 case ARM::R4: 632 case ARM::R5: 633 case ARM::R6: 634 case ARM::R7: 635 CS1Spilled = true; 636 break; 637 default: 638 break; 639 } 640 } else { 641 if (!STI.isTargetDarwin()) { 642 UnspilledCS1GPRs.push_back(Reg); 643 continue; 644 } 645 646 switch (Reg) { 647 case ARM::R4: 648 case ARM::R5: 649 case ARM::R6: 650 case ARM::R7: 651 case ARM::LR: 652 UnspilledCS1GPRs.push_back(Reg); 653 break; 654 default: 655 UnspilledCS2GPRs.push_back(Reg); 656 break; 657 } 658 } 659 } 660 } 661 662 bool ForceLRSpill = false; 663 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 664 unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 665 // Force LR to be spilled if the Thumb function size is > 2048. This enables 666 // use of BL to implement far jump. If it turns out that it's not needed 667 // then the branch fix up path will undo it. 668 if (FnSize >= (1 << 11)) { 669 CanEliminateFrame = false; 670 ForceLRSpill = true; 671 } 672 } 673 674 bool ExtraCSSpill = false; 675 if (!CanEliminateFrame || cannotEliminateFrame(MF)) { 676 AFI->setHasStackFrame(true); 677 678 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 679 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 680 if (!LRSpilled && CS1Spilled) { 681 MF.getRegInfo().setPhysRegUsed(ARM::LR); 682 AFI->setCSRegisterIsSpilled(ARM::LR); 683 NumGPRSpills++; 684 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 685 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 686 ForceLRSpill = false; 687 ExtraCSSpill = true; 688 } 689 690 // Darwin ABI requires FP to point to the stack slot that contains the 691 // previous FP. 692 if (STI.isTargetDarwin() || hasFP(MF)) { 693 MF.getRegInfo().setPhysRegUsed(FramePtr); 694 NumGPRSpills++; 695 } 696 697 // If stack and double are 8-byte aligned and we are spilling an odd number 698 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 699 // the integer and double callee save areas. 700 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 701 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 702 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 703 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 704 unsigned Reg = UnspilledCS1GPRs[i]; 705 // Don't spill high register if the function is thumb1 706 if (!AFI->isThumb1OnlyFunction() || 707 isARMLowRegister(Reg) || Reg == ARM::LR) { 708 MF.getRegInfo().setPhysRegUsed(Reg); 709 AFI->setCSRegisterIsSpilled(Reg); 710 if (!isReservedReg(MF, Reg)) 711 ExtraCSSpill = true; 712 break; 713 } 714 } 715 } else if (!UnspilledCS2GPRs.empty() && 716 !AFI->isThumb1OnlyFunction()) { 717 unsigned Reg = UnspilledCS2GPRs.front(); 718 MF.getRegInfo().setPhysRegUsed(Reg); 719 AFI->setCSRegisterIsSpilled(Reg); 720 if (!isReservedReg(MF, Reg)) 721 ExtraCSSpill = true; 722 } 723 } 724 725 // Estimate if we might need to scavenge a register at some point in order 726 // to materialize a stack offset. If so, either spill one additional 727 // callee-saved register or reserve a special spill slot to facilitate 728 // register scavenging. Thumb1 needs a spill slot for stack pointer 729 // adjustments also, even when the frame itself is small. 730 if (RS && !ExtraCSSpill) { 731 MachineFrameInfo *MFI = MF.getFrameInfo(); 732 // If any of the stack slot references may be out of range of an 733 // immediate offset, make sure a register (or a spill slot) is 734 // available for the register scavenger. Note that if we're indexing 735 // off the frame pointer, the effective stack size is 4 bytes larger 736 // since the FP points to the stack slot of the previous FP. 737 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0) 738 >= estimateRSStackSizeLimit(MF)) { 739 // If any non-reserved CS register isn't spilled, just spill one or two 740 // extra. That should take care of it! 741 unsigned NumExtras = TargetAlign / 4; 742 SmallVector<unsigned, 2> Extras; 743 while (NumExtras && !UnspilledCS1GPRs.empty()) { 744 unsigned Reg = UnspilledCS1GPRs.back(); 745 UnspilledCS1GPRs.pop_back(); 746 if (!isReservedReg(MF, Reg)) { 747 Extras.push_back(Reg); 748 NumExtras--; 749 } 750 } 751 // For non-Thumb1 functions, also check for hi-reg CS registers 752 if (!AFI->isThumb1OnlyFunction()) { 753 while (NumExtras && !UnspilledCS2GPRs.empty()) { 754 unsigned Reg = UnspilledCS2GPRs.back(); 755 UnspilledCS2GPRs.pop_back(); 756 if (!isReservedReg(MF, Reg)) { 757 Extras.push_back(Reg); 758 NumExtras--; 759 } 760 } 761 } 762 if (Extras.size() && NumExtras == 0) { 763 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 764 MF.getRegInfo().setPhysRegUsed(Extras[i]); 765 AFI->setCSRegisterIsSpilled(Extras[i]); 766 } 767 } else if (!AFI->isThumb1OnlyFunction()) { 768 // note: Thumb1 functions spill to R12, not the stack. 769 // Reserve a slot closest to SP or frame pointer. 770 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 771 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 772 RC->getAlignment(), 773 false)); 774 } 775 } 776 } 777 } 778 779 if (ForceLRSpill) { 780 MF.getRegInfo().setPhysRegUsed(ARM::LR); 781 AFI->setCSRegisterIsSpilled(ARM::LR); 782 AFI->setLRIsSpilledForFarJump(true); 783 } 784} 785 786unsigned ARMBaseRegisterInfo::getRARegister() const { 787 return ARM::LR; 788} 789 790unsigned 791ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 792 if (STI.isTargetDarwin() || hasFP(MF)) 793 return FramePtr; 794 return ARM::SP; 795} 796 797int 798ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI, 799 unsigned &FrameReg) const { 800 const MachineFrameInfo *MFI = MF.getFrameInfo(); 801 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 802 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 803 bool isFixed = MFI->isFixedObjectIndex(FI); 804 805 FrameReg = ARM::SP; 806 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 807 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 808 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 809 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 810 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 811 Offset -= AFI->getDPRCalleeSavedAreaOffset(); 812 else if (needsStackRealignment(MF)) { 813 // When dynamically realigning the stack, use the frame pointer for 814 // parameters, and the stack pointer for locals. 815 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 816 if (isFixed) { 817 FrameReg = getFrameRegister(MF); 818 Offset -= AFI->getFramePtrSpillOffset(); 819 } 820 } else if (hasFP(MF) && AFI->hasStackFrame()) { 821 if (isFixed || MFI->hasVarSizedObjects()) { 822 // Use frame pointer to reference fixed objects unless this is a 823 // frameless function. 824 FrameReg = getFrameRegister(MF); 825 Offset -= AFI->getFramePtrSpillOffset(); 826 } else if (AFI->isThumb2Function()) { 827 // In Thumb2 mode, the negative offset is very limited. 828 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 829 if (FPOffset >= -255 && FPOffset < 0) { 830 FrameReg = getFrameRegister(MF); 831 Offset = FPOffset; 832 } 833 } 834 } 835 return Offset; 836} 837 838 839int 840ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF, 841 int FI) const { 842 unsigned FrameReg; 843 return getFrameIndexReference(MF, FI, FrameReg); 844} 845 846unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 847 llvm_unreachable("What is the exception register"); 848 return 0; 849} 850 851unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 852 llvm_unreachable("What is the exception handler register"); 853 return 0; 854} 855 856int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 857 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 858} 859 860unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 861 const MachineFunction &MF) const { 862 switch (Reg) { 863 default: break; 864 // Return 0 if either register of the pair is a special register. 865 // So no R12, etc. 866 case ARM::R1: 867 return ARM::R0; 868 case ARM::R3: 869 return ARM::R2; 870 case ARM::R5: 871 return ARM::R4; 872 case ARM::R7: 873 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 874 case ARM::R9: 875 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 876 case ARM::R11: 877 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 878 879 case ARM::S1: 880 return ARM::S0; 881 case ARM::S3: 882 return ARM::S2; 883 case ARM::S5: 884 return ARM::S4; 885 case ARM::S7: 886 return ARM::S6; 887 case ARM::S9: 888 return ARM::S8; 889 case ARM::S11: 890 return ARM::S10; 891 case ARM::S13: 892 return ARM::S12; 893 case ARM::S15: 894 return ARM::S14; 895 case ARM::S17: 896 return ARM::S16; 897 case ARM::S19: 898 return ARM::S18; 899 case ARM::S21: 900 return ARM::S20; 901 case ARM::S23: 902 return ARM::S22; 903 case ARM::S25: 904 return ARM::S24; 905 case ARM::S27: 906 return ARM::S26; 907 case ARM::S29: 908 return ARM::S28; 909 case ARM::S31: 910 return ARM::S30; 911 912 case ARM::D1: 913 return ARM::D0; 914 case ARM::D3: 915 return ARM::D2; 916 case ARM::D5: 917 return ARM::D4; 918 case ARM::D7: 919 return ARM::D6; 920 case ARM::D9: 921 return ARM::D8; 922 case ARM::D11: 923 return ARM::D10; 924 case ARM::D13: 925 return ARM::D12; 926 case ARM::D15: 927 return ARM::D14; 928 case ARM::D17: 929 return ARM::D16; 930 case ARM::D19: 931 return ARM::D18; 932 case ARM::D21: 933 return ARM::D20; 934 case ARM::D23: 935 return ARM::D22; 936 case ARM::D25: 937 return ARM::D24; 938 case ARM::D27: 939 return ARM::D26; 940 case ARM::D29: 941 return ARM::D28; 942 case ARM::D31: 943 return ARM::D30; 944 } 945 946 return 0; 947} 948 949unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 950 const MachineFunction &MF) const { 951 switch (Reg) { 952 default: break; 953 // Return 0 if either register of the pair is a special register. 954 // So no R12, etc. 955 case ARM::R0: 956 return ARM::R1; 957 case ARM::R2: 958 return ARM::R3; 959 case ARM::R4: 960 return ARM::R5; 961 case ARM::R6: 962 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 963 case ARM::R8: 964 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 965 case ARM::R10: 966 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 967 968 case ARM::S0: 969 return ARM::S1; 970 case ARM::S2: 971 return ARM::S3; 972 case ARM::S4: 973 return ARM::S5; 974 case ARM::S6: 975 return ARM::S7; 976 case ARM::S8: 977 return ARM::S9; 978 case ARM::S10: 979 return ARM::S11; 980 case ARM::S12: 981 return ARM::S13; 982 case ARM::S14: 983 return ARM::S15; 984 case ARM::S16: 985 return ARM::S17; 986 case ARM::S18: 987 return ARM::S19; 988 case ARM::S20: 989 return ARM::S21; 990 case ARM::S22: 991 return ARM::S23; 992 case ARM::S24: 993 return ARM::S25; 994 case ARM::S26: 995 return ARM::S27; 996 case ARM::S28: 997 return ARM::S29; 998 case ARM::S30: 999 return ARM::S31; 1000 1001 case ARM::D0: 1002 return ARM::D1; 1003 case ARM::D2: 1004 return ARM::D3; 1005 case ARM::D4: 1006 return ARM::D5; 1007 case ARM::D6: 1008 return ARM::D7; 1009 case ARM::D8: 1010 return ARM::D9; 1011 case ARM::D10: 1012 return ARM::D11; 1013 case ARM::D12: 1014 return ARM::D13; 1015 case ARM::D14: 1016 return ARM::D15; 1017 case ARM::D16: 1018 return ARM::D17; 1019 case ARM::D18: 1020 return ARM::D19; 1021 case ARM::D20: 1022 return ARM::D21; 1023 case ARM::D22: 1024 return ARM::D23; 1025 case ARM::D24: 1026 return ARM::D25; 1027 case ARM::D26: 1028 return ARM::D27; 1029 case ARM::D28: 1030 return ARM::D29; 1031 case ARM::D30: 1032 return ARM::D31; 1033 } 1034 1035 return 0; 1036} 1037 1038/// emitLoadConstPool - Emits a load from constpool to materialize the 1039/// specified immediate. 1040void ARMBaseRegisterInfo:: 1041emitLoadConstPool(MachineBasicBlock &MBB, 1042 MachineBasicBlock::iterator &MBBI, 1043 DebugLoc dl, 1044 unsigned DestReg, unsigned SubIdx, int Val, 1045 ARMCC::CondCodes Pred, 1046 unsigned PredReg) const { 1047 MachineFunction &MF = *MBB.getParent(); 1048 MachineConstantPool *ConstantPool = MF.getConstantPool(); 1049 Constant *C = 1050 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1051 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1052 1053 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1054 .addReg(DestReg, getDefRegState(true), SubIdx) 1055 .addConstantPoolIndex(Idx) 1056 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1057} 1058 1059bool ARMBaseRegisterInfo:: 1060requiresRegisterScavenging(const MachineFunction &MF) const { 1061 return true; 1062} 1063 1064bool ARMBaseRegisterInfo:: 1065requiresFrameIndexScavenging(const MachineFunction &MF) const { 1066 return true; 1067} 1068 1069// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1070// not required, we reserve argument space for call sites in the function 1071// immediately on entry to the current function. This eliminates the need for 1072// add/sub sp brackets around call sites. Returns true if the call frame is 1073// included as part of the stack frame. 1074bool ARMBaseRegisterInfo:: 1075hasReservedCallFrame(MachineFunction &MF) const { 1076 const MachineFrameInfo *FFI = MF.getFrameInfo(); 1077 unsigned CFSize = FFI->getMaxCallFrameSize(); 1078 // It's not always a good idea to include the call frame as part of the 1079 // stack frame. ARM (especially Thumb) has small immediate offset to 1080 // address the stack frame. So a large call frame can cause poor codegen 1081 // and may even makes it impossible to scavenge a register. 1082 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1083 return false; 1084 1085 return !MF.getFrameInfo()->hasVarSizedObjects(); 1086} 1087 1088// canSimplifyCallFramePseudos - If there is a reserved call frame, the 1089// call frame pseudos can be simplified. Unlike most targets, having a FP 1090// is not sufficient here since we still may reference some objects via SP 1091// even when FP is available in Thumb2 mode. 1092bool ARMBaseRegisterInfo:: 1093canSimplifyCallFramePseudos(MachineFunction &MF) const { 1094 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1095 return hasReservedCallFrame(MF) || (AFI->isThumb1OnlyFunction() && hasFP(MF)); 1096} 1097 1098static void 1099emitSPUpdate(bool isARM, 1100 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 1101 DebugLoc dl, const ARMBaseInstrInfo &TII, 1102 int NumBytes, 1103 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 1104 if (isARM) 1105 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1106 Pred, PredReg, TII); 1107 else 1108 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1109 Pred, PredReg, TII); 1110} 1111 1112 1113void ARMBaseRegisterInfo:: 1114eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1115 MachineBasicBlock::iterator I) const { 1116 if (!hasReservedCallFrame(MF)) { 1117 // If we have alloca, convert as follows: 1118 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1119 // ADJCALLSTACKUP -> add, sp, sp, amount 1120 MachineInstr *Old = I; 1121 DebugLoc dl = Old->getDebugLoc(); 1122 unsigned Amount = Old->getOperand(0).getImm(); 1123 if (Amount != 0) { 1124 // We need to keep the stack aligned properly. To do this, we round the 1125 // amount of space needed for the outgoing arguments up to the next 1126 // alignment boundary. 1127 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1128 Amount = (Amount+Align-1)/Align*Align; 1129 1130 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1131 assert(!AFI->isThumb1OnlyFunction() && 1132 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 1133 bool isARM = !AFI->isThumbFunction(); 1134 1135 // Replace the pseudo instruction with a new instruction... 1136 unsigned Opc = Old->getOpcode(); 1137 int PIdx = Old->findFirstPredOperandIdx(); 1138 ARMCC::CondCodes Pred = (PIdx == -1) 1139 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 1140 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1141 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1142 unsigned PredReg = Old->getOperand(2).getReg(); 1143 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1144 } else { 1145 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1146 unsigned PredReg = Old->getOperand(3).getReg(); 1147 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1148 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1149 } 1150 } 1151 } 1152 MBB.erase(I); 1153} 1154 1155unsigned 1156ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1157 int SPAdj, int *Value, 1158 RegScavenger *RS) const { 1159 unsigned i = 0; 1160 MachineInstr &MI = *II; 1161 MachineBasicBlock &MBB = *MI.getParent(); 1162 MachineFunction &MF = *MBB.getParent(); 1163 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1164 assert(!AFI->isThumb1OnlyFunction() && 1165 "This eliminateFrameIndex does not support Thumb1!"); 1166 1167 while (!MI.getOperand(i).isFI()) { 1168 ++i; 1169 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1170 } 1171 1172 int FrameIndex = MI.getOperand(i).getIndex(); 1173 unsigned FrameReg; 1174 1175 int Offset = getFrameIndexReference(MF, FrameIndex, FrameReg); 1176 if (FrameReg != ARM::SP) 1177 SPAdj = 0; 1178 Offset += SPAdj; 1179 1180 // Modify MI as necessary to handle as much of 'Offset' as possible 1181 bool Done = false; 1182 if (!AFI->isThumbFunction()) 1183 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 1184 else { 1185 assert(AFI->isThumb2Function()); 1186 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 1187 } 1188 if (Done) 1189 return 0; 1190 1191 // If we get here, the immediate doesn't fit into the instruction. We folded 1192 // as much as possible above, handle the rest, providing a register that is 1193 // SP+LargeImm. 1194 assert((Offset || 1195 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1196 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1197 "This code isn't needed if offset already handled!"); 1198 1199 unsigned ScratchReg = 0; 1200 int PIdx = MI.findFirstPredOperandIdx(); 1201 ARMCC::CondCodes Pred = (PIdx == -1) 1202 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1203 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1204 if (Offset == 0) 1205 // Must be addrmode4/6. 1206 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1207 else { 1208 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1209 if (Value) *Value = Offset; 1210 if (!AFI->isThumbFunction()) 1211 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1212 Offset, Pred, PredReg, TII); 1213 else { 1214 assert(AFI->isThumb2Function()); 1215 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1216 Offset, Pred, PredReg, TII); 1217 } 1218 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1219 if (!ReuseFrameIndexVals) 1220 ScratchReg = 0; 1221 } 1222 return ScratchReg; 1223} 1224 1225/// Move iterator past the next bunch of callee save load / store ops for 1226/// the particular spill area (1: integer area 1, 2: integer area 2, 1227/// 3: fp area, 0: don't care). 1228static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1229 MachineBasicBlock::iterator &MBBI, 1230 int Opc1, int Opc2, unsigned Area, 1231 const ARMSubtarget &STI) { 1232 while (MBBI != MBB.end() && 1233 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 1234 MBBI->getOperand(1).isFI()) { 1235 if (Area != 0) { 1236 bool Done = false; 1237 unsigned Category = 0; 1238 switch (MBBI->getOperand(0).getReg()) { 1239 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1240 case ARM::LR: 1241 Category = 1; 1242 break; 1243 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1244 Category = STI.isTargetDarwin() ? 2 : 1; 1245 break; 1246 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1247 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1248 Category = 3; 1249 break; 1250 default: 1251 Done = true; 1252 break; 1253 } 1254 if (Done || Category != Area) 1255 break; 1256 } 1257 1258 ++MBBI; 1259 } 1260} 1261 1262void ARMBaseRegisterInfo:: 1263emitPrologue(MachineFunction &MF) const { 1264 MachineBasicBlock &MBB = MF.front(); 1265 MachineBasicBlock::iterator MBBI = MBB.begin(); 1266 MachineFrameInfo *MFI = MF.getFrameInfo(); 1267 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1268 assert(!AFI->isThumb1OnlyFunction() && 1269 "This emitPrologue does not support Thumb1!"); 1270 bool isARM = !AFI->isThumbFunction(); 1271 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1272 unsigned NumBytes = MFI->getStackSize(); 1273 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1274 DebugLoc dl = (MBBI != MBB.end() ? 1275 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1276 1277 // Determine the sizes of each callee-save spill areas and record which frame 1278 // belongs to which callee-save spill areas. 1279 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1280 int FramePtrSpillFI = 0; 1281 1282 // Allocate the vararg register save area. This is not counted in NumBytes. 1283 if (VARegSaveSize) 1284 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1285 1286 if (!AFI->hasStackFrame()) { 1287 if (NumBytes != 0) 1288 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1289 return; 1290 } 1291 1292 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1293 unsigned Reg = CSI[i].getReg(); 1294 int FI = CSI[i].getFrameIdx(); 1295 switch (Reg) { 1296 case ARM::R4: 1297 case ARM::R5: 1298 case ARM::R6: 1299 case ARM::R7: 1300 case ARM::LR: 1301 if (Reg == FramePtr) 1302 FramePtrSpillFI = FI; 1303 AFI->addGPRCalleeSavedArea1Frame(FI); 1304 GPRCS1Size += 4; 1305 break; 1306 case ARM::R8: 1307 case ARM::R9: 1308 case ARM::R10: 1309 case ARM::R11: 1310 if (Reg == FramePtr) 1311 FramePtrSpillFI = FI; 1312 if (STI.isTargetDarwin()) { 1313 AFI->addGPRCalleeSavedArea2Frame(FI); 1314 GPRCS2Size += 4; 1315 } else { 1316 AFI->addGPRCalleeSavedArea1Frame(FI); 1317 GPRCS1Size += 4; 1318 } 1319 break; 1320 default: 1321 AFI->addDPRCalleeSavedAreaFrame(FI); 1322 DPRCSSize += 8; 1323 } 1324 } 1325 1326 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1327 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 1328 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1329 1330 // Set FP to point to the stack slot that contains the previous FP. 1331 // For Darwin, FP is R7, which has now been stored in spill area 1. 1332 // Otherwise, if this is not Darwin, all the callee-saved registers go 1333 // into spill area 1, including the FP in R11. In either case, it is 1334 // now safe to emit this assignment. 1335 if (STI.isTargetDarwin() || hasFP(MF)) { 1336 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1337 MachineInstrBuilder MIB = 1338 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1339 .addFrameIndex(FramePtrSpillFI).addImm(0); 1340 AddDefaultCC(AddDefaultPred(MIB)); 1341 } 1342 1343 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1344 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1345 1346 // Build the new SUBri to adjust SP for FP callee-save spill area. 1347 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 1348 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1349 1350 // Determine starting offsets of spill areas. 1351 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1352 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1353 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1354 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1355 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1356 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1357 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1358 1359 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); 1360 NumBytes = DPRCSOffset; 1361 if (NumBytes) { 1362 // Adjust SP after all the callee-save spills. 1363 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1364 } 1365 1366 if (STI.isTargetELF() && hasFP(MF)) { 1367 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1368 AFI->getFramePtrSpillOffset()); 1369 } 1370 1371 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1372 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1373 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1374 1375 // If we need dynamic stack realignment, do it here. 1376 if (needsStackRealignment(MF)) { 1377 unsigned MaxAlign = MFI->getMaxAlignment(); 1378 assert (!AFI->isThumb1OnlyFunction()); 1379 if (!AFI->isThumbFunction()) { 1380 // Emit bic sp, sp, MaxAlign 1381 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 1382 TII.get(ARM::BICri), ARM::SP) 1383 .addReg(ARM::SP, RegState::Kill) 1384 .addImm(MaxAlign-1))); 1385 } else { 1386 // We cannot use sp as source/dest register here, thus we're emitting the 1387 // following sequence: 1388 // mov r4, sp 1389 // bic r4, r4, MaxAlign 1390 // mov sp, r4 1391 // FIXME: It will be better just to find spare register here. 1392 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4) 1393 .addReg(ARM::SP, RegState::Kill); 1394 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 1395 TII.get(ARM::t2BICri), ARM::R4) 1396 .addReg(ARM::R4, RegState::Kill) 1397 .addImm(MaxAlign-1))); 1398 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) 1399 .addReg(ARM::R4, RegState::Kill); 1400 } 1401 } 1402} 1403 1404static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1405 for (unsigned i = 0; CSRegs[i]; ++i) 1406 if (Reg == CSRegs[i]) 1407 return true; 1408 return false; 1409} 1410 1411static bool isCSRestore(MachineInstr *MI, 1412 const ARMBaseInstrInfo &TII, 1413 const unsigned *CSRegs) { 1414 return ((MI->getOpcode() == (int)ARM::VLDRD || 1415 MI->getOpcode() == (int)ARM::LDR || 1416 MI->getOpcode() == (int)ARM::t2LDRi12) && 1417 MI->getOperand(1).isFI() && 1418 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1419} 1420 1421void ARMBaseRegisterInfo:: 1422emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1423 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1424 assert(MBBI->getDesc().isReturn() && 1425 "Can only insert epilog into returning blocks"); 1426 DebugLoc dl = MBBI->getDebugLoc(); 1427 MachineFrameInfo *MFI = MF.getFrameInfo(); 1428 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1429 assert(!AFI->isThumb1OnlyFunction() && 1430 "This emitEpilogue does not support Thumb1!"); 1431 bool isARM = !AFI->isThumbFunction(); 1432 1433 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1434 int NumBytes = (int)MFI->getStackSize(); 1435 1436 if (!AFI->hasStackFrame()) { 1437 if (NumBytes != 0) 1438 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1439 } else { 1440 // Unwind MBBI to point to first LDR / VLDRD. 1441 const unsigned *CSRegs = getCalleeSavedRegs(); 1442 if (MBBI != MBB.begin()) { 1443 do 1444 --MBBI; 1445 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 1446 if (!isCSRestore(MBBI, TII, CSRegs)) 1447 ++MBBI; 1448 } 1449 1450 // Move SP to start of FP callee save spill area. 1451 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1452 AFI->getGPRCalleeSavedArea2Size() + 1453 AFI->getDPRCalleeSavedAreaSize()); 1454 1455 // Darwin ABI requires FP to point to the stack slot that contains the 1456 // previous FP. 1457 bool HasFP = hasFP(MF); 1458 if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1459 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1460 // Reset SP based on frame pointer only if the stack frame extends beyond 1461 // frame pointer stack slot or target is ELF and the function has FP. 1462 if (HasFP || 1463 AFI->getGPRCalleeSavedArea2Size() || 1464 AFI->getDPRCalleeSavedAreaSize() || 1465 AFI->getDPRCalleeSavedAreaOffset()) { 1466 if (NumBytes) { 1467 if (isARM) 1468 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1469 ARMCC::AL, 0, TII); 1470 else 1471 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1472 ARMCC::AL, 0, TII); 1473 } else { 1474 // Thumb2 or ARM. 1475 if (isARM) 1476 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1477 .addReg(FramePtr) 1478 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1479 else 1480 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1481 .addReg(FramePtr); 1482 } 1483 } 1484 } else if (NumBytes) 1485 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1486 1487 // Move SP to start of integer callee save spill area 2. 1488 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); 1489 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1490 1491 // Move SP to start of integer callee save spill area 1. 1492 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 1493 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1494 1495 // Move SP to SP upon entry to the function. 1496 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 1497 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1498 } 1499 1500 if (VARegSaveSize) 1501 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1502} 1503 1504#include "ARMGenRegisterInfo.inc" 1505