ARMBaseRegisterInfo.cpp revision e7bd51980a1341fb60322e5922cfcc0c9b92b165
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/RegisterScavenging.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetFrameLowering.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include "llvm/ADT/BitVector.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/Support/CommandLine.h" 40 41#define GET_REGINFO_TARGET_DESC 42#include "ARMGenRegisterInfo.inc" 43 44using namespace llvm; 45 46static cl::opt<bool> 47ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), 48 cl::desc("Force use of virtual base registers for stack load/store")); 49static cl::opt<bool> 50EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, 51 cl::desc("Enable pre-regalloc stack frame index allocation")); 52static cl::opt<bool> 53EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), 54 cl::desc("Enable use of a base pointer for complex stack frames")); 55 56ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 57 const ARMSubtarget &sti) 58 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), 59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 60 BasePtr(ARM::R6) { 61} 62 63const uint16_t* 64ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 65 bool ghcCall = false; 66 67 if (MF) { 68 const Function *F = MF->getFunction(); 69 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 70 } 71 72 if (ghcCall) { 73 return CSR_GHC_SaveList; 74 } 75 else { 76 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 77 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 78 } 79} 80 81const uint32_t* 82ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 83 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 84 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 85} 86 87const uint32_t* 88ARMBaseRegisterInfo::getNoPreservedMask() const { 89 return CSR_NoRegs_RegMask; 90} 91 92BitVector ARMBaseRegisterInfo:: 93getReservedRegs(const MachineFunction &MF) const { 94 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 95 96 // FIXME: avoid re-calculating this every time. 97 BitVector Reserved(getNumRegs()); 98 Reserved.set(ARM::SP); 99 Reserved.set(ARM::PC); 100 Reserved.set(ARM::FPSCR); 101 if (TFI->hasFP(MF)) 102 Reserved.set(FramePtr); 103 if (hasBasePointer(MF)) 104 Reserved.set(BasePtr); 105 // Some targets reserve R9. 106 if (STI.isR9Reserved()) 107 Reserved.set(ARM::R9); 108 // Reserve D16-D31 if the subtarget doesn't support them. 109 if (!STI.hasVFP3() || STI.hasD16()) { 110 assert(ARM::D31 == ARM::D16 + 15); 111 for (unsigned i = 0; i != 16; ++i) 112 Reserved.set(ARM::D16 + i); 113 } 114 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 115 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 116 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 117 if (Reserved.test(*SI)) Reserved.set(*I); 118 119 return Reserved; 120} 121 122const TargetRegisterClass* 123ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 124 const { 125 const TargetRegisterClass *Super = RC; 126 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 127 do { 128 switch (Super->getID()) { 129 case ARM::GPRRegClassID: 130 case ARM::SPRRegClassID: 131 case ARM::DPRRegClassID: 132 case ARM::QPRRegClassID: 133 case ARM::QQPRRegClassID: 134 case ARM::QQQQPRRegClassID: 135 case ARM::GPRPairRegClassID: 136 return Super; 137 } 138 Super = *I++; 139 } while (Super); 140 return RC; 141} 142 143const TargetRegisterClass * 144ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 145 const { 146 return &ARM::GPRRegClass; 147} 148 149const TargetRegisterClass * 150ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 151 if (RC == &ARM::CCRRegClass) 152 return 0; // Can't copy CCR registers. 153 return RC; 154} 155 156unsigned 157ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 158 MachineFunction &MF) const { 159 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 160 161 switch (RC->getID()) { 162 default: 163 return 0; 164 case ARM::tGPRRegClassID: 165 return TFI->hasFP(MF) ? 4 : 5; 166 case ARM::GPRRegClassID: { 167 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 168 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 169 } 170 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 171 case ARM::DPRRegClassID: 172 return 32 - 10; 173 } 174} 175 176/// getRawAllocationOrder - Returns the register allocation order for a 177/// specified register class with a target-dependent hint. 178ArrayRef<uint16_t> 179ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, 180 unsigned HintType, unsigned HintReg, 181 const MachineFunction &MF) const { 182 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 183 // Alternative register allocation orders when favoring even / odd registers 184 // of register pairs. 185 186 // No FP, R9 is available. 187 static const uint16_t GPREven1[] = { 188 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 189 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 190 ARM::R9, ARM::R11 191 }; 192 static const uint16_t GPROdd1[] = { 193 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 194 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 195 ARM::R8, ARM::R10 196 }; 197 198 // FP is R7, R9 is available. 199 static const uint16_t GPREven2[] = { 200 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 201 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 202 ARM::R9, ARM::R11 203 }; 204 static const uint16_t GPROdd2[] = { 205 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 206 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 207 ARM::R8, ARM::R10 208 }; 209 210 // FP is R11, R9 is available. 211 static const uint16_t GPREven3[] = { 212 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 213 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 214 ARM::R9 215 }; 216 static const uint16_t GPROdd3[] = { 217 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 218 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 219 ARM::R8 220 }; 221 222 // No FP, R9 is not available. 223 static const uint16_t GPREven4[] = { 224 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 225 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 226 ARM::R11 227 }; 228 static const uint16_t GPROdd4[] = { 229 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 230 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 231 ARM::R10 232 }; 233 234 // FP is R7, R9 is not available. 235 static const uint16_t GPREven5[] = { 236 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 237 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 238 ARM::R11 239 }; 240 static const uint16_t GPROdd5[] = { 241 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 242 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 243 ARM::R10 244 }; 245 246 // FP is R11, R9 is not available. 247 static const uint16_t GPREven6[] = { 248 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 249 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 250 }; 251 static const uint16_t GPROdd6[] = { 252 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 253 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 254 }; 255 256 // We only support even/odd hints for GPR and rGPR. 257 if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass) 258 return RC->getRawAllocationOrder(MF); 259 260 if (HintType == ARMRI::RegPairEven) { 261 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 262 // It's no longer possible to fulfill this hint. Return the default 263 // allocation order. 264 return RC->getRawAllocationOrder(MF); 265 266 if (!TFI->hasFP(MF)) { 267 if (!STI.isR9Reserved()) 268 return makeArrayRef(GPREven1); 269 else 270 return makeArrayRef(GPREven4); 271 } else if (FramePtr == ARM::R7) { 272 if (!STI.isR9Reserved()) 273 return makeArrayRef(GPREven2); 274 else 275 return makeArrayRef(GPREven5); 276 } else { // FramePtr == ARM::R11 277 if (!STI.isR9Reserved()) 278 return makeArrayRef(GPREven3); 279 else 280 return makeArrayRef(GPREven6); 281 } 282 } else if (HintType == ARMRI::RegPairOdd) { 283 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 284 // It's no longer possible to fulfill this hint. Return the default 285 // allocation order. 286 return RC->getRawAllocationOrder(MF); 287 288 if (!TFI->hasFP(MF)) { 289 if (!STI.isR9Reserved()) 290 return makeArrayRef(GPROdd1); 291 else 292 return makeArrayRef(GPROdd4); 293 } else if (FramePtr == ARM::R7) { 294 if (!STI.isR9Reserved()) 295 return makeArrayRef(GPROdd2); 296 else 297 return makeArrayRef(GPROdd5); 298 } else { // FramePtr == ARM::R11 299 if (!STI.isR9Reserved()) 300 return makeArrayRef(GPROdd3); 301 else 302 return makeArrayRef(GPROdd6); 303 } 304 } 305 return RC->getRawAllocationOrder(MF); 306} 307 308/// ResolveRegAllocHint - Resolves the specified register allocation hint 309/// to a physical register. Returns the physical register if it is successful. 310unsigned 311ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 312 const MachineFunction &MF) const { 313 if (Reg == 0 || !isPhysicalRegister(Reg)) 314 return 0; 315 if (Type == 0) 316 return Reg; 317 else if (Type == (unsigned)ARMRI::RegPairOdd) 318 // Odd register. 319 return getRegisterPairOdd(Reg, MF); 320 else if (Type == (unsigned)ARMRI::RegPairEven) 321 // Even register. 322 return getRegisterPairEven(Reg, MF); 323 return 0; 324} 325 326void 327ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 328 MachineFunction &MF) const { 329 MachineRegisterInfo *MRI = &MF.getRegInfo(); 330 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 331 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 332 Hint.first == (unsigned)ARMRI::RegPairEven) && 333 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 334 // If 'Reg' is one of the even / odd register pair and it's now changed 335 // (e.g. coalesced) into a different register. The other register of the 336 // pair allocation hint must be updated to reflect the relationship 337 // change. 338 unsigned OtherReg = Hint.second; 339 Hint = MRI->getRegAllocationHint(OtherReg); 340 if (Hint.second == Reg) 341 // Make sure the pair has not already divorced. 342 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 343 } 344} 345 346bool 347ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 348 // CortexA9 has a Write-after-write hazard for NEON registers. 349 if (!STI.isLikeA9()) 350 return false; 351 352 switch (RC->getID()) { 353 case ARM::DPRRegClassID: 354 case ARM::DPR_8RegClassID: 355 case ARM::DPR_VFP2RegClassID: 356 case ARM::QPRRegClassID: 357 case ARM::QPR_8RegClassID: 358 case ARM::QPR_VFP2RegClassID: 359 case ARM::SPRRegClassID: 360 case ARM::SPR_8RegClassID: 361 // Avoid reusing S, D, and Q registers. 362 // Don't increase register pressure for QQ and QQQQ. 363 return true; 364 default: 365 return false; 366 } 367} 368 369bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 370 const MachineFrameInfo *MFI = MF.getFrameInfo(); 371 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 372 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 373 374 if (!EnableBasePointer) 375 return false; 376 377 // When outgoing call frames are so large that we adjust the stack pointer 378 // around the call, we can no longer use the stack pointer to reach the 379 // emergency spill slot. 380 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 381 return true; 382 383 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 384 // negative range for ldr/str (255), and thumb1 is positive offsets only. 385 // It's going to be better to use the SP or Base Pointer instead. When there 386 // are variable sized objects, we can't reference off of the SP, so we 387 // reserve a Base Pointer. 388 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 389 // Conservatively estimate whether the negative offset from the frame 390 // pointer will be sufficient to reach. If a function has a smallish 391 // frame, it's less likely to have lots of spills and callee saved 392 // space, so it's all more likely to be within range of the frame pointer. 393 // If it's wrong, the scavenger will still enable access to work, it just 394 // won't be optimal. 395 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 396 return false; 397 return true; 398 } 399 400 return false; 401} 402 403bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 404 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 405 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 406 // We can't realign the stack if: 407 // 1. Dynamic stack realignment is explicitly disabled, 408 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 409 // 3. There are VLAs in the function and the base pointer is disabled. 410 if (!MF.getTarget().Options.RealignStack) 411 return false; 412 if (AFI->isThumb1OnlyFunction()) 413 return false; 414 // Stack realignment requires a frame pointer. If we already started 415 // register allocation with frame pointer elimination, it is too late now. 416 if (!MRI->canReserveReg(FramePtr)) 417 return false; 418 // We may also need a base pointer if there are dynamic allocas or stack 419 // pointer adjustments around calls. 420 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 421 return true; 422 if (!EnableBasePointer) 423 return false; 424 // A base pointer is required and allowed. Check that it isn't too late to 425 // reserve it. 426 return MRI->canReserveReg(BasePtr); 427} 428 429bool ARMBaseRegisterInfo:: 430needsStackRealignment(const MachineFunction &MF) const { 431 const MachineFrameInfo *MFI = MF.getFrameInfo(); 432 const Function *F = MF.getFunction(); 433 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 434 bool requiresRealignment = 435 ((MFI->getMaxAlignment() > StackAlign) || 436 F->getFnAttributes().hasAttribute(Attributes::StackAlignment)); 437 438 return requiresRealignment && canRealignStack(MF); 439} 440 441bool ARMBaseRegisterInfo:: 442cannotEliminateFrame(const MachineFunction &MF) const { 443 const MachineFrameInfo *MFI = MF.getFrameInfo(); 444 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 445 return true; 446 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 447 || needsStackRealignment(MF); 448} 449 450unsigned 451ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 452 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 453 454 if (TFI->hasFP(MF)) 455 return FramePtr; 456 return ARM::SP; 457} 458 459unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 460 llvm_unreachable("What is the exception register"); 461} 462 463unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 464 llvm_unreachable("What is the exception handler register"); 465} 466 467unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 468 const MachineFunction &MF) const { 469 const MachineRegisterInfo &MRI = MF.getRegInfo(); 470 switch (Reg) { 471 default: break; 472 // Return 0 if either register of the pair is a special register. 473 // So no R12, etc. 474 case ARM::R1: return ARM::R0; 475 case ARM::R3: return ARM::R2; 476 case ARM::R5: return ARM::R4; 477 case ARM::R7: 478 return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6)) 479 ? 0 : ARM::R6; 480 case ARM::R9: return MRI.isReserved(ARM::R9) ? 0 :ARM::R8; 481 case ARM::R11: return MRI.isReserved(ARM::R11) ? 0 : ARM::R10; 482 483 case ARM::S1: return ARM::S0; 484 case ARM::S3: return ARM::S2; 485 case ARM::S5: return ARM::S4; 486 case ARM::S7: return ARM::S6; 487 case ARM::S9: return ARM::S8; 488 case ARM::S11: return ARM::S10; 489 case ARM::S13: return ARM::S12; 490 case ARM::S15: return ARM::S14; 491 case ARM::S17: return ARM::S16; 492 case ARM::S19: return ARM::S18; 493 case ARM::S21: return ARM::S20; 494 case ARM::S23: return ARM::S22; 495 case ARM::S25: return ARM::S24; 496 case ARM::S27: return ARM::S26; 497 case ARM::S29: return ARM::S28; 498 case ARM::S31: return ARM::S30; 499 500 case ARM::D1: return ARM::D0; 501 case ARM::D3: return ARM::D2; 502 case ARM::D5: return ARM::D4; 503 case ARM::D7: return ARM::D6; 504 case ARM::D9: return ARM::D8; 505 case ARM::D11: return ARM::D10; 506 case ARM::D13: return ARM::D12; 507 case ARM::D15: return ARM::D14; 508 case ARM::D17: return ARM::D16; 509 case ARM::D19: return ARM::D18; 510 case ARM::D21: return ARM::D20; 511 case ARM::D23: return ARM::D22; 512 case ARM::D25: return ARM::D24; 513 case ARM::D27: return ARM::D26; 514 case ARM::D29: return ARM::D28; 515 case ARM::D31: return ARM::D30; 516 } 517 518 return 0; 519} 520 521unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 522 const MachineFunction &MF) const { 523 const MachineRegisterInfo &MRI = MF.getRegInfo(); 524 switch (Reg) { 525 default: break; 526 // Return 0 if either register of the pair is a special register. 527 // So no R12, etc. 528 case ARM::R0: return ARM::R1; 529 case ARM::R2: return ARM::R3; 530 case ARM::R4: return ARM::R5; 531 case ARM::R6: 532 return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6)) 533 ? 0 : ARM::R7; 534 case ARM::R8: return MRI.isReserved(ARM::R9) ? 0 :ARM::R9; 535 case ARM::R10: return MRI.isReserved(ARM::R11) ? 0 : ARM::R11; 536 537 case ARM::S0: return ARM::S1; 538 case ARM::S2: return ARM::S3; 539 case ARM::S4: return ARM::S5; 540 case ARM::S6: return ARM::S7; 541 case ARM::S8: return ARM::S9; 542 case ARM::S10: return ARM::S11; 543 case ARM::S12: return ARM::S13; 544 case ARM::S14: return ARM::S15; 545 case ARM::S16: return ARM::S17; 546 case ARM::S18: return ARM::S19; 547 case ARM::S20: return ARM::S21; 548 case ARM::S22: return ARM::S23; 549 case ARM::S24: return ARM::S25; 550 case ARM::S26: return ARM::S27; 551 case ARM::S28: return ARM::S29; 552 case ARM::S30: return ARM::S31; 553 554 case ARM::D0: return ARM::D1; 555 case ARM::D2: return ARM::D3; 556 case ARM::D4: return ARM::D5; 557 case ARM::D6: return ARM::D7; 558 case ARM::D8: return ARM::D9; 559 case ARM::D10: return ARM::D11; 560 case ARM::D12: return ARM::D13; 561 case ARM::D14: return ARM::D15; 562 case ARM::D16: return ARM::D17; 563 case ARM::D18: return ARM::D19; 564 case ARM::D20: return ARM::D21; 565 case ARM::D22: return ARM::D23; 566 case ARM::D24: return ARM::D25; 567 case ARM::D26: return ARM::D27; 568 case ARM::D28: return ARM::D29; 569 case ARM::D30: return ARM::D31; 570 } 571 572 return 0; 573} 574 575/// emitLoadConstPool - Emits a load from constpool to materialize the 576/// specified immediate. 577void ARMBaseRegisterInfo:: 578emitLoadConstPool(MachineBasicBlock &MBB, 579 MachineBasicBlock::iterator &MBBI, 580 DebugLoc dl, 581 unsigned DestReg, unsigned SubIdx, int Val, 582 ARMCC::CondCodes Pred, 583 unsigned PredReg, unsigned MIFlags) const { 584 MachineFunction &MF = *MBB.getParent(); 585 MachineConstantPool *ConstantPool = MF.getConstantPool(); 586 const Constant *C = 587 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 588 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 589 590 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 591 .addReg(DestReg, getDefRegState(true), SubIdx) 592 .addConstantPoolIndex(Idx) 593 .addImm(0).addImm(Pred).addReg(PredReg) 594 .setMIFlags(MIFlags); 595} 596 597bool ARMBaseRegisterInfo:: 598requiresRegisterScavenging(const MachineFunction &MF) const { 599 return true; 600} 601 602bool ARMBaseRegisterInfo:: 603trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 604 return true; 605} 606 607bool ARMBaseRegisterInfo:: 608requiresFrameIndexScavenging(const MachineFunction &MF) const { 609 return true; 610} 611 612bool ARMBaseRegisterInfo:: 613requiresVirtualBaseRegisters(const MachineFunction &MF) const { 614 return EnableLocalStackAlloc; 615} 616 617static void 618emitSPUpdate(bool isARM, 619 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 620 DebugLoc dl, const ARMBaseInstrInfo &TII, 621 int NumBytes, 622 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 623 if (isARM) 624 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 625 Pred, PredReg, TII); 626 else 627 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 628 Pred, PredReg, TII); 629} 630 631 632void ARMBaseRegisterInfo:: 633eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 634 MachineBasicBlock::iterator I) const { 635 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 636 if (!TFI->hasReservedCallFrame(MF)) { 637 // If we have alloca, convert as follows: 638 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 639 // ADJCALLSTACKUP -> add, sp, sp, amount 640 MachineInstr *Old = I; 641 DebugLoc dl = Old->getDebugLoc(); 642 unsigned Amount = Old->getOperand(0).getImm(); 643 if (Amount != 0) { 644 // We need to keep the stack aligned properly. To do this, we round the 645 // amount of space needed for the outgoing arguments up to the next 646 // alignment boundary. 647 unsigned Align = TFI->getStackAlignment(); 648 Amount = (Amount+Align-1)/Align*Align; 649 650 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 651 assert(!AFI->isThumb1OnlyFunction() && 652 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 653 bool isARM = !AFI->isThumbFunction(); 654 655 // Replace the pseudo instruction with a new instruction... 656 unsigned Opc = Old->getOpcode(); 657 int PIdx = Old->findFirstPredOperandIdx(); 658 ARMCC::CondCodes Pred = (PIdx == -1) 659 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 660 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 661 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 662 unsigned PredReg = Old->getOperand(2).getReg(); 663 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 664 } else { 665 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 666 unsigned PredReg = Old->getOperand(3).getReg(); 667 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 668 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 669 } 670 } 671 } 672 MBB.erase(I); 673} 674 675int64_t ARMBaseRegisterInfo:: 676getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 677 const MCInstrDesc &Desc = MI->getDesc(); 678 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 679 int64_t InstrOffs = 0; 680 int Scale = 1; 681 unsigned ImmIdx = 0; 682 switch (AddrMode) { 683 case ARMII::AddrModeT2_i8: 684 case ARMII::AddrModeT2_i12: 685 case ARMII::AddrMode_i12: 686 InstrOffs = MI->getOperand(Idx+1).getImm(); 687 Scale = 1; 688 break; 689 case ARMII::AddrMode5: { 690 // VFP address mode. 691 const MachineOperand &OffOp = MI->getOperand(Idx+1); 692 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 693 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 694 InstrOffs = -InstrOffs; 695 Scale = 4; 696 break; 697 } 698 case ARMII::AddrMode2: { 699 ImmIdx = Idx+2; 700 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 701 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 702 InstrOffs = -InstrOffs; 703 break; 704 } 705 case ARMII::AddrMode3: { 706 ImmIdx = Idx+2; 707 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 708 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 709 InstrOffs = -InstrOffs; 710 break; 711 } 712 case ARMII::AddrModeT1_s: { 713 ImmIdx = Idx+1; 714 InstrOffs = MI->getOperand(ImmIdx).getImm(); 715 Scale = 4; 716 break; 717 } 718 default: 719 llvm_unreachable("Unsupported addressing mode!"); 720 } 721 722 return InstrOffs * Scale; 723} 724 725/// needsFrameBaseReg - Returns true if the instruction's frame index 726/// reference would be better served by a base register other than FP 727/// or SP. Used by LocalStackFrameAllocation to determine which frame index 728/// references it should create new base registers for. 729bool ARMBaseRegisterInfo:: 730needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 731 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 732 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 733 } 734 735 // It's the load/store FI references that cause issues, as it can be difficult 736 // to materialize the offset if it won't fit in the literal field. Estimate 737 // based on the size of the local frame and some conservative assumptions 738 // about the rest of the stack frame (note, this is pre-regalloc, so 739 // we don't know everything for certain yet) whether this offset is likely 740 // to be out of range of the immediate. Return true if so. 741 742 // We only generate virtual base registers for loads and stores, so 743 // return false for everything else. 744 unsigned Opc = MI->getOpcode(); 745 switch (Opc) { 746 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 747 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 748 case ARM::t2LDRi12: case ARM::t2LDRi8: 749 case ARM::t2STRi12: case ARM::t2STRi8: 750 case ARM::VLDRS: case ARM::VLDRD: 751 case ARM::VSTRS: case ARM::VSTRD: 752 case ARM::tSTRspi: case ARM::tLDRspi: 753 if (ForceAllBaseRegAlloc) 754 return true; 755 break; 756 default: 757 return false; 758 } 759 760 // Without a virtual base register, if the function has variable sized 761 // objects, all fixed-size local references will be via the frame pointer, 762 // Approximate the offset and see if it's legal for the instruction. 763 // Note that the incoming offset is based on the SP value at function entry, 764 // so it'll be negative. 765 MachineFunction &MF = *MI->getParent()->getParent(); 766 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 767 MachineFrameInfo *MFI = MF.getFrameInfo(); 768 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 769 770 // Estimate an offset from the frame pointer. 771 // Conservatively assume all callee-saved registers get pushed. R4-R6 772 // will be earlier than the FP, so we ignore those. 773 // R7, LR 774 int64_t FPOffset = Offset - 8; 775 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 776 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 777 FPOffset -= 80; 778 // Estimate an offset from the stack pointer. 779 // The incoming offset is relating to the SP at the start of the function, 780 // but when we access the local it'll be relative to the SP after local 781 // allocation, so adjust our SP-relative offset by that allocation size. 782 Offset = -Offset; 783 Offset += MFI->getLocalFrameSize(); 784 // Assume that we'll have at least some spill slots allocated. 785 // FIXME: This is a total SWAG number. We should run some statistics 786 // and pick a real one. 787 Offset += 128; // 128 bytes of spill slots 788 789 // If there is a frame pointer, try using it. 790 // The FP is only available if there is no dynamic realignment. We 791 // don't know for sure yet whether we'll need that, so we guess based 792 // on whether there are any local variables that would trigger it. 793 unsigned StackAlign = TFI->getStackAlignment(); 794 if (TFI->hasFP(MF) && 795 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 796 if (isFrameOffsetLegal(MI, FPOffset)) 797 return false; 798 } 799 // If we can reference via the stack pointer, try that. 800 // FIXME: This (and the code that resolves the references) can be improved 801 // to only disallow SP relative references in the live range of 802 // the VLA(s). In practice, it's unclear how much difference that 803 // would make, but it may be worth doing. 804 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 805 return false; 806 807 // The offset likely isn't legal, we want to allocate a virtual base register. 808 return true; 809} 810 811/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 812/// be a pointer to FrameIdx at the beginning of the basic block. 813void ARMBaseRegisterInfo:: 814materializeFrameBaseRegister(MachineBasicBlock *MBB, 815 unsigned BaseReg, int FrameIdx, 816 int64_t Offset) const { 817 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 818 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 819 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 820 821 MachineBasicBlock::iterator Ins = MBB->begin(); 822 DebugLoc DL; // Defaults to "unknown" 823 if (Ins != MBB->end()) 824 DL = Ins->getDebugLoc(); 825 826 const MCInstrDesc &MCID = TII.get(ADDriOpc); 827 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 828 const MachineFunction &MF = *MBB->getParent(); 829 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 830 831 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 832 .addFrameIndex(FrameIdx).addImm(Offset)); 833 834 if (!AFI->isThumb1OnlyFunction()) 835 AddDefaultCC(MIB); 836} 837 838void 839ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 840 unsigned BaseReg, int64_t Offset) const { 841 MachineInstr &MI = *I; 842 MachineBasicBlock &MBB = *MI.getParent(); 843 MachineFunction &MF = *MBB.getParent(); 844 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 845 int Off = Offset; // ARM doesn't need the general 64-bit offsets 846 unsigned i = 0; 847 848 assert(!AFI->isThumb1OnlyFunction() && 849 "This resolveFrameIndex does not support Thumb1!"); 850 851 while (!MI.getOperand(i).isFI()) { 852 ++i; 853 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 854 } 855 bool Done = false; 856 if (!AFI->isThumbFunction()) 857 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 858 else { 859 assert(AFI->isThumb2Function()); 860 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 861 } 862 assert (Done && "Unable to resolve frame index!"); 863 (void)Done; 864} 865 866bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 867 int64_t Offset) const { 868 const MCInstrDesc &Desc = MI->getDesc(); 869 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 870 unsigned i = 0; 871 872 while (!MI->getOperand(i).isFI()) { 873 ++i; 874 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 875 } 876 877 // AddrMode4 and AddrMode6 cannot handle any offset. 878 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 879 return Offset == 0; 880 881 unsigned NumBits = 0; 882 unsigned Scale = 1; 883 bool isSigned = true; 884 switch (AddrMode) { 885 case ARMII::AddrModeT2_i8: 886 case ARMII::AddrModeT2_i12: 887 // i8 supports only negative, and i12 supports only positive, so 888 // based on Offset sign, consider the appropriate instruction 889 Scale = 1; 890 if (Offset < 0) { 891 NumBits = 8; 892 Offset = -Offset; 893 } else { 894 NumBits = 12; 895 } 896 break; 897 case ARMII::AddrMode5: 898 // VFP address mode. 899 NumBits = 8; 900 Scale = 4; 901 break; 902 case ARMII::AddrMode_i12: 903 case ARMII::AddrMode2: 904 NumBits = 12; 905 break; 906 case ARMII::AddrMode3: 907 NumBits = 8; 908 break; 909 case ARMII::AddrModeT1_s: 910 NumBits = 5; 911 Scale = 4; 912 isSigned = false; 913 break; 914 default: 915 llvm_unreachable("Unsupported addressing mode!"); 916 } 917 918 Offset += getFrameIndexInstrOffset(MI, i); 919 // Make sure the offset is encodable for instructions that scale the 920 // immediate. 921 if ((Offset & (Scale-1)) != 0) 922 return false; 923 924 if (isSigned && Offset < 0) 925 Offset = -Offset; 926 927 unsigned Mask = (1 << NumBits) - 1; 928 if ((unsigned)Offset <= Mask * Scale) 929 return true; 930 931 return false; 932} 933 934void 935ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 936 int SPAdj, RegScavenger *RS) const { 937 unsigned i = 0; 938 MachineInstr &MI = *II; 939 MachineBasicBlock &MBB = *MI.getParent(); 940 MachineFunction &MF = *MBB.getParent(); 941 const ARMFrameLowering *TFI = 942 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 943 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 944 assert(!AFI->isThumb1OnlyFunction() && 945 "This eliminateFrameIndex does not support Thumb1!"); 946 947 while (!MI.getOperand(i).isFI()) { 948 ++i; 949 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 950 } 951 952 int FrameIndex = MI.getOperand(i).getIndex(); 953 unsigned FrameReg; 954 955 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 956 957 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 958 // call frame setup/destroy instructions have already been eliminated. That 959 // means the stack pointer cannot be used to access the emergency spill slot 960 // when !hasReservedCallFrame(). 961#ifndef NDEBUG 962 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){ 963 assert(TFI->hasReservedCallFrame(MF) && 964 "Cannot use SP to access the emergency spill slot in " 965 "functions without a reserved call frame"); 966 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 967 "Cannot use SP to access the emergency spill slot in " 968 "functions with variable sized frame objects"); 969 } 970#endif // NDEBUG 971 972 // Special handling of dbg_value instructions. 973 if (MI.isDebugValue()) { 974 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 975 MI.getOperand(i+1).ChangeToImmediate(Offset); 976 return; 977 } 978 979 // Modify MI as necessary to handle as much of 'Offset' as possible 980 bool Done = false; 981 if (!AFI->isThumbFunction()) 982 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 983 else { 984 assert(AFI->isThumb2Function()); 985 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 986 } 987 if (Done) 988 return; 989 990 // If we get here, the immediate doesn't fit into the instruction. We folded 991 // as much as possible above, handle the rest, providing a register that is 992 // SP+LargeImm. 993 assert((Offset || 994 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 995 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 996 "This code isn't needed if offset already handled!"); 997 998 unsigned ScratchReg = 0; 999 int PIdx = MI.findFirstPredOperandIdx(); 1000 ARMCC::CondCodes Pred = (PIdx == -1) 1001 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1002 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1003 if (Offset == 0) 1004 // Must be addrmode4/6. 1005 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1006 else { 1007 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 1008 if (!AFI->isThumbFunction()) 1009 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1010 Offset, Pred, PredReg, TII); 1011 else { 1012 assert(AFI->isThumb2Function()); 1013 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1014 Offset, Pred, PredReg, TII); 1015 } 1016 // Update the original instruction to use the scratch register. 1017 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1018 } 1019} 1020