ARMBaseRegisterInfo.cpp revision f86e436fb95670ed110818fefa403f21ae104639
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/ADT/BitVector.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/RegisterScavenging.h" 29#include "llvm/CodeGen/VirtRegMap.h" 30#include "llvm/IR/Constants.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/Function.h" 33#include "llvm/IR/LLVMContext.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetFrameLowering.h" 38#include "llvm/Target/TargetMachine.h" 39#include "llvm/Target/TargetOptions.h" 40 41#define GET_REGINFO_TARGET_DESC 42#include "ARMGenRegisterInfo.inc" 43 44using namespace llvm; 45 46ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 47 const ARMSubtarget &sti) 48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti), 49 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 50 BasePtr(ARM::R6) { 51} 52 53const uint16_t* 54ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 55 bool ghcCall = false; 56 57 if (MF) { 58 const Function *F = MF->getFunction(); 59 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 60 } 61 62 if (ghcCall) { 63 return CSR_GHC_SaveList; 64 } 65 else { 66 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 67 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 68 } 69} 70 71const uint32_t* 72ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 73 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 74 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 75} 76 77const uint32_t* 78ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const { 79 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 80 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask; 81} 82 83const uint32_t* 84ARMBaseRegisterInfo::getNoPreservedMask() const { 85 return CSR_NoRegs_RegMask; 86} 87 88BitVector ARMBaseRegisterInfo:: 89getReservedRegs(const MachineFunction &MF) const { 90 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 91 92 // FIXME: avoid re-calculating this every time. 93 BitVector Reserved(getNumRegs()); 94 Reserved.set(ARM::SP); 95 Reserved.set(ARM::PC); 96 Reserved.set(ARM::FPSCR); 97 Reserved.set(ARM::APSR_NZCV); 98 if (TFI->hasFP(MF)) 99 Reserved.set(FramePtr); 100 if (hasBasePointer(MF)) 101 Reserved.set(BasePtr); 102 // Some targets reserve R9. 103 if (STI.isR9Reserved()) 104 Reserved.set(ARM::R9); 105 // Reserve D16-D31 if the subtarget doesn't support them. 106 if (!STI.hasVFP3() || STI.hasD16()) { 107 assert(ARM::D31 == ARM::D16 + 15); 108 for (unsigned i = 0; i != 16; ++i) 109 Reserved.set(ARM::D16 + i); 110 } 111 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 112 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 113 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 114 if (Reserved.test(*SI)) Reserved.set(*I); 115 116 return Reserved; 117} 118 119const TargetRegisterClass* 120ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 121 const { 122 const TargetRegisterClass *Super = RC; 123 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 124 do { 125 switch (Super->getID()) { 126 case ARM::GPRRegClassID: 127 case ARM::SPRRegClassID: 128 case ARM::DPRRegClassID: 129 case ARM::QPRRegClassID: 130 case ARM::QQPRRegClassID: 131 case ARM::QQQQPRRegClassID: 132 case ARM::GPRPairRegClassID: 133 return Super; 134 } 135 Super = *I++; 136 } while (Super); 137 return RC; 138} 139 140const TargetRegisterClass * 141ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 142 const { 143 return &ARM::GPRRegClass; 144} 145 146const TargetRegisterClass * 147ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 148 if (RC == &ARM::CCRRegClass) 149 return 0; // Can't copy CCR registers. 150 return RC; 151} 152 153unsigned 154ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 155 MachineFunction &MF) const { 156 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 157 158 switch (RC->getID()) { 159 default: 160 return 0; 161 case ARM::tGPRRegClassID: 162 return TFI->hasFP(MF) ? 4 : 5; 163 case ARM::GPRRegClassID: { 164 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 165 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 166 } 167 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 168 case ARM::DPRRegClassID: 169 return 32 - 10; 170 } 171} 172 173// Get the other register in a GPRPair. 174static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 175 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 176 if (ARM::GPRPairRegClass.contains(*Supers)) 177 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 178 return 0; 179} 180 181// Resolve the RegPairEven / RegPairOdd register allocator hints. 182void 183ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 184 ArrayRef<MCPhysReg> Order, 185 SmallVectorImpl<MCPhysReg> &Hints, 186 const MachineFunction &MF, 187 const VirtRegMap *VRM) const { 188 const MachineRegisterInfo &MRI = MF.getRegInfo(); 189 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 190 191 unsigned Odd; 192 switch (Hint.first) { 193 case ARMRI::RegPairEven: 194 Odd = 0; 195 break; 196 case ARMRI::RegPairOdd: 197 Odd = 1; 198 break; 199 default: 200 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 201 return; 202 } 203 204 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 205 // Check if the other part of the pair has already been assigned, and provide 206 // the paired register as the first hint. 207 unsigned PairedPhys = 0; 208 if (VRM && VRM->hasPhys(Hint.second)) { 209 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 210 if (PairedPhys && MRI.isReserved(PairedPhys)) 211 PairedPhys = 0; 212 } 213 214 // First prefer the paired physreg. 215 if (PairedPhys && 216 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 217 Hints.push_back(PairedPhys); 218 219 // Then prefer even or odd registers. 220 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 221 unsigned Reg = Order[I]; 222 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 223 continue; 224 // Don't provide hints that are paired to a reserved register. 225 unsigned Paired = getPairedGPR(Reg, !Odd, this); 226 if (!Paired || MRI.isReserved(Paired)) 227 continue; 228 Hints.push_back(Reg); 229 } 230} 231 232void 233ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 234 MachineFunction &MF) const { 235 MachineRegisterInfo *MRI = &MF.getRegInfo(); 236 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 237 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 238 Hint.first == (unsigned)ARMRI::RegPairEven) && 239 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 240 // If 'Reg' is one of the even / odd register pair and it's now changed 241 // (e.g. coalesced) into a different register. The other register of the 242 // pair allocation hint must be updated to reflect the relationship 243 // change. 244 unsigned OtherReg = Hint.second; 245 Hint = MRI->getRegAllocationHint(OtherReg); 246 if (Hint.second == Reg) 247 // Make sure the pair has not already divorced. 248 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 249 } 250} 251 252bool 253ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 254 // CortexA9 has a Write-after-write hazard for NEON registers. 255 if (!STI.isLikeA9()) 256 return false; 257 258 switch (RC->getID()) { 259 case ARM::DPRRegClassID: 260 case ARM::DPR_8RegClassID: 261 case ARM::DPR_VFP2RegClassID: 262 case ARM::QPRRegClassID: 263 case ARM::QPR_8RegClassID: 264 case ARM::QPR_VFP2RegClassID: 265 case ARM::SPRRegClassID: 266 case ARM::SPR_8RegClassID: 267 // Avoid reusing S, D, and Q registers. 268 // Don't increase register pressure for QQ and QQQQ. 269 return true; 270 default: 271 return false; 272 } 273} 274 275bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 276 const MachineFrameInfo *MFI = MF.getFrameInfo(); 277 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 278 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 279 280 // When outgoing call frames are so large that we adjust the stack pointer 281 // around the call, we can no longer use the stack pointer to reach the 282 // emergency spill slot. 283 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 284 return true; 285 286 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 287 // negative range for ldr/str (255), and thumb1 is positive offsets only. 288 // It's going to be better to use the SP or Base Pointer instead. When there 289 // are variable sized objects, we can't reference off of the SP, so we 290 // reserve a Base Pointer. 291 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 292 // Conservatively estimate whether the negative offset from the frame 293 // pointer will be sufficient to reach. If a function has a smallish 294 // frame, it's less likely to have lots of spills and callee saved 295 // space, so it's all more likely to be within range of the frame pointer. 296 // If it's wrong, the scavenger will still enable access to work, it just 297 // won't be optimal. 298 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 299 return false; 300 return true; 301 } 302 303 return false; 304} 305 306bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 307 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 308 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 309 // We can't realign the stack if: 310 // 1. Dynamic stack realignment is explicitly disabled, 311 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 312 // 3. There are VLAs in the function and the base pointer is disabled. 313 if (!MF.getTarget().Options.RealignStack) 314 return false; 315 if (AFI->isThumb1OnlyFunction()) 316 return false; 317 // Stack realignment requires a frame pointer. If we already started 318 // register allocation with frame pointer elimination, it is too late now. 319 if (!MRI->canReserveReg(FramePtr)) 320 return false; 321 // We may also need a base pointer if there are dynamic allocas or stack 322 // pointer adjustments around calls. 323 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 324 return true; 325 // A base pointer is required and allowed. Check that it isn't too late to 326 // reserve it. 327 return MRI->canReserveReg(BasePtr); 328} 329 330bool ARMBaseRegisterInfo:: 331needsStackRealignment(const MachineFunction &MF) const { 332 const MachineFrameInfo *MFI = MF.getFrameInfo(); 333 const Function *F = MF.getFunction(); 334 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 335 bool requiresRealignment = 336 ((MFI->getMaxAlignment() > StackAlign) || 337 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 338 Attribute::StackAlignment)); 339 340 return requiresRealignment && canRealignStack(MF); 341} 342 343bool ARMBaseRegisterInfo:: 344cannotEliminateFrame(const MachineFunction &MF) const { 345 const MachineFrameInfo *MFI = MF.getFrameInfo(); 346 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 347 return true; 348 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 349 || needsStackRealignment(MF); 350} 351 352unsigned 353ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 354 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 355 356 if (TFI->hasFP(MF)) 357 return FramePtr; 358 return ARM::SP; 359} 360 361unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 362 llvm_unreachable("What is the exception register"); 363} 364 365unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 366 llvm_unreachable("What is the exception handler register"); 367} 368 369/// emitLoadConstPool - Emits a load from constpool to materialize the 370/// specified immediate. 371void ARMBaseRegisterInfo:: 372emitLoadConstPool(MachineBasicBlock &MBB, 373 MachineBasicBlock::iterator &MBBI, 374 DebugLoc dl, 375 unsigned DestReg, unsigned SubIdx, int Val, 376 ARMCC::CondCodes Pred, 377 unsigned PredReg, unsigned MIFlags) const { 378 MachineFunction &MF = *MBB.getParent(); 379 MachineConstantPool *ConstantPool = MF.getConstantPool(); 380 const Constant *C = 381 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 382 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 383 384 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 385 .addReg(DestReg, getDefRegState(true), SubIdx) 386 .addConstantPoolIndex(Idx) 387 .addImm(0).addImm(Pred).addReg(PredReg) 388 .setMIFlags(MIFlags); 389} 390 391bool ARMBaseRegisterInfo:: 392requiresRegisterScavenging(const MachineFunction &MF) const { 393 return true; 394} 395 396bool ARMBaseRegisterInfo:: 397trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 398 return true; 399} 400 401bool ARMBaseRegisterInfo:: 402requiresFrameIndexScavenging(const MachineFunction &MF) const { 403 return true; 404} 405 406bool ARMBaseRegisterInfo:: 407requiresVirtualBaseRegisters(const MachineFunction &MF) const { 408 return true; 409} 410 411int64_t ARMBaseRegisterInfo:: 412getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 413 const MCInstrDesc &Desc = MI->getDesc(); 414 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 415 int64_t InstrOffs = 0; 416 int Scale = 1; 417 unsigned ImmIdx = 0; 418 switch (AddrMode) { 419 case ARMII::AddrModeT2_i8: 420 case ARMII::AddrModeT2_i12: 421 case ARMII::AddrMode_i12: 422 InstrOffs = MI->getOperand(Idx+1).getImm(); 423 Scale = 1; 424 break; 425 case ARMII::AddrMode5: { 426 // VFP address mode. 427 const MachineOperand &OffOp = MI->getOperand(Idx+1); 428 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 429 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 430 InstrOffs = -InstrOffs; 431 Scale = 4; 432 break; 433 } 434 case ARMII::AddrMode2: { 435 ImmIdx = Idx+2; 436 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 437 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 438 InstrOffs = -InstrOffs; 439 break; 440 } 441 case ARMII::AddrMode3: { 442 ImmIdx = Idx+2; 443 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 444 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 445 InstrOffs = -InstrOffs; 446 break; 447 } 448 case ARMII::AddrModeT1_s: { 449 ImmIdx = Idx+1; 450 InstrOffs = MI->getOperand(ImmIdx).getImm(); 451 Scale = 4; 452 break; 453 } 454 default: 455 llvm_unreachable("Unsupported addressing mode!"); 456 } 457 458 return InstrOffs * Scale; 459} 460 461/// needsFrameBaseReg - Returns true if the instruction's frame index 462/// reference would be better served by a base register other than FP 463/// or SP. Used by LocalStackFrameAllocation to determine which frame index 464/// references it should create new base registers for. 465bool ARMBaseRegisterInfo:: 466needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 467 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 468 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 469 } 470 471 // It's the load/store FI references that cause issues, as it can be difficult 472 // to materialize the offset if it won't fit in the literal field. Estimate 473 // based on the size of the local frame and some conservative assumptions 474 // about the rest of the stack frame (note, this is pre-regalloc, so 475 // we don't know everything for certain yet) whether this offset is likely 476 // to be out of range of the immediate. Return true if so. 477 478 // We only generate virtual base registers for loads and stores, so 479 // return false for everything else. 480 unsigned Opc = MI->getOpcode(); 481 switch (Opc) { 482 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 483 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 484 case ARM::t2LDRi12: case ARM::t2LDRi8: 485 case ARM::t2STRi12: case ARM::t2STRi8: 486 case ARM::VLDRS: case ARM::VLDRD: 487 case ARM::VSTRS: case ARM::VSTRD: 488 case ARM::tSTRspi: case ARM::tLDRspi: 489 break; 490 default: 491 return false; 492 } 493 494 // Without a virtual base register, if the function has variable sized 495 // objects, all fixed-size local references will be via the frame pointer, 496 // Approximate the offset and see if it's legal for the instruction. 497 // Note that the incoming offset is based on the SP value at function entry, 498 // so it'll be negative. 499 MachineFunction &MF = *MI->getParent()->getParent(); 500 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 501 MachineFrameInfo *MFI = MF.getFrameInfo(); 502 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 503 504 // Estimate an offset from the frame pointer. 505 // Conservatively assume all callee-saved registers get pushed. R4-R6 506 // will be earlier than the FP, so we ignore those. 507 // R7, LR 508 int64_t FPOffset = Offset - 8; 509 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 510 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 511 FPOffset -= 80; 512 // Estimate an offset from the stack pointer. 513 // The incoming offset is relating to the SP at the start of the function, 514 // but when we access the local it'll be relative to the SP after local 515 // allocation, so adjust our SP-relative offset by that allocation size. 516 Offset = -Offset; 517 Offset += MFI->getLocalFrameSize(); 518 // Assume that we'll have at least some spill slots allocated. 519 // FIXME: This is a total SWAG number. We should run some statistics 520 // and pick a real one. 521 Offset += 128; // 128 bytes of spill slots 522 523 // If there is a frame pointer, try using it. 524 // The FP is only available if there is no dynamic realignment. We 525 // don't know for sure yet whether we'll need that, so we guess based 526 // on whether there are any local variables that would trigger it. 527 unsigned StackAlign = TFI->getStackAlignment(); 528 if (TFI->hasFP(MF) && 529 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 530 if (isFrameOffsetLegal(MI, FPOffset)) 531 return false; 532 } 533 // If we can reference via the stack pointer, try that. 534 // FIXME: This (and the code that resolves the references) can be improved 535 // to only disallow SP relative references in the live range of 536 // the VLA(s). In practice, it's unclear how much difference that 537 // would make, but it may be worth doing. 538 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 539 return false; 540 541 // The offset likely isn't legal, we want to allocate a virtual base register. 542 return true; 543} 544 545/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 546/// be a pointer to FrameIdx at the beginning of the basic block. 547void ARMBaseRegisterInfo:: 548materializeFrameBaseRegister(MachineBasicBlock *MBB, 549 unsigned BaseReg, int FrameIdx, 550 int64_t Offset) const { 551 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 552 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 553 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 554 555 MachineBasicBlock::iterator Ins = MBB->begin(); 556 DebugLoc DL; // Defaults to "unknown" 557 if (Ins != MBB->end()) 558 DL = Ins->getDebugLoc(); 559 560 const MCInstrDesc &MCID = TII.get(ADDriOpc); 561 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 562 const MachineFunction &MF = *MBB->getParent(); 563 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 564 565 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 566 .addFrameIndex(FrameIdx).addImm(Offset)); 567 568 if (!AFI->isThumb1OnlyFunction()) 569 AddDefaultCC(MIB); 570} 571 572void 573ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 574 unsigned BaseReg, int64_t Offset) const { 575 MachineInstr &MI = *I; 576 MachineBasicBlock &MBB = *MI.getParent(); 577 MachineFunction &MF = *MBB.getParent(); 578 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 579 int Off = Offset; // ARM doesn't need the general 64-bit offsets 580 unsigned i = 0; 581 582 assert(!AFI->isThumb1OnlyFunction() && 583 "This resolveFrameIndex does not support Thumb1!"); 584 585 while (!MI.getOperand(i).isFI()) { 586 ++i; 587 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 588 } 589 bool Done = false; 590 if (!AFI->isThumbFunction()) 591 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 592 else { 593 assert(AFI->isThumb2Function()); 594 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 595 } 596 assert (Done && "Unable to resolve frame index!"); 597 (void)Done; 598} 599 600bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 601 int64_t Offset) const { 602 const MCInstrDesc &Desc = MI->getDesc(); 603 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 604 unsigned i = 0; 605 606 while (!MI->getOperand(i).isFI()) { 607 ++i; 608 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 609 } 610 611 // AddrMode4 and AddrMode6 cannot handle any offset. 612 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 613 return Offset == 0; 614 615 unsigned NumBits = 0; 616 unsigned Scale = 1; 617 bool isSigned = true; 618 switch (AddrMode) { 619 case ARMII::AddrModeT2_i8: 620 case ARMII::AddrModeT2_i12: 621 // i8 supports only negative, and i12 supports only positive, so 622 // based on Offset sign, consider the appropriate instruction 623 Scale = 1; 624 if (Offset < 0) { 625 NumBits = 8; 626 Offset = -Offset; 627 } else { 628 NumBits = 12; 629 } 630 break; 631 case ARMII::AddrMode5: 632 // VFP address mode. 633 NumBits = 8; 634 Scale = 4; 635 break; 636 case ARMII::AddrMode_i12: 637 case ARMII::AddrMode2: 638 NumBits = 12; 639 break; 640 case ARMII::AddrMode3: 641 NumBits = 8; 642 break; 643 case ARMII::AddrModeT1_s: 644 NumBits = 5; 645 Scale = 4; 646 isSigned = false; 647 break; 648 default: 649 llvm_unreachable("Unsupported addressing mode!"); 650 } 651 652 Offset += getFrameIndexInstrOffset(MI, i); 653 // Make sure the offset is encodable for instructions that scale the 654 // immediate. 655 if ((Offset & (Scale-1)) != 0) 656 return false; 657 658 if (isSigned && Offset < 0) 659 Offset = -Offset; 660 661 unsigned Mask = (1 << NumBits) - 1; 662 if ((unsigned)Offset <= Mask * Scale) 663 return true; 664 665 return false; 666} 667 668void 669ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 670 int SPAdj, unsigned FIOperandNum, 671 RegScavenger *RS) const { 672 MachineInstr &MI = *II; 673 MachineBasicBlock &MBB = *MI.getParent(); 674 MachineFunction &MF = *MBB.getParent(); 675 const ARMFrameLowering *TFI = 676 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 677 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 678 assert(!AFI->isThumb1OnlyFunction() && 679 "This eliminateFrameIndex does not support Thumb1!"); 680 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 681 unsigned FrameReg; 682 683 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 684 685 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 686 // call frame setup/destroy instructions have already been eliminated. That 687 // means the stack pointer cannot be used to access the emergency spill slot 688 // when !hasReservedCallFrame(). 689#ifndef NDEBUG 690 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 691 assert(TFI->hasReservedCallFrame(MF) && 692 "Cannot use SP to access the emergency spill slot in " 693 "functions without a reserved call frame"); 694 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 695 "Cannot use SP to access the emergency spill slot in " 696 "functions with variable sized frame objects"); 697 } 698#endif // NDEBUG 699 700 // Special handling of dbg_value instructions. 701 if (MI.isDebugValue()) { 702 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/); 703 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 704 return; 705 } 706 707 // Modify MI as necessary to handle as much of 'Offset' as possible 708 bool Done = false; 709 if (!AFI->isThumbFunction()) 710 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 711 else { 712 assert(AFI->isThumb2Function()); 713 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 714 } 715 if (Done) 716 return; 717 718 // If we get here, the immediate doesn't fit into the instruction. We folded 719 // as much as possible above, handle the rest, providing a register that is 720 // SP+LargeImm. 721 assert((Offset || 722 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 723 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 724 "This code isn't needed if offset already handled!"); 725 726 unsigned ScratchReg = 0; 727 int PIdx = MI.findFirstPredOperandIdx(); 728 ARMCC::CondCodes Pred = (PIdx == -1) 729 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 730 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 731 if (Offset == 0) 732 // Must be addrmode4/6. 733 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 734 else { 735 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 736 if (!AFI->isThumbFunction()) 737 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 738 Offset, Pred, PredReg, TII); 739 else { 740 assert(AFI->isThumb2Function()); 741 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 742 Offset, Pred, PredReg, TII); 743 } 744 // Update the original instruction to use the scratch register. 745 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 746 } 747} 748