131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 3b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// The LLVM Compiler Infrastructure 4b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 5b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// This file is distributed under the University of Illinois Open Source 6b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// License. See LICENSE.TXT for details. 7b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 8b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 9b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 10656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// This file contains a pass that expands pseudo instructions into target 11b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// instructions to allow proper scheduling, if-conversion, and other late 12b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// optimizations. This pass should be run after register allocation but before 13656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// the post-regalloc scheduling pass. 14b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 15b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 16b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 17b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARM.h" 18b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARMBaseInstrInfo.h" 19e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMBaseRegisterInfo.h" 2036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "ARMConstantPoolValue.h" 21e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMMachineFunctionInfo.h" 22ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 23e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/CodeGen/MachineFrameInfo.h" 24b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineFunctionPass.h" 25b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 26ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines#include "llvm/CodeGen/MachineInstrBundle.h" 2736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "llvm/IR/GlobalValue.h" 28e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen#include "llvm/Support/CommandLine.h" 29e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 30d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetFrameLowering.h" 31d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetRegisterInfo.h" 32b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengusing namespace llvm; 33b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 34dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "arm-pseudo" 35dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 36a67f14bf53737f9bb0afefa28e08c4aac6ec4804Benjamin Kramerstatic cl::opt<bool> 37e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund OlesenVerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 38e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen cl::desc("Verify machine code after expanding ARM pseudos")); 39e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen 40b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengnamespace { 41b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng class ARMExpandPseudo : public MachineFunctionPass { 42b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng public: 43b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng static char ID; 4490c579de5a383cee278acc3f7e7b9d0a656e6a35Owen Anderson ARMExpandPseudo() : MachineFunctionPass(ID) {} 45b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 46e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *TII; 47d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng const TargetRegisterInfo *TRI; 48893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng const ARMSubtarget *STI; 499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ARMFunctionInfo *AFI; 50b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 5136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool runOnMachineFunction(MachineFunction &Fn) override; 52b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 5336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const char *getPassName() const override { 54b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return "ARM pseudo instruction expansion pass"; 55b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 56b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 57b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng private: 58431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng void TransferImpOps(MachineInstr &OldMI, 59431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool ExpandMI(MachineBasicBlock &MBB, 619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI); 62b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool ExpandMBB(MachineBasicBlock &MBB); 638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVLD(MachineBasicBlock::iterator &MBBI); 648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVST(MachineBasicBlock::iterator &MBBI); 658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 66bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 6760d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach unsigned Opc, bool IsExt); 689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng void ExpandMOV32BitImm(MachineBasicBlock &MBB, 699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI); 70b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng }; 71b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng char ARMExpandPseudo::ID = 0; 72b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 73b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 74431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// TransferImpOps - Transfer implicit operands on the pseudo instruction to 75431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// the instructions created from the expansion. 76431300797b84600fc9b4eb8ca283277d3e0674ebEvan Chengvoid ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 77431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, 78431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &DefMI) { 79e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = OldMI.getDesc(); 80431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 81431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng i != e; ++i) { 82431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const MachineOperand &MO = OldMI.getOperand(i); 83431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng assert(MO.isReg() && MO.getReg()); 84431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isUse()) 8563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson UseMI.addOperand(MO); 86431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng else 8763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson DefMI.addOperand(MO); 88431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } 89431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng} 90431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonnamespace { 928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Constants for register spacing in NEON load/store instructions. 938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // For quad-register load-lane and store-lane pseudo instructors, the 948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // spacing is initially assumed to be EvenDblSpc, and that is changed to 958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // OddDblSpc depending on the lane number operand. 968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson enum NEONRegSpacing { 978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson SingleSpc, 988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson EvenDblSpc, 998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson OddDblSpc 1008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Entries for NEON load/store information table. The table is sorted by 1038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // PseudoOpc for fast binary-search lookups. 1048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson struct NEONLdStTableEntry { 105b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper uint16_t PseudoOpc; 106b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper uint16_t RealOpc; 1078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool IsLoad; 108f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach bool isUpdating; 109f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach bool hasWritebackOperand; 110aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper uint8_t RegSpacing; // One of type NEONRegSpacing 111aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper uint8_t NumRegs; // D registers loaded or stored 112aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper uint8_t RegElts; // elements per D register; used for lane ops 113280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // FIXME: Temporary flag to denote whether the real instruction takes 114280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // a single register (like the encoding) or all of the registers in 115280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // the list (like the asm syntax and the isel DAG). When all definitions 116280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // are converted to take only the single encoded register, this will 117280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // go away. 118280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach bool copyAllListRegs; 1198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Comparison methods for binary search of the table. 1218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool operator<(const NEONLdStTableEntry &TE) const { 1228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 1258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return TE.PseudoOpc < PseudoOpc; 1268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 127100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 128100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth const NEONLdStTableEntry &TE) { 1298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 1338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry NEONLdStTable[] = { 135f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 136f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 137f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 138f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 139f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 140f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 141f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 142f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 14336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 144f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 14536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 146f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 147f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 148f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 149f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 150f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 151f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 152f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 153f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 154f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 155f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 156f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 157f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 158f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 159a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 160a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 161f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 162a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 163a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 164f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 165a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 166a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 167f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 168f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 169f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 170f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 171f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 172f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 173f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 174f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 175f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 176f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 177f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 178f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 179f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 180f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 181f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 182f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 183f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 184f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 185f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 186f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 187f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 188f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 189f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 190f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 191f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 192f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 193f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 194f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 195f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 196f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 197f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 198f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 199f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 200f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 201f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 202f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 203f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 204f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 205f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 206f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 207f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 208f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 209f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 210f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 211f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 212f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 213f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 214f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 215f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 216f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 217f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 218f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 219f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 220f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 221f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 222f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 223f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 224f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 225f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 226f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 227f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 228f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 229f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 230f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 231f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 232f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 233f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 234f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 235f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 236f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 237f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 238f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 239f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 240f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 241f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 242f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 243f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 244f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 2454c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 2464c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 2474c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 248d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 249d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 250d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 251f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 252f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 253f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 254f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 255f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 256f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 257f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 258f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 259f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 260f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 261f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 262f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 263e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 264bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 265bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 266e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 267bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 268bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 269e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 270bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 271bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 272f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 273f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 274f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 275f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 276f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 277f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 278f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 279f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 280f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 281f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 282f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 283f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 284f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 285f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 286f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 287f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 288f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 289f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 290f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 291f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 292f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 293f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 294f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 295f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 296f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 297f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 298f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 299f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 300f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 301f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 302f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 303f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 304f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 305f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 306f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 307f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 308f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 309f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 310f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 311f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 312f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 313f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 314f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 315f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 316f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 317f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 318f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 319f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 320f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 321f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 322f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 323f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 324f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 325f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 326f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 327f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 3288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson}; 3298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 3318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// load or store pseudo instruction. 3328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 3338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#ifndef NDEBUG 3348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Make sure the table is sorted. 3358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson static bool TableChecked = false; 3368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableChecked) { 337cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) && 338cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar "NEONLdStTable is not sorted!"); 3398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TableChecked = true; 3408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 3418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#endif 3428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 343cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar auto I = std::lower_bound(std::begin(NEONLdStTable), 344cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar std::end(NEONLdStTable), Opcode); 345cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode) 3468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return I; 347dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 3488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 3518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// corresponding to the specified register spacing. Not all of the results 3528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// are necessarily valid, e.g., a Q register only has 2 D subregisters. 3538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 3548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const TargetRegisterInfo *TRI, unsigned &D0, 3558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned &D1, unsigned &D2, unsigned &D3) { 3568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == SingleSpc) { 3578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_1); 3598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_2); 3608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_3); 3618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else if (RegSpc == EvenDblSpc) { 3628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_2); 3648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_4); 3658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_6); 3668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else { 3678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc == OddDblSpc && "unknown register spacing"); 3688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_1); 3698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_3); 3708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_5); 3718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_7); 372bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson } 3738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 37582a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 37682a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// operands to real VLD instructions with D register operands. 3778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 378ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineInstr &MI = *MBBI; 379ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 380ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 3818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 3828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 383aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 3848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 3858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 3878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 388ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned OpIdx = 0; 389ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 390ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 391ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 392ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned D0, D1, D2, D3; 3938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 394280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 395280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 1 && TableEntry->copyAllListRegs) 396280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 397280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 2 && TableEntry->copyAllListRegs) 398f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 399280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 3 && TableEntry->copyAllListRegs) 400f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 401ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 402f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 40363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 405ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson // Copy the addrmode6 operands. 40663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40863569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 409f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 41063569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 411ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 41219d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // For an instruction writing double-spaced subregs, the pseudo instruction 413823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // has an extra operand that is a use of the super-register. Record the 414823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // operand index and skip over it. 415823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcOpIdx = 0; 416823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 417823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson SrcOpIdx = OpIdx++; 418823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 419823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 420823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 421823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 422823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 423823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the super-register source operand used for double-spaced subregs over 42419d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // to the new instruction as an implicit operand. 425823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (SrcOpIdx != 0) { 426823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MachineOperand MO = MI.getOperand(SrcOpIdx); 42719d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MO.setImplicit(true); 42819d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MIB.addOperand(MO); 42919d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson } 430f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson // Add an implicit def for the super-register. 431f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 43219d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson TransferImpOps(MI, MIB, MIB); 433b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 434b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 435d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 436b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 437ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MI.eraseFromParent(); 438ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson} 439ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 44001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 44101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// operands to real VST instructions with D register operands. 4428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 443709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineInstr &MI = *MBBI; 444709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 445709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 448aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 4498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 4528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 453709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned OpIdx = 0; 454f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 45563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 45663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 457709d59255a3100c7d440c93069efa1f726677a27Bob Wilson // Copy the addrmode6 operands. 45863569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 45963569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 46063569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 461f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 46263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 463709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 464709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 465d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 466823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 467709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned D0, D1, D2, D3; 4688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 469d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 4704334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 1 && TableEntry->copyAllListRegs) 471d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 4724334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 2 && TableEntry->copyAllListRegs) 473d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 4744334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 3 && TableEntry->copyAllListRegs) 475d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 476823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 477823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 478823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 479823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 480823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 481d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 482d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 48336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines else if (!SrcIsUndef) 48436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 485bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 486b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 487b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 488d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 489b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 490709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MI.eraseFromParent(); 491709d59255a3100c7d440c93069efa1f726677a27Bob Wilson} 492709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 4948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// register operands to real instructions with D register operands. 4958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 4968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstr &MI = *MBBI; 4978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 4988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 5008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && "NEONLdStTable lookup failed"); 501aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 5028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 5038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RegElts = TableEntry->RegElts; 5048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 5068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 5078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned OpIdx = 0; 5088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // The lane operand is always the 3rd from last operand, before the 2 5098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // predicate operands. 5108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 5118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Adjust the lane and spacing as needed for Q registers. 5138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 5148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == EvenDblSpc && Lane >= RegElts) { 5158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson RegSpc = OddDblSpc; 5168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson Lane -= RegElts; 5178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 5198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 520584520e8e2c1f8cc04bc8dd4dc4ea6c390627317Ted Kremenek unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 521fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned DstReg = 0; 522fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson bool DstIsDead = false; 5238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) { 5248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstIsDead = MI.getOperand(OpIdx).isDead(); 5258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstReg = MI.getOperand(OpIdx++).getReg(); 5268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 527b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 528b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 529b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 5308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 5328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 5348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 536f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 5378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the addrmode6 operands. 5408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the am6offset operand. 543f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 5448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Grab the super-register source. 5478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineOperand MO = MI.getOperand(OpIdx++); 5488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableEntry->IsLoad) 5498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 5508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the subregs as sources of the new instruction. 5528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 5538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson getKillRegState(MO.isKill())); 554b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, SrcFlags); 555b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 556b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, SrcFlags); 5578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, SrcFlags); 5598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, SrcFlags); 5618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the lane number operand. 5638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addImm(Lane); 564823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson OpIdx += 1; 565823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 566823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 567823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 568823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the super-register source to be an implicit source. 5718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MO.setImplicit(true); 5728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MO); 5738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) 5748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add an implicit def for the super-register. 5758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 5768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TransferImpOps(MI, MIB, MIB); 5772027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen // Transfer memoperands. 5782027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 5798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MI.eraseFromParent(); 5808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 5818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 582bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 583bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// register operands to real instructions with D register operands. 584bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilsonvoid ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 58560d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach unsigned Opc, bool IsExt) { 586bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstr &MI = *MBBI; 587bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 588bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 589bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 590bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned OpIdx = 0; 591bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 592bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Transfer the destination register operand. 593bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 594bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (IsExt) 595bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 596bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 597bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 598bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 599bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned D0, D1, D2, D3; 600bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 60160d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach MIB.addReg(D0); 602bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 603bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Copy the other source register operand. 604823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 605823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 606823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 607823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 608823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 609bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 61036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // Add an implicit kill and use for the super-reg. 61136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 612bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 613bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MI.eraseFromParent(); 614bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson} 615bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 616dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesstatic bool IsAnAddressOperand(const MachineOperand &MO) { 617dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // This check is overly conservative. Unless we are certain that the machine 618dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // operand is not a symbol reference, we return that it is a symbol reference. 619dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // This is important as the load pair may not be split up Windows. 620dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines switch (MO.getType()) { 621dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Register: 622dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Immediate: 623dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_CImmediate: 624dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_FPImmediate: 625dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 626dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_MachineBasicBlock: 627dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 628dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_FrameIndex: 629dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 630dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_ConstantPoolIndex: 631dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_TargetIndex: 632dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_JumpTableIndex: 633dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_ExternalSymbol: 634dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_GlobalAddress: 635dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_BlockAddress: 636dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 637dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_RegisterMask: 638dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_RegisterLiveOut: 639dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 640dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Metadata: 641dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_MCSymbol: 642dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 643dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_CFIIndex: 644dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 645dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 646dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_unreachable("unhandled machine operand type"); 647dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 648dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 6499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengvoid ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 6509fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI) { 6519fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 6529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 6539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PredReg = 0; 654c89c744b69cecac576317a98322fd295e36e9886Craig Topper ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); 6559fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 6569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 6579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 6589fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 659dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 6609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder LO16, HI16; 6619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!STI->hasV6T2Ops() && 6639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 664dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // FIXME Windows CE supports older ARM CPUs 665dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 666dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 6679fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Expand into a movi + orr. 6689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 6699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 6709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 6719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 6729fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6739fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 6749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned ImmVal = (unsigned)MO.getImm(); 6759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 6769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 6779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(SOImmValV1); 6789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(SOImmValV2); 679d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 680d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 6819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg).addReg(0); 6829fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg).addReg(0); 6839fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 6849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 6859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return; 6869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 687b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 6889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LO16Opc = 0; 6899fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned HI16Opc = 0; 6909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 6919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::t2MOVi16; 6929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::t2MOVTi16; 6939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else { 6949fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::MOVi16; 6959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::MOVTi16; 6969fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 697b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 6989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 6999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 7009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 7019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 7029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 703dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines switch (MO.getType()) { 704dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Immediate: { 7059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Imm = MO.getImm(); 7069fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Lo16 = Imm & 0xffff; 7079fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Hi16 = (Imm >> 16) & 0xffff; 7089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(Lo16); 7099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(Hi16); 710dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 711dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 712dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_ExternalSymbol: { 713dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const char *ES = MO.getSymbolName(); 714dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned TF = MO.getTargetFlags(); 715dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 716dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 717dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 718dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 719dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines default: { 7209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO.getGlobal(); 7219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO.getTargetFlags(); 7229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 7239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 724dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 725dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 7269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 727709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 728d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 729d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 7309fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg); 7319fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg); 7329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 733dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (RequiresBundling) 734cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator()); 735dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 7369fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 7379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 7389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 7399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 7409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 7419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI) { 7429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 7439fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 7449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng switch (Opcode) { 7459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng default: 7469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 747cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 748cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case ARM::TCRETURNdi: 749cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case ARM::TCRETURNri: { 750cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 751cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(MBBI->isReturn() && 752cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar "Can only insert epilog into returning blocks"); 753cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned RetOpcode = MBBI->getOpcode(); 754cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DebugLoc dl = MBBI->getDebugLoc(); 755cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>( 756cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MBB.getParent()->getSubtarget().getInstrInfo()); 757cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 758cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Tail call return: adjust the stack pointer and jump to callee. 759cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MBBI = MBB.getLastNonDebugInstr(); 760cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineOperand &JumpTarget = MBBI->getOperand(0); 761cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 762cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Jump to label or value in register. 763cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (RetOpcode == ARM::TCRETURNdi) { 764cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned TCOpcode = 765cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar STI->isThumb() 766cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) 767cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar : ARM::TAILJMPd; 768cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 769cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (JumpTarget.isGlobal()) 770cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 771cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar JumpTarget.getTargetFlags()); 772cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar else { 773cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(JumpTarget.isSymbol()); 774cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MIB.addExternalSymbol(JumpTarget.getSymbolName(), 775cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar JumpTarget.getTargetFlags()); 776cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 777cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 778cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Add the default predicate in Thumb mode. 779cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (STI->isThumb()) 780cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MIB.addImm(ARMCC::AL).addReg(0); 781cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } else if (RetOpcode == ARM::TCRETURNri) { 782cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar BuildMI(MBB, MBBI, dl, 783cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)) 784cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar .addReg(JumpTarget.getReg(), RegState::Kill); 785cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 786cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 787cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstr *NewMI = std::prev(MBBI); 788cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 789cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar NewMI->addOperand(MBBI->getOperand(i)); 790cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 791cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Delete the pseudo instruction TCRETURN. 792cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MBB.erase(MBBI); 793cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MBBI = NewMI; 794cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return true; 795cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 796f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVScc: 797f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVDcc: { 798f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; 799f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 800f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.getOperand(1).getReg()) 801e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 802f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 803e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)); 804f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach 805f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.eraseFromParent(); 806f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach return true; 807f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach } 808efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach case ARM::t2MOVCCr: 809d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach case ARM::MOVCCr: { 810efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 811efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 812d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.getOperand(1).getReg()) 813e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 814d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 815e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)) 816d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 817d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 818d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 819d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 820d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 821152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM::MOVCCsi: { 822152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 823152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson (MI.getOperand(1).getReg())) 824e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 825152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addImm(MI.getOperand(3).getImm()) 826152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addImm(MI.getOperand(4).getImm()) // 'pred' 827e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(5)) 828152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addReg(0); // 's' bit 829152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 830152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson MI.eraseFromParent(); 831152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return true; 832152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson } 83392a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson case ARM::MOVCCsr: { 834152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 835d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach (MI.getOperand(1).getReg())) 836e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 837e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(3)) 838d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(4).getImm()) 839d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(5).getImm()) // 'pred' 840e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(6)) 841d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 8423906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach 8433906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 8443906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 8453906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 846f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCi16: 8473906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi16: { 848f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 849f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 8503906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 8513906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 8523906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 853e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)); 8543906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 8553906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 8563906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 857efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach case ARM::t2MOVCCi: 8583906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi: { 859efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 860efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 8613906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 8623906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 8633906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 864e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)) 8653906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(0); // 's' bit 866e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach 867e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.eraseFromParent(); 868e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach return true; 869e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach } 870f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MVNCCi: 871e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach case ARM::MVNCCi: { 872f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 873f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 874e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.getOperand(1).getReg()) 875e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(2).getImm()) 876e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 877e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)) 878e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addReg(0); // 's' bit 879d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 880d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 881d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 882d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 883f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsl: 884f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsr: 885f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCasr: 886f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCror: { 887f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover unsigned NewOpc; 888f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover switch (Opcode) { 889f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 890f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 891f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 892f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 893f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover default: llvm_unreachable("unexpeced conditional move"); 894f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover } 895f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 896f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover MI.getOperand(1).getReg()) 897e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 898f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover .addImm(MI.getOperand(3).getImm()) 899f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover .addImm(MI.getOperand(4).getImm()) // 'pred' 900e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(5)) 901f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover .addReg(0); // 's' bit 902f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover MI.eraseFromParent(); 903f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover return true; 904f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover } 905e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier case ARM::Int_eh_sjlj_dispatchsetup: { 906e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MachineFunction &MF = *MI.getParent()->getParent(); 907e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *AII = 908e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach static_cast<const ARMBaseInstrInfo*>(TII); 909e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 910e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // For functions using a base pointer, we rematerialize it (via the frame 911e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 912e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // for us. Otherwise, expand to nothing. 913e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (RI.hasBasePointer(MF)) { 914e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int32_t NumBytes = AFI->getFramePtrSpillOffset(); 915e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned FramePtr = RI.getFrameRegister(MF); 91637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) && 9177920d96964d707a3af85332c98d95b2fabc3d5c9Benjamin Kramer "base pointer without frame pointer?"); 918e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 919e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (AFI->isThumb2Function()) { 920c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 921c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 922e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else if (AFI->isThumbFunction()) { 923c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 924c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, *TII, RI); 925e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else { 926c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 927c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, ARMCC::AL, 0, 928c89c744b69cecac576317a98322fd295e36e9886Craig Topper *TII); 929e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 9308b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // If there's dynamic realignment, adjust for it. 931b8e67fc92b0a508e3782b782baa98a6d56d5d7eaJim Grosbach if (RI.needsStackRealignment(MF)) { 9328b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 9338b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 9348b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 9358b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // Emit bic r6, r6, MaxAlign 936ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines assert(MaxAlign <= 256 && "The BIC instruction cannot encode " 937ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines "immediates larger than 256 with all lower " 938ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines "bits set."); 9398b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned bicOpc = AFI->isThumbFunction() ? 9408b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach ARM::t2BICri : ARM::BICri; 9418b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 9428b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach TII->get(bicOpc), ARM::R6) 9438b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addReg(ARM::R6, RegState::Kill) 9448b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addImm(MaxAlign-1))); 9458b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach } 946e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 947e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 948e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MI.eraseFromParent(); 9499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 950e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 951e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 9527032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsrl_flag: 9537032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsra_flag: { 9543f4f420ab7acb10221ba971543a7eed5489fb626Robert Wilhelm // These are just fancy MOVs instructions. 955152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 956dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands MI.getOperand(0).getReg()) 9579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 958aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? 959aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach ARM_AM::lsr : ARM_AM::asr), 960aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach 1))) 9619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(ARM::CPSR, RegState::Define); 9627032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 9639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9647032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 9657032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::RRX: { 9667032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // This encodes as "MOVs Rd, Rm, rrx 9677032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MachineInstrBuilder MIB = 9688e0c7697fd9b9354856074efc06eea9f6d80015cJim Grosbach AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi), 9697032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.getOperand(0).getReg()) 9709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 9719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 9727032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addReg(0); 9737032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach TransferImpOps(MI, MIB, MIB); 9747032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 9759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9767032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 977ff97eb0cf4394090570feaa327d1237ba4b935e2Jim Grosbach case ARM::tTPsoft: 978a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim case ARM::TPsoft: { 979c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines MachineInstrBuilder MIB; 980c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (Opcode == ARM::tTPsoft) 981c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 982c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines TII->get( ARM::tBL)) 983c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines .addImm((unsigned)ARMCC::AL).addReg(0) 984c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines .addExternalSymbol("__aeabi_read_tp", 0); 985c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines else 986c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 987c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines TII->get( ARM::BL)) 988c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines .addExternalSymbol("__aeabi_read_tp", 0); 989a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim 990d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 991a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim TransferImpOps(MI, MIB, MIB); 992a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim MI.eraseFromParent(); 9939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9942fe813af23e682b418ecd477144fe070be325419Bill Wendling } 995bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::tLDRpci_pic: 996b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng case ARM::t2LDRpci_pic: { 997b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 998971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson ? ARM::tLDRpci : ARM::t2LDRpci; 999b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 1000431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 1001431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB1 = 1002971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 1003971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson TII->get(NewLdOpc), DstReg) 1004971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson .addOperand(MI.getOperand(1))); 1005d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 1006431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 1007431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TII->get(ARM::tPICADD)) 100801b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 1009431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg) 1010431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addOperand(MI.getOperand(2)); 1011431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, MIB1, MIB2); 1012b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 10139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1014b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 1015431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 101636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::LDRLIT_ga_abs: 101736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::LDRLIT_ga_pcrel: 101836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::LDRLIT_ga_pcrel_ldr: 101936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::tLDRLIT_ga_abs: 102036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::tLDRLIT_ga_pcrel: { 102136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned DstReg = MI.getOperand(0).getReg(); 102236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool DstIsDead = MI.getOperand(0).isDead(); 102336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MachineOperand &MO1 = MI.getOperand(1); 102436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const GlobalValue *GV = MO1.getGlobal(); 102536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool IsARM = 102636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; 102736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool IsPIC = 102836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 102936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 103036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned PICAddOpc = 103136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines IsARM 1032ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 103336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines : ARM::tPICADD; 103436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 103536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // We need a new const-pool entry to load from. 103636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 103736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned ARMPCLabelIndex = 0; 103836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineConstantPoolValue *CPV; 103936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 104036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsPIC) { 104136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned PCAdj = IsARM ? 8 : 4; 104236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines ARMPCLabelIndex = AFI->createPICLabelUId(); 104336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, 104436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines ARMCP::CPValue, PCAdj); 104536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } else 104636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 104736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 104836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstrBuilder MIB = 104936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 105036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); 105136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsARM) 105236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MIB.addImm(0); 105336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AddDefaultPred(MIB); 105436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 105536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsPIC) { 105636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstrBuilder MIB = 105736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 105836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 105936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addReg(DstReg) 106036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addImm(ARMPCLabelIndex); 106136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 106236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsARM) 106336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AddDefaultPred(MIB); 106436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 106536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 106636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MI.eraseFromParent(); 106736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return true; 106836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 106953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel: 107053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel_ldr: 107153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOV_ga_pcrel: { 107253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 10739fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LabelId = AFI->createPICLabelUId(); 1074b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 1075431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 10769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI.getOperand(1); 10779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO1.getGlobal(); 10789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO1.getTargetFlags(); 107936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 108053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 1081aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 108236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned LO16TF = TF | ARMII::MO_LO16; 108336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned HI16TF = TF | ARMII::MO_HI16; 10849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PICAddOpc = isARM 108553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 10869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng : ARM::tPICADD; 10879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 10889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(LO16Opc), DstReg) 108953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 10909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 109136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 109236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 10939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg) 109453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 10959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 109653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng 109753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 10989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(PICAddOpc)) 109901b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 11009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg).addImm(LabelId); 11019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (isARM) { 110253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng AddDefaultPred(MIB3); 110353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_pcrel_ldr) 11046e6269a976baee45717265dbd12996367df6a201Jakob Stoklund Olesen MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 11055de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng } 110653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TransferImpOps(MI, MIB1, MIB3); 1107b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 11089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1109d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng } 1110d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng 11119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVi32imm: 11129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVCCi32imm: 11139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVi32imm: 11149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVCCi32imm: 11159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ExpandMOV32BitImm(MBB, MBBI); 11169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 11179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1118bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover case ARM::SUBS_PC_LR: { 1119bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover MachineInstrBuilder MIB = 1120bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 1121bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addReg(ARM::LR) 1122bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addOperand(MI.getOperand(0)) 1123bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addOperand(MI.getOperand(1)) 1124bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addOperand(MI.getOperand(2)) 1125bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addReg(ARM::CPSR, RegState::Undef); 1126bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover TransferImpOps(MI, MIB, MIB); 1127bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover MI.eraseFromParent(); 1128bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return true; 1129bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } 1130848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VLDMQIA: { 1131848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VLDMDIA; 11329d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 113373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 11349d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 113573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11369d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register destination. 11379d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 11389d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 113973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 114073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the source register. 11419d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 114273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11439d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 11449d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 11459d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 114673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11479d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the destination operands (D subregs). 11489d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 11499d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 11509d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 11519d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 115273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11539d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add an implicit def for the super-register. 11549d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 11559d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 11562027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 11579d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 11589fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 11599d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 11609d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 1161848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VSTMQIA: { 1162848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VSTMDIA; 11639d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 116473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 11659d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 116673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11679d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register source. 11689d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 11699d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 117073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 117173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the destination register. 11729d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 117373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11749d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 11759d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 11769d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 117773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11789d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the source operands (D subregs). 11799d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 11809d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 1181ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0) 1182ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addReg(D1, SrcIsKill ? RegState::Kill : 0); 118373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1184d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner if (SrcIsKill) // Add an implicit kill for the Q register. 1185d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 118673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11879d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 11882027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 11899d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 11909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 11919d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 11929d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 1193ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo: 1194ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo: 1195ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo: 1196a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 1197a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 1198a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 1199a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 1200a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 1201a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 1202f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo: 1203f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo: 1204f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo: 1205ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo: 120636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64TPseudoWB_fixed: 1207f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo_UPD: 1208f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo_UPD: 1209f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo_UPD: 1210f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8Pseudo_UPD: 1211f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16Pseudo_UPD: 1212f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32Pseudo_UPD: 12137de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q8oddPseudo: 12147de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q16oddPseudo: 12157de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q32oddPseudo: 1216f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8oddPseudo_UPD: 1217f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16oddPseudo_UPD: 1218f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32oddPseudo_UPD: 1219f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo: 1220f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo: 1221f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo: 1222ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo: 122336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64QPseudoWB_fixed: 1224f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo_UPD: 1225f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo_UPD: 1226f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo_UPD: 1227f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8Pseudo_UPD: 1228f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16Pseudo_UPD: 1229f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32Pseudo_UPD: 12307de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q8oddPseudo: 12317de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q16oddPseudo: 12327de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q32oddPseudo: 1233f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8oddPseudo_UPD: 1234f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16oddPseudo_UPD: 1235f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32oddPseudo_UPD: 123686c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo: 123786c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo: 123886c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo: 123986c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo_UPD: 124086c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo_UPD: 124186c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo_UPD: 12426c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo: 12436c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo: 12446c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo: 12456c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo_UPD: 12466c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo_UPD: 12476c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo_UPD: 12488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVLD(MBBI); 12499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1250ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 1251e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo: 1252e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo: 1253e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo: 1254bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q8PseudoWB_fixed: 1255bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q16PseudoWB_fixed: 1256bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q32PseudoWB_fixed: 1257bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q8PseudoWB_register: 1258bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q16PseudoWB_register: 1259bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q32PseudoWB_register: 126001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo: 126101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo: 126201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo: 126301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo: 126401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo_UPD: 126501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo_UPD: 126601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo_UPD: 1267d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach case ARM::VST1d64TPseudoWB_fixed: 1268d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach case ARM::VST1d64TPseudoWB_register: 126901ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8Pseudo_UPD: 127001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16Pseudo_UPD: 127101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32Pseudo_UPD: 12727de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q8oddPseudo: 12737de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q16oddPseudo: 12747de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q32oddPseudo: 127501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8oddPseudo_UPD: 127601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16oddPseudo_UPD: 127701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32oddPseudo_UPD: 1278709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo: 1279709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo: 1280709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo: 128170e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo: 1282709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo_UPD: 1283709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo_UPD: 1284709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo_UPD: 12854c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach case ARM::VST1d64QPseudoWB_fixed: 12864c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach case ARM::VST1d64QPseudoWB_register: 1287709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8Pseudo_UPD: 1288709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16Pseudo_UPD: 1289709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32Pseudo_UPD: 12907de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q8oddPseudo: 12917de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q16oddPseudo: 12927de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q32oddPseudo: 1293709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8oddPseudo_UPD: 1294709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16oddPseudo_UPD: 1295709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32oddPseudo_UPD: 12968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVST(MBBI); 12979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 12988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1299b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo: 1300b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo: 1301b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo: 1302b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo_UPD: 1303b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo_UPD: 1304b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo_UPD: 13058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo: 13068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo: 13078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo: 13088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo: 13098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo: 13108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo_UPD: 13118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo_UPD: 13128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo_UPD: 13138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo_UPD: 13148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo_UPD: 13158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo: 13168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo: 13178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo: 13188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo: 13198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo: 13208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo_UPD: 13218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo_UPD: 13228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo_UPD: 13238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo_UPD: 13248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo_UPD: 13258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo: 13268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo: 13278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo: 13288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo: 13298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo: 13308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo_UPD: 13318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo_UPD: 13328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo_UPD: 13338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo_UPD: 13348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo_UPD: 1335d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo: 1336d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo: 1337d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo: 1338d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo_UPD: 1339d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo_UPD: 1340d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo_UPD: 13418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo: 13428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo: 13438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo: 13448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo: 13458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo: 13468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo_UPD: 13478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo_UPD: 13488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo_UPD: 13498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo_UPD: 13508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo_UPD: 13518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo: 13528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo: 13538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo: 13548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo: 13558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo: 13568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo_UPD: 13578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo_UPD: 13588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo_UPD: 13598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo_UPD: 13608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo_UPD: 13618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo: 13628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo: 13638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo: 13648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo: 13658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo: 13668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo_UPD: 13678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo_UPD: 13688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo_UPD: 13698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo_UPD: 13708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo_UPD: 13718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandLaneOp(MBBI); 13729fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 13739fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 137460d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 137560d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 137660d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 137760d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 13789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 13799fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 1380709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 13819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 13829fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool Modified = false; 13839fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 13859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng while (MBBI != E) { 138636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::iterator NMBBI = std::next(MBBI); 13879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Modified |= ExpandMI(MBB, MBBI); 1388b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MBBI = NMBBI; 1389b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 1390b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1391b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1392b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1393b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1394b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 1395ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget()); 1396ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines TII = STI->getInstrInfo(); 1397ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines TRI = STI->getRegisterInfo(); 13989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng AFI = MF.getInfo<ARMFunctionInfo>(); 1399b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1400b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 1401b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1402b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng ++MFI) 1403b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng Modified |= ExpandMBB(*MFI); 1404e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen if (VerifyARMPseudo) 1405e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen MF.verify(this, "After expanding ARM pseudo instructions."); 1406b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1407b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1408b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1409b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1410b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// expansion pass. 1411b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan ChengFunctionPass *llvm::createARMExpandPseudoPass() { 1412b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return new ARMExpandPseudo(); 1413b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1414