ARMExpandPseudoInsts.cpp revision 16c29b5f285f375be53dabaa73e3e91107485fe4
1b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=// 2b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 3b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// The LLVM Compiler Infrastructure 4b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 5b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// This file is distributed under the University of Illinois Open Source 6b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// License. See LICENSE.TXT for details. 7b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 8b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 9b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 10656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// This file contains a pass that expands pseudo instructions into target 11b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// instructions to allow proper scheduling, if-conversion, and other late 12b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// optimizations. This pass should be run after register allocation but before 13656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// the post-regalloc scheduling pass. 14b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 15b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 16b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 17b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#define DEBUG_TYPE "arm-pseudo" 18b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARM.h" 197032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach#include "ARMAddressingModes.h" 20b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARMBaseInstrInfo.h" 21e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMBaseRegisterInfo.h" 22e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMMachineFunctionInfo.h" 2365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach#include "ARMRegisterInfo.h" 24e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/CodeGen/MachineFrameInfo.h" 25b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineFunctionPass.h" 26b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 2716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 284dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "llvm/Target/TargetRegisterInfo.h" 29e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 30b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengusing namespace llvm; 31b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 32b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengnamespace { 33b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng class ARMExpandPseudo : public MachineFunctionPass { 34b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng public: 35b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng static char ID; 3690c579de5a383cee278acc3f7e7b9d0a656e6a35Owen Anderson ARMExpandPseudo() : MachineFunctionPass(ID) {} 37b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 38e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *TII; 39d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng const TargetRegisterInfo *TRI; 40893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng const ARMSubtarget *STI; 41b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 42b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual bool runOnMachineFunction(MachineFunction &Fn); 43b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 44b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual const char *getPassName() const { 45b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return "ARM pseudo instruction expansion pass"; 46b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 47b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 48b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng private: 49431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng void TransferImpOps(MachineInstr &OldMI, 50431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 51b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool ExpandMBB(MachineBasicBlock &MBB); 528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVLD(MachineBasicBlock::iterator &MBBI); 538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVST(MachineBasicBlock::iterator &MBBI); 548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 55bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 56bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned Opc, bool IsExt, unsigned NumRegs); 57b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng }; 58b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng char ARMExpandPseudo::ID = 0; 59b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 60b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 61431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// TransferImpOps - Transfer implicit operands on the pseudo instruction to 62431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// the instructions created from the expansion. 63431300797b84600fc9b4eb8ca283277d3e0674ebEvan Chengvoid ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 64431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, 65431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &DefMI) { 66431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const TargetInstrDesc &Desc = OldMI.getDesc(); 67431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 68431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng i != e; ++i) { 69431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const MachineOperand &MO = OldMI.getOperand(i); 70431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng assert(MO.isReg() && MO.getReg()); 71431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isUse()) 7263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson UseMI.addOperand(MO); 73431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng else 7463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson DefMI.addOperand(MO); 75431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } 76431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng} 77431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonnamespace { 798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Constants for register spacing in NEON load/store instructions. 808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // For quad-register load-lane and store-lane pseudo instructors, the 818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // spacing is initially assumed to be EvenDblSpc, and that is changed to 828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // OddDblSpc depending on the lane number operand. 838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson enum NEONRegSpacing { 848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson SingleSpc, 858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson EvenDblSpc, 868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson OddDblSpc 878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Entries for NEON load/store information table. The table is sorted by 908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // PseudoOpc for fast binary-search lookups. 918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson struct NEONLdStTableEntry { 928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned PseudoOpc; 938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RealOpc; 948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool IsLoad; 958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool HasWriteBack; 968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpacing; 978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char NumRegs; // D registers loaded or stored 988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char RegElts; // elements per D register; used for lane ops 998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Comparison methods for binary search of the table. 1018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool operator<(const NEONLdStTableEntry &TE) const { 1028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 1058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return TE.PseudoOpc < PseudoOpc; 1068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 107100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 108100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth const NEONLdStTableEntry &TE) { 1098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 1138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry NEONLdStTable[] = { 1152a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4}, 1162a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4}, 1172a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2}, 1182a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2}, 1192a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8}, 1202a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8}, 1212a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson 122b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 }, 123d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 }, 124b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 }, 125d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 }, 126b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 }, 127d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 }, 128b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson 1298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, 1308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, 1318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 }, 1328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 }, 1338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 }, 1358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 }, 1368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 }, 1378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 }, 1388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 }, 1398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 }, 1408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 }, 1418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 }, 1428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 143b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4}, 144b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4}, 145b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2}, 146b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2}, 147b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8}, 148b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8}, 149b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson 1508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 }, 1518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 }, 1528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 }, 1538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 }, 1548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 }, 1558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 }, 1568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 }, 1578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 }, 1588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 }, 1598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 }, 1608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 }, 1628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 }, 1638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 }, 1648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 }, 1658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 }, 1668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 }, 1678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 }, 1698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 }, 1708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 }, 1718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 }, 1728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 }, 1738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 }, 1748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 17586c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4}, 17686c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4}, 17786c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2}, 17886c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2}, 17986c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8}, 18086c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8}, 18186c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson 1828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 }, 1838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 }, 1848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 }, 1858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 }, 1868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 }, 1878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 }, 1888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 }, 1898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 }, 1908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 }, 1918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 }, 1928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 }, 1948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 }, 1958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 }, 1968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 }, 1978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 }, 1988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 }, 1998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 }, 2018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 }, 2028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 }, 2038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 }, 2048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 }, 2058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 }, 2068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2076c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4}, 2086c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4}, 2096c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2}, 2106c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2}, 2116c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8}, 2126c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8}, 2136c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson 2148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 }, 2158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 }, 2168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 }, 2178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 }, 2188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 }, 2198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 }, 2208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 }, 2218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 }, 2228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 }, 2238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 }, 2248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 }, 2268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 }, 2278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 }, 2288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 }, 2298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 }, 2308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 }, 2318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 }, 2338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 }, 2348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 }, 2358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 }, 2368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 }, 2378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 }, 2388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 239d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 }, 240d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 }, 241d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 }, 242d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 }, 243d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 }, 244d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 }, 245d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson 2468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 }, 2478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 }, 2488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 }, 2498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 }, 2508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 }, 2528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 }, 2538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 }, 2548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 }, 2558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 }, 2568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 }, 2578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 }, 2588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 }, 2598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 }, 2618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 }, 2628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 }, 2638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 }, 2648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 }, 2658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 }, 2668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4}, 2678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4}, 2688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2}, 2698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2}, 2708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 }, 2728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 }, 2738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 }, 2748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 }, 2758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 }, 2768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 }, 2778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 }, 2798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 }, 2808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 }, 2818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 }, 2828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 }, 2838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 }, 2848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 }, 2868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 }, 2878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 }, 2888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 }, 2898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 }, 2908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 }, 2918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4}, 2928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4}, 2938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2}, 2948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2}, 2958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 }, 2978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 }, 2988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 }, 2998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 }, 3008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 }, 3018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 }, 3028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 }, 3048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 }, 3058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 }, 3068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 }, 3078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 }, 3088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 }, 3098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 }, 3118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 }, 3128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 }, 3138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 }, 3148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 }, 3158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 }, 3168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4}, 3178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4}, 3188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2}, 3198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2}, 3208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 }, 3228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 }, 3238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 }, 3248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 }, 3258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 }, 3268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 }, 3278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 }, 3298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 }, 3308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 }, 3318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 }, 3328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 }, 3338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 } 3348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson}; 3358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 3378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// load or store pseudo instruction. 3388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 3398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumEntries = array_lengthof(NEONLdStTable); 3408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#ifndef NDEBUG 3428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Make sure the table is sorted. 3438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson static bool TableChecked = false; 3448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableChecked) { 3458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson for (unsigned i = 0; i != NumEntries-1; ++i) 3468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(NEONLdStTable[i] < NEONLdStTable[i+1] && 3478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson "NEONLdStTable is not sorted!"); 3488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TableChecked = true; 3498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 3508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#endif 3518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *I = 3538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); 3548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) 3558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return I; 3568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return NULL; 3578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 3608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// corresponding to the specified register spacing. Not all of the results 3618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// are necessarily valid, e.g., a Q register only has 2 D subregisters. 3628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 3638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const TargetRegisterInfo *TRI, unsigned &D0, 3648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned &D1, unsigned &D2, unsigned &D3) { 3658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == SingleSpc) { 3668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_1); 3688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_2); 3698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_3); 3708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else if (RegSpc == EvenDblSpc) { 3718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_2); 3738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_4); 3748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_6); 3758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else { 3768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc == OddDblSpc && "unknown register spacing"); 3778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_1); 3788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_3); 3798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_5); 3808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_7); 381bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson } 3828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 38482a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 38582a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// operands to real VLD instructions with D register operands. 3868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 387ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineInstr &MI = *MBBI; 388ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 389ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 3908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 3918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 3928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 3938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 3948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 3968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 397ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned OpIdx = 0; 398ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 399ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 400ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 401ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned D0, D1, D2, D3; 4028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 403f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 404f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 405ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson if (NumRegs > 2) 406f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 407ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson if (NumRegs > 3) 408f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 409ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 4108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 41163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 41263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 413ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson // Copy the addrmode6 operands. 41463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 41563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 41663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 4178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 41863569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 419ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 42019d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // For an instruction writing double-spaced subregs, the pseudo instruction 421823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // has an extra operand that is a use of the super-register. Record the 422823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // operand index and skip over it. 423823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcOpIdx = 0; 424823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 425823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson SrcOpIdx = OpIdx++; 426823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 427823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 428823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 429823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 430823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 431823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the super-register source operand used for double-spaced subregs over 43219d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // to the new instruction as an implicit operand. 433823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (SrcOpIdx != 0) { 434823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MachineOperand MO = MI.getOperand(SrcOpIdx); 43519d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MO.setImplicit(true); 43619d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MIB.addOperand(MO); 43719d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson } 438f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson // Add an implicit def for the super-register. 439f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 44019d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson TransferImpOps(MI, MIB, MIB); 441ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MI.eraseFromParent(); 442ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson} 443ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 44401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 44501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// operands to real VST instructions with D register operands. 4468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 447709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineInstr &MI = *MBBI; 448709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 449709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 4528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 4538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 4568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 457709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned OpIdx = 0; 4588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 45963569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 46063569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 461709d59255a3100c7d440c93069efa1f726677a27Bob Wilson // Copy the addrmode6 operands. 46263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 46363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 46463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 4658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 46663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 467709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 468709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 469823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 470709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned D0, D1, D2, D3; 4718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 4727e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D0).addReg(D1); 473e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson if (NumRegs > 2) 4747e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D2); 47501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson if (NumRegs > 3) 4767e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D3); 477823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 478823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 479823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 480823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 481823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 4827e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson if (SrcIsKill) 4837e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson // Add an implicit kill for the super-reg. 4847e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson (*MIB).addRegisterKilled(SrcReg, TRI, true); 485bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 486709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MI.eraseFromParent(); 487709d59255a3100c7d440c93069efa1f726677a27Bob Wilson} 488709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 4908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// register operands to real instructions with D register operands. 4918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 4928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstr &MI = *MBBI; 4938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 4948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && "NEONLdStTable lookup failed"); 4978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 4988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RegElts = TableEntry->RegElts; 5008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 5028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 5038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned OpIdx = 0; 5048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // The lane operand is always the 3rd from last operand, before the 2 5058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // predicate operands. 5068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 5078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Adjust the lane and spacing as needed for Q registers. 5098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 5108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == EvenDblSpc && Lane >= RegElts) { 5118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson RegSpc = OddDblSpc; 5128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson Lane -= RegElts; 5138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 5158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 516fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned D0, D1, D2, D3; 517fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned DstReg = 0; 518fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson bool DstIsDead = false; 5198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) { 5208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstIsDead = MI.getOperand(OpIdx).isDead(); 5218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstReg = MI.getOperand(OpIdx++).getReg(); 5228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 523b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 524b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 525b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 5268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 5288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 5308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 5338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the addrmode6 operands. 5368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the am6offset operand. 5398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 5408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Grab the super-register source. 5438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineOperand MO = MI.getOperand(OpIdx++); 5448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableEntry->IsLoad) 5458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 5468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the subregs as sources of the new instruction. 5488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 5498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson getKillRegState(MO.isKill())); 550b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, SrcFlags); 551b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 552b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, SrcFlags); 5538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, SrcFlags); 5558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, SrcFlags); 5578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the lane number operand. 5598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addImm(Lane); 560823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson OpIdx += 1; 561823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 562823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 563823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 564823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the super-register source to be an implicit source. 5678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MO.setImplicit(true); 5688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MO); 5698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) 5708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add an implicit def for the super-register. 5718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 5728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TransferImpOps(MI, MIB, MIB); 5738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MI.eraseFromParent(); 5748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 5758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 576bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 577bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// register operands to real instructions with D register operands. 578bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilsonvoid ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 579bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned Opc, bool IsExt, unsigned NumRegs) { 580bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstr &MI = *MBBI; 581bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 582bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 583bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 584bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned OpIdx = 0; 585bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 586bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Transfer the destination register operand. 587bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 588bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (IsExt) 589bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 590bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 591bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 592bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 593bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned D0, D1, D2, D3; 594bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 595bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D0).addReg(D1); 596bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (NumRegs > 2) 597bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D2); 598bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (NumRegs > 3) 599bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D3); 600bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 601bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Copy the other source register operand. 602823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 603823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 604823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 605823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 606823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 607bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 608bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (SrcIsKill) 609bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Add an implicit kill for the super-reg. 610bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson (*MIB).addRegisterKilled(SrcReg, TRI, true); 611bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 612bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MI.eraseFromParent(); 613bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson} 614bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 615b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 616b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 617b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 618b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 619b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng while (MBBI != E) { 620b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MachineInstr &MI = *MBBI; 6217896c9f436a4eda5ec15e882a7505ba482a2fcd0Chris Lattner MachineBasicBlock::iterator NMBBI = llvm::next(MBBI); 622b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 623709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool ModifiedOp = true; 624b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned Opcode = MI.getOpcode(); 625b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng switch (Opcode) { 626709d59255a3100c7d440c93069efa1f726677a27Bob Wilson default: 627709d59255a3100c7d440c93069efa1f726677a27Bob Wilson ModifiedOp = false; 628709d59255a3100c7d440c93069efa1f726677a27Bob Wilson break; 629709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 630e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach case ARM::Int_eh_sjlj_dispatchsetup: { 631e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MachineFunction &MF = *MI.getParent()->getParent(); 632e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *AII = 633e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach static_cast<const ARMBaseInstrInfo*>(TII); 634e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 635e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // For functions using a base pointer, we rematerialize it (via the frame 636e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 637e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // for us. Otherwise, expand to nothing. 638e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (RI.hasBasePointer(MF)) { 639e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 640e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int32_t NumBytes = AFI->getFramePtrSpillOffset(); 641e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned FramePtr = RI.getFrameRegister(MF); 64216c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 6437920d96964d707a3af85332c98d95b2fabc3d5c9Benjamin Kramer "base pointer without frame pointer?"); 644e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 645e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (AFI->isThumb2Function()) { 646e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 647e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 648e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else if (AFI->isThumbFunction()) { 649e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach llvm::emitThumbRegPlusImmediate(MBB, MBBI, ARM::R6, 650e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach FramePtr, -NumBytes, 651e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach *TII, RI, MI.getDebugLoc()); 652e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else { 653e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 654e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach FramePtr, -NumBytes, ARMCC::AL, 0, 655e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach *TII); 656e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 6578b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // If there's dynamic realignment, adjust for it. 658b8e67fc92b0a508e3782b782baa98a6d56d5d7eaJim Grosbach if (RI.needsStackRealignment(MF)) { 6598b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 6608b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 6618b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 6628b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // Emit bic r6, r6, MaxAlign 6638b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned bicOpc = AFI->isThumbFunction() ? 6648b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach ARM::t2BICri : ARM::BICri; 6658b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 6668b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach TII->get(bicOpc), ARM::R6) 6678b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addReg(ARM::R6, RegState::Kill) 6688b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addImm(MaxAlign-1))); 6698b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach } 670e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 671e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 672e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MI.eraseFromParent(); 673e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach break; 674e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 675e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 6767032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsrl_flag: 6777032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsra_flag: { 6787032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // These are just fancy MOVs insructions. 679dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 680dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands MI.getOperand(0).getReg()) 681dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands .addOperand(MI.getOperand(1)) 682dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands .addReg(0) 683dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr 684dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands : ARM_AM::asr), 1))) 685dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands .addReg(ARM::CPSR, RegState::Define); 6867032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 6877032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach break; 6887032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 6897032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::RRX: { 6907032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // This encodes as "MOVs Rd, Rm, rrx 6917032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MachineInstrBuilder MIB = 6927032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 6937032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.getOperand(0).getReg()) 6947032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addOperand(MI.getOperand(1)) 6957032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addOperand(MI.getOperand(1)) 6967032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 6977032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addReg(0); 6987032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach TransferImpOps(MI, MIB, MIB); 6997032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 7007032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach break; 7017032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 702a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim case ARM::TPsoft: { 703a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim MachineInstrBuilder MIB = 704a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim BuildMI(MBB, MBBI, MI.getDebugLoc(), 705a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim TII->get(ARM::BL)) 706a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim .addExternalSymbol("__aeabi_read_tp", 0); 707a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim 708a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 709a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim TransferImpOps(MI, MIB, MIB); 710a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim MI.eraseFromParent(); 711045869c12ac5af2b1dd97a0dcbedab8db01fe765Jason W Kim break; 7122fe813af23e682b418ecd477144fe070be325419Bill Wendling } 713eb6779c5b98383e33542207f062102e79263df16Owen Anderson case ARM::t2LDRHpci: 714eb6779c5b98383e33542207f062102e79263df16Owen Anderson case ARM::t2LDRBpci: 715eb6779c5b98383e33542207f062102e79263df16Owen Anderson case ARM::t2LDRSHpci: 716eb6779c5b98383e33542207f062102e79263df16Owen Anderson case ARM::t2LDRSBpci: 717eb6779c5b98383e33542207f062102e79263df16Owen Anderson case ARM::t2LDRpci: { 718eb6779c5b98383e33542207f062102e79263df16Owen Anderson unsigned NewLdOpc; 719eb6779c5b98383e33542207f062102e79263df16Owen Anderson if (Opcode == ARM::t2LDRpci) 720eb6779c5b98383e33542207f062102e79263df16Owen Anderson NewLdOpc = ARM::t2LDRi12; 721eb6779c5b98383e33542207f062102e79263df16Owen Anderson else if (Opcode == ARM::t2LDRHpci) 722eb6779c5b98383e33542207f062102e79263df16Owen Anderson NewLdOpc = ARM::t2LDRHi12; 723eb6779c5b98383e33542207f062102e79263df16Owen Anderson else if (Opcode == ARM::t2LDRBpci) 724eb6779c5b98383e33542207f062102e79263df16Owen Anderson NewLdOpc = ARM::t2LDRBi12; 725eb6779c5b98383e33542207f062102e79263df16Owen Anderson else if (Opcode == ARM::t2LDRSHpci) 726eb6779c5b98383e33542207f062102e79263df16Owen Anderson NewLdOpc = ARM::t2LDRSHi12; 727eb6779c5b98383e33542207f062102e79263df16Owen Anderson else if (Opcode == ARM::t2LDRSBpci) 728eb6779c5b98383e33542207f062102e79263df16Owen Anderson NewLdOpc = ARM::t2LDRSBi12; 729eb6779c5b98383e33542207f062102e79263df16Owen Anderson else 730eb6779c5b98383e33542207f062102e79263df16Owen Anderson llvm_unreachable("Not a known opcode?"); 731eb6779c5b98383e33542207f062102e79263df16Owen Anderson 732eb6779c5b98383e33542207f062102e79263df16Owen Anderson unsigned DstReg = MI.getOperand(0).getReg(); 733eb6779c5b98383e33542207f062102e79263df16Owen Anderson MachineInstrBuilder MIB = 734eb6779c5b98383e33542207f062102e79263df16Owen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 735eb6779c5b98383e33542207f062102e79263df16Owen Anderson TII->get(NewLdOpc), DstReg) 736eb6779c5b98383e33542207f062102e79263df16Owen Anderson .addReg(ARM::PC) 737eb6779c5b98383e33542207f062102e79263df16Owen Anderson .addOperand(MI.getOperand(1))); 738eb6779c5b98383e33542207f062102e79263df16Owen Anderson (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 739eb6779c5b98383e33542207f062102e79263df16Owen Anderson TransferImpOps(MI, MIB, MIB); 740eb6779c5b98383e33542207f062102e79263df16Owen Anderson MI.eraseFromParent(); 741eb6779c5b98383e33542207f062102e79263df16Owen Anderson break; 742eb6779c5b98383e33542207f062102e79263df16Owen Anderson } 743bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::tLDRpci_pic: 744b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng case ARM::t2LDRpci_pic: { 745b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 746eb6779c5b98383e33542207f062102e79263df16Owen Anderson ? ARM::tLDRpci : ARM::t2LDRi12; 747b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 748431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 749431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB1 = 750eb6779c5b98383e33542207f062102e79263df16Owen Anderson BuildMI(MBB, MBBI, MI.getDebugLoc(), 751eb6779c5b98383e33542207f062102e79263df16Owen Anderson TII->get(NewLdOpc), DstReg); 752eb6779c5b98383e33542207f062102e79263df16Owen Anderson if (Opcode == ARM::t2LDRpci_pic) MIB1.addReg(ARM::PC); 753eb6779c5b98383e33542207f062102e79263df16Owen Anderson MIB1.addOperand(MI.getOperand(1)); 754eb6779c5b98383e33542207f062102e79263df16Owen Anderson AddDefaultPred(MIB1); 755431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 756431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 757431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TII->get(ARM::tPICADD)) 75801b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 759431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg) 760431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addOperand(MI.getOperand(2)); 761431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, MIB1, MIB2); 762b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 763b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng break; 764b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 765431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 7666d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov case ARM::MOVi32imm: 76763f3544a7f6ca09e7515d6b0e1bf9e8e884131e2Evan Cheng case ARM::MOVCCi32imm: 76863f3544a7f6ca09e7515d6b0e1bf9e8e884131e2Evan Cheng case ARM::t2MOVi32imm: 76963f3544a7f6ca09e7515d6b0e1bf9e8e884131e2Evan Cheng case ARM::t2MOVCCi32imm: { 770431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned PredReg = 0; 771431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); 772b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 773431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 77463f3544a7f6ca09e7515d6b0e1bf9e8e884131e2Evan Cheng bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 77563f3544a7f6ca09e7515d6b0e1bf9e8e884131e2Evan Cheng const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 776431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder LO16, HI16; 777431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 77863f3544a7f6ca09e7515d6b0e1bf9e8e884131e2Evan Cheng if (!STI->hasV6T2Ops() && 77963f3544a7f6ca09e7515d6b0e1bf9e8e884131e2Evan Cheng (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 780893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng // Expand into a movi + orr. 781893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 782893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 783893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 784893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng .addReg(DstReg); 785893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng 786893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 787893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng unsigned ImmVal = (unsigned)MO.getImm(); 788893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 789893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 790893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng LO16 = LO16.addImm(SOImmValV1); 791893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng HI16 = HI16.addImm(SOImmValV2); 792893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 793893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 794893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng LO16.addImm(Pred).addReg(PredReg).addReg(0); 795893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng HI16.addImm(Pred).addReg(PredReg).addReg(0); 796893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng TransferImpOps(MI, LO16, HI16); 797893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng MI.eraseFromParent(); 798893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng break; 799893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng } 800893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng 8011ab4b211ea5165445b791277507d58dcf1e46688Jim Grosbach bool isThumb = 8021ab4b211ea5165445b791277507d58dcf1e46688Jim Grosbach (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm); 8031ab4b211ea5165445b791277507d58dcf1e46688Jim Grosbach 8046d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 8051ab4b211ea5165445b791277507d58dcf1e46688Jim Grosbach TII->get(isThumb ? ARM::t2MOVi16 : ARM::MOVi16), 806431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng DstReg); 8076d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 8081ab4b211ea5165445b791277507d58dcf1e46688Jim Grosbach TII->get(isThumb ? ARM::t2MOVTi16 : ARM::MOVTi16)) 80901b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 810431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg); 811431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 812431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isImm()) { 813431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned Imm = MO.getImm(); 814431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned Lo16 = Imm & 0xffff; 815431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned Hi16 = (Imm >> 16) & 0xffff; 816431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng LO16 = LO16.addImm(Lo16); 817431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng HI16 = HI16.addImm(Hi16); 818431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } else { 819431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const GlobalValue *GV = MO.getGlobal(); 820431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned TF = MO.getTargetFlags(); 821431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 822431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 823b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 824431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 825431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 826431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng LO16.addImm(Pred).addReg(PredReg); 827431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng HI16.addImm(Pred).addReg(PredReg); 828431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, LO16, HI16); 829b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 830d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng break; 831d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng } 832d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng 833d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng case ARM::VMOVQQ: { 834d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 835d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 836558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0); 837558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1); 838d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng unsigned SrcReg = MI.getOperand(1).getReg(); 839d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng bool SrcIsKill = MI.getOperand(1).isKill(); 840558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0); 841558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1); 842d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MachineInstrBuilder Even = 843d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 844d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TII->get(ARM::VMOVQ)) 84518f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(EvenDst, 84601b35c25deee3d4cab339e620c12c721e627d609Bob Wilson RegState::Define | getDeadRegState(DstIsDead)) 84718f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(EvenSrc, getKillRegState(SrcIsKill))); 848d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MachineInstrBuilder Odd = 849d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 850d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TII->get(ARM::VMOVQ)) 85118f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(OddDst, 85201b35c25deee3d4cab339e620c12c721e627d609Bob Wilson RegState::Define | getDeadRegState(DstIsDead)) 85318f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(OddSrc, getKillRegState(SrcIsKill))); 854d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TransferImpOps(MI, Even, Odd); 855d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MI.eraseFromParent(); 856ea606bb76b9922f67b678ea48645cdc9bfa0305bBob Wilson break; 857b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 858709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 85973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQIA: 86073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VLDMQDB: { 86173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling unsigned NewOpc = (Opcode == ARM::VLDMQIA) ? ARM::VLDMDIA : ARM::VLDMDDB; 8629d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 86373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 8649d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 86573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 8669d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register destination. 8679d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 8689d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 86973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 87073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the source register. 8719d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 87273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 8739d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 8749d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 8759d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 87673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 8779d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the destination operands (D subregs). 8789d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 8799d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 8809d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 8819d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 88273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 8839d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add an implicit def for the super-register. 8849d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 8859d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 8869d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 8879d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson break; 8889d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 8899d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 89073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQIA: 89173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling case ARM::VSTMQDB: { 89273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling unsigned NewOpc = (Opcode == ARM::VSTMQIA) ? ARM::VSTMDIA : ARM::VSTMDDB; 8939d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 89473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 8959d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 89673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 8979d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register source. 8989d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 8999d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 90073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 90173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the destination register. 9029d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 90373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9049d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 9059d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 9069d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 90773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9089d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the source operands (D subregs). 9099d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 9109d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 9119d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0).addReg(D1); 91273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9139d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson if (SrcIsKill) 9149d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add an implicit kill for the Q register. 9159d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson (*MIB).addRegisterKilled(SrcReg, TRI, true); 91673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9179d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 9189d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 9199d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson break; 9209d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 92165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach case ARM::VDUPfqf: 92265dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach case ARM::VDUPfdf:{ 92365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLNfq : ARM::VDUPLNfd; 92465dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MachineInstrBuilder MIB = 92565dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 92665dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned OpIdx = 0; 92765dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned SrcReg = MI.getOperand(1).getReg(); 92865dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned Lane = getARMRegisterNumbering(SrcReg) & 1; 92965dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned DReg = TRI->getMatchingSuperReg(SrcReg, 93065dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass); 93165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // The lane is [0,1] for the containing DReg superregister. 93265dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Copy the dst/src register operands. 93365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 93465dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addReg(DReg); 93565dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach ++OpIdx; 93665dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Add the lane select operand. 93765dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addImm(Lane); 93865dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Add the predicate operands. 93965dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 94065dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 94165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach 94265dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach TransferImpOps(MI, MIB, MIB); 94365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MI.eraseFromParent(); 94465dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach break; 94565dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach } 9469d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 947ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q8Pseudo: 948ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q16Pseudo: 949ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q32Pseudo: 950ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q64Pseudo: 951ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q8Pseudo_UPD: 952ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q16Pseudo_UPD: 953ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q32Pseudo_UPD: 954ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q64Pseudo_UPD: 955ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d8Pseudo: 956ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d16Pseudo: 957ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d32Pseudo: 958ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo: 959ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo: 960ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo: 961ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d8Pseudo_UPD: 962ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d16Pseudo_UPD: 963ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d32Pseudo_UPD: 964ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo_UPD: 965ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo_UPD: 966ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo_UPD: 967f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo: 968f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo: 969f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo: 970ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo: 971f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo_UPD: 972f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo_UPD: 973f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo_UPD: 974ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo_UPD: 975f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8Pseudo_UPD: 976f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16Pseudo_UPD: 977f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32Pseudo_UPD: 978f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8oddPseudo_UPD: 979f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16oddPseudo_UPD: 980f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32oddPseudo_UPD: 981f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo: 982f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo: 983f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo: 984ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo: 985f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo_UPD: 986f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo_UPD: 987f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo_UPD: 988ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo_UPD: 989f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8Pseudo_UPD: 990f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16Pseudo_UPD: 991f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32Pseudo_UPD: 992f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8oddPseudo_UPD: 993f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16oddPseudo_UPD: 994f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32oddPseudo_UPD: 9952a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq8Pseudo: 9962a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq16Pseudo: 9972a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq32Pseudo: 9982a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq8Pseudo_UPD: 9992a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq16Pseudo_UPD: 10002a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq32Pseudo_UPD: 1001b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd8Pseudo: 1002b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd16Pseudo: 1003b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd32Pseudo: 1004b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd8Pseudo_UPD: 1005b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd16Pseudo_UPD: 1006b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd32Pseudo_UPD: 100786c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo: 100886c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo: 100986c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo: 101086c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo_UPD: 101186c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo_UPD: 101286c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo_UPD: 10136c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo: 10146c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo: 10156c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo: 10166c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo_UPD: 10176c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo_UPD: 10186c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo_UPD: 10198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVLD(MBBI); 10208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson break; 1021ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 1022e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q8Pseudo: 1023e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q16Pseudo: 1024e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q32Pseudo: 1025e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q64Pseudo: 1026e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q8Pseudo_UPD: 1027e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q16Pseudo_UPD: 1028e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q32Pseudo_UPD: 1029e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q64Pseudo_UPD: 1030e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d8Pseudo: 1031e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d16Pseudo: 1032e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d32Pseudo: 1033e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo: 1034e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo: 1035e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo: 1036e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d8Pseudo_UPD: 1037e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d16Pseudo_UPD: 1038e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d32Pseudo_UPD: 1039e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo_UPD: 1040e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo_UPD: 1041e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo_UPD: 104201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo: 104301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo: 104401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo: 104501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo: 104601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo_UPD: 104701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo_UPD: 104801ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo_UPD: 104901ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo_UPD: 105001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8Pseudo_UPD: 105101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16Pseudo_UPD: 105201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32Pseudo_UPD: 105301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8oddPseudo_UPD: 105401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16oddPseudo_UPD: 105501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32oddPseudo_UPD: 1056709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo: 1057709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo: 1058709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo: 105970e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo: 1060709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo_UPD: 1061709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo_UPD: 1062709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo_UPD: 106370e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo_UPD: 1064709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8Pseudo_UPD: 1065709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16Pseudo_UPD: 1066709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32Pseudo_UPD: 1067709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8oddPseudo_UPD: 1068709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16oddPseudo_UPD: 1069709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32oddPseudo_UPD: 10708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVST(MBBI); 10718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson break; 10728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1073b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo: 1074b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo: 1075b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo: 1076b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo_UPD: 1077b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo_UPD: 1078b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo_UPD: 10798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo: 10808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo: 10818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo: 10828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo: 10838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo: 10848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo_UPD: 10858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo_UPD: 10868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo_UPD: 10878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo_UPD: 10888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo_UPD: 10898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo: 10908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo: 10918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo: 10928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo: 10938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo: 10948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo_UPD: 10958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo_UPD: 10968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo_UPD: 10978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo_UPD: 10988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo_UPD: 10998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo: 11008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo: 11018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo: 11028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo: 11038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo: 11048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo_UPD: 11058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo_UPD: 11068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo_UPD: 11078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo_UPD: 11088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo_UPD: 1109d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo: 1110d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo: 1111d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo: 1112d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo_UPD: 1113d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo_UPD: 1114d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo_UPD: 11158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo: 11168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo: 11178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo: 11188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo: 11198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo: 11208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo_UPD: 11218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo_UPD: 11228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo_UPD: 11238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo_UPD: 11248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo_UPD: 11258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo: 11268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo: 11278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo: 11288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo: 11298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo: 11308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo_UPD: 11318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo_UPD: 11328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo_UPD: 11338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo_UPD: 11348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo_UPD: 11358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo: 11368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo: 11378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo: 11388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo: 11398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo: 11408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo_UPD: 11418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo_UPD: 11428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo_UPD: 11438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo_UPD: 11448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo_UPD: 11458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandLaneOp(MBBI); 11468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson break; 1147bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 11483a6756cb1c87908f5d04660b6ed7d464b56f78f6Bob Wilson case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break; 11493a6756cb1c87908f5d04660b6ed7d464b56f78f6Bob Wilson case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break; 11503a6756cb1c87908f5d04660b6ed7d464b56f78f6Bob Wilson case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break; 11513a6756cb1c87908f5d04660b6ed7d464b56f78f6Bob Wilson case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break; 11523a6756cb1c87908f5d04660b6ed7d464b56f78f6Bob Wilson case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break; 11533a6756cb1c87908f5d04660b6ed7d464b56f78f6Bob Wilson case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break; 1154b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 1155709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 1156709d59255a3100c7d440c93069efa1f726677a27Bob Wilson if (ModifiedOp) 1157709d59255a3100c7d440c93069efa1f726677a27Bob Wilson Modified = true; 1158b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MBBI = NMBBI; 1159b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 1160b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1161b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1162b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1163b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1164b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 1165e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach TII = static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 1166d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TRI = MF.getTarget().getRegisterInfo(); 1167893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng STI = &MF.getTarget().getSubtarget<ARMSubtarget>(); 1168b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1169b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 1170b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1171b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng ++MFI) 1172b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng Modified |= ExpandMBB(*MFI); 1173b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1174b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1175b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1176b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1177b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// expansion pass. 1178b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan ChengFunctionPass *llvm::createARMExpandPseudoPass() { 1179b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return new ARMExpandPseudo(); 1180b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1181