ARMExpandPseudoInsts.cpp revision e837dead3c8dc3445ef6a0e2322179c57e264a13
1b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=// 2b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 3b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// The LLVM Compiler Infrastructure 4b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 5b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// This file is distributed under the University of Illinois Open Source 6b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// License. See LICENSE.TXT for details. 7b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 8b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 9b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 10656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// This file contains a pass that expands pseudo instructions into target 11b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// instructions to allow proper scheduling, if-conversion, and other late 12b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// optimizations. This pass should be run after register allocation but before 13656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// the post-regalloc scheduling pass. 14b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 15b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 16b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 17b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#define DEBUG_TYPE "arm-pseudo" 18b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARM.h" 197032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach#include "ARMAddressingModes.h" 20b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARMBaseInstrInfo.h" 21e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMBaseRegisterInfo.h" 22e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMMachineFunctionInfo.h" 2365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach#include "ARMRegisterInfo.h" 24e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/CodeGen/MachineFrameInfo.h" 25b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineFunctionPass.h" 26b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 2716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 284dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "llvm/Target/TargetRegisterInfo.h" 29e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 30b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengusing namespace llvm; 31b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 32b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengnamespace { 33b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng class ARMExpandPseudo : public MachineFunctionPass { 34b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng public: 35b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng static char ID; 3690c579de5a383cee278acc3f7e7b9d0a656e6a35Owen Anderson ARMExpandPseudo() : MachineFunctionPass(ID) {} 37b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 38e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *TII; 39d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng const TargetRegisterInfo *TRI; 40893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng const ARMSubtarget *STI; 419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ARMFunctionInfo *AFI; 42b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 43b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual bool runOnMachineFunction(MachineFunction &Fn); 44b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 45b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual const char *getPassName() const { 46b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return "ARM pseudo instruction expansion pass"; 47b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 48b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 49b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng private: 50431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng void TransferImpOps(MachineInstr &OldMI, 51431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool ExpandMI(MachineBasicBlock &MBB, 539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI); 54b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool ExpandMBB(MachineBasicBlock &MBB); 558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVLD(MachineBasicBlock::iterator &MBBI); 568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVST(MachineBasicBlock::iterator &MBBI); 578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 58bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 59bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned Opc, bool IsExt, unsigned NumRegs); 609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng void ExpandMOV32BitImm(MachineBasicBlock &MBB, 619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI); 62b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng }; 63b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng char ARMExpandPseudo::ID = 0; 64b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 65b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 66431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// TransferImpOps - Transfer implicit operands on the pseudo instruction to 67431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// the instructions created from the expansion. 68431300797b84600fc9b4eb8ca283277d3e0674ebEvan Chengvoid ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 69431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, 70431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &DefMI) { 71e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = OldMI.getDesc(); 72431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 73431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng i != e; ++i) { 74431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const MachineOperand &MO = OldMI.getOperand(i); 75431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng assert(MO.isReg() && MO.getReg()); 76431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isUse()) 7763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson UseMI.addOperand(MO); 78431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng else 7963569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson DefMI.addOperand(MO); 80431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } 81431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng} 82431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonnamespace { 848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Constants for register spacing in NEON load/store instructions. 858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // For quad-register load-lane and store-lane pseudo instructors, the 868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // spacing is initially assumed to be EvenDblSpc, and that is changed to 878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // OddDblSpc depending on the lane number operand. 888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson enum NEONRegSpacing { 898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson SingleSpc, 908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson EvenDblSpc, 918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson OddDblSpc 928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Entries for NEON load/store information table. The table is sorted by 958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // PseudoOpc for fast binary-search lookups. 968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson struct NEONLdStTableEntry { 978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned PseudoOpc; 988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RealOpc; 998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool IsLoad; 1008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool HasWriteBack; 1018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpacing; 1028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char NumRegs; // D registers loaded or stored 1038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char RegElts; // elements per D register; used for lane ops 1048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Comparison methods for binary search of the table. 1068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool operator<(const NEONLdStTableEntry &TE) const { 1078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 1108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return TE.PseudoOpc < PseudoOpc; 1118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 112100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 113100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth const NEONLdStTableEntry &TE) { 1148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 1188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry NEONLdStTable[] = { 1202a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4}, 1212a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4}, 1222a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2}, 1232a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2}, 1242a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8}, 1252a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson{ ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8}, 1262a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson 127b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 }, 128d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 }, 129b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 }, 130d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 }, 131b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 }, 132d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 }, 133b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson 1348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, 1358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, 1368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 }, 1378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 }, 1388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 }, 1408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 }, 1418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 }, 1428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 }, 1438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 }, 1448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 }, 1458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 }, 1468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 }, 1478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 148b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4}, 149b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4}, 150b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2}, 151b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2}, 152b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8}, 153b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson{ ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8}, 154b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson 1558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 }, 1568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 }, 1578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 }, 1588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 }, 1598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 }, 1608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 }, 1618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 }, 1628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 }, 1638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 }, 1648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 }, 1658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 }, 1678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 }, 1688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 }, 1698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 }, 1708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 }, 1718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 }, 1728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 }, 1748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 }, 1758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 }, 1768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 }, 1778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 }, 1788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 }, 1798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 18086c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4}, 18186c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4}, 18286c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2}, 18386c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2}, 18486c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8}, 18586c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8}, 18686c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson 1878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 }, 1888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 }, 1898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 }, 1908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 }, 1918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 }, 1928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 }, 1938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 }, 1948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 }, 1958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 }, 1968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 }, 1978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 }, 1998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 }, 2008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 }, 2018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 }, 2028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 }, 2038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 }, 2048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 }, 2067de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, OddDblSpc, 3, 4 }, 2078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 }, 2088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 }, 2097de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, OddDblSpc, 3, 2 }, 2108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 }, 2118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 }, 2127de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, OddDblSpc, 3, 8 }, 2138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 }, 2148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2156c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4}, 2166c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4}, 2176c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2}, 2186c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2}, 2196c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8}, 2206c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8}, 2216c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson 2228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 }, 2238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 }, 2248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 }, 2258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 }, 2268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 }, 2278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 }, 2288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 }, 2298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 }, 2308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 }, 2318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 }, 2328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 }, 2348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 }, 2358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 }, 2368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 }, 2378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 }, 2388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 }, 2398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 }, 2417de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, OddDblSpc, 4, 4 }, 2428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 }, 2438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 }, 2447de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, OddDblSpc, 4, 2 }, 2458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 }, 2468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 }, 2477de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, OddDblSpc, 4, 8 }, 2488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 }, 2498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 250d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 }, 251d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 }, 252d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 }, 253d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 }, 254d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 }, 255d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 }, 256d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson 2578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 }, 2588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 }, 2598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 }, 2608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 }, 2618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 }, 2638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 }, 2648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 }, 2658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 }, 2668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 }, 2678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 }, 2688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 }, 2698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 }, 2708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 }, 2728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 }, 2738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 }, 2748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 }, 2758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 }, 2768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 }, 2778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4}, 2788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4}, 2798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2}, 2808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2}, 2818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 }, 2838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 }, 2848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 }, 2858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 }, 2868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 }, 2878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 }, 2888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 }, 2908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 }, 2918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 }, 2928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 }, 2938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 }, 2948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 }, 2958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 }, 2978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 }, 2988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 }, 2998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 }, 3008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 }, 3018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 }, 3028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4}, 3038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4}, 3048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2}, 3058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2}, 3068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 }, 3088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 }, 3098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 }, 3108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 }, 3118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 }, 3128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 }, 3138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 }, 3157de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, OddDblSpc, 3, 4 }, 3168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 }, 3178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 }, 3187de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, OddDblSpc, 3, 2 }, 3198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 }, 3208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 }, 3217de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, OddDblSpc, 3, 8 }, 3228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 }, 3238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 }, 3258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 }, 3268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 }, 3278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 }, 3288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 }, 3298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 }, 3308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4}, 3318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4}, 3328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2}, 3338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2}, 3348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 }, 3368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 }, 3378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 }, 3388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 }, 3398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 }, 3408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 }, 3418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 }, 3437de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, OddDblSpc, 4, 4 }, 3448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 }, 3458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 }, 3467de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, OddDblSpc, 4, 2 }, 3478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 }, 3488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 }, 3497de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, OddDblSpc, 4, 8 }, 3507de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 } 3518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson}; 3528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 3548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// load or store pseudo instruction. 3558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 3568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumEntries = array_lengthof(NEONLdStTable); 3578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#ifndef NDEBUG 3598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Make sure the table is sorted. 3608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson static bool TableChecked = false; 3618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableChecked) { 3628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson for (unsigned i = 0; i != NumEntries-1; ++i) 3638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(NEONLdStTable[i] < NEONLdStTable[i+1] && 3648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson "NEONLdStTable is not sorted!"); 3658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TableChecked = true; 3668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 3678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#endif 3688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *I = 3708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); 3718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) 3728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return I; 3738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return NULL; 3748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 3778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// corresponding to the specified register spacing. Not all of the results 3788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// are necessarily valid, e.g., a Q register only has 2 D subregisters. 3798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 3808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const TargetRegisterInfo *TRI, unsigned &D0, 3818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned &D1, unsigned &D2, unsigned &D3) { 3828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == SingleSpc) { 3838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_1); 3858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_2); 3868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_3); 3878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else if (RegSpc == EvenDblSpc) { 3888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_2); 3908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_4); 3918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_6); 3928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else { 3938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc == OddDblSpc && "unknown register spacing"); 3948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_1); 3958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_3); 3968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_5); 3978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_7); 398bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson } 3998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 4008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 40182a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 40282a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// operands to real VLD instructions with D register operands. 4038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 404ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineInstr &MI = *MBBI; 405ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 406ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 4078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 4098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 4108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 4138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 414ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned OpIdx = 0; 415ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 416ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 417ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 418ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned D0, D1, D2, D3; 4198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 420f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 421f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 422ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson if (NumRegs > 2) 423f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 424ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson if (NumRegs > 3) 425f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 426ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 4278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 42863569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 42963569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 430ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson // Copy the addrmode6 operands. 43163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 43263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 43363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 4348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 43563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 436ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 43719d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // For an instruction writing double-spaced subregs, the pseudo instruction 438823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // has an extra operand that is a use of the super-register. Record the 439823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // operand index and skip over it. 440823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcOpIdx = 0; 441823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 442823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson SrcOpIdx = OpIdx++; 443823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 444823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 445823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 446823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 447823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 448823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the super-register source operand used for double-spaced subregs over 44919d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // to the new instruction as an implicit operand. 450823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (SrcOpIdx != 0) { 451823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MachineOperand MO = MI.getOperand(SrcOpIdx); 45219d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MO.setImplicit(true); 45319d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MIB.addOperand(MO); 45419d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson } 455f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson // Add an implicit def for the super-register. 456f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 45719d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson TransferImpOps(MI, MIB, MIB); 458b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 459b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 460d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 461b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 462ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MI.eraseFromParent(); 463ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson} 464ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 46501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 46601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// operands to real VST instructions with D register operands. 4678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 468709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineInstr &MI = *MBBI; 469709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 470709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 4738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 4748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 4778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 478709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned OpIdx = 0; 4798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 48063569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 48163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 482709d59255a3100c7d440c93069efa1f726677a27Bob Wilson // Copy the addrmode6 operands. 48363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 48463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 48563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 4868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 48763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 488709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 489709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 490823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 491709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned D0, D1, D2, D3; 4928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 4937e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D0).addReg(D1); 494e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson if (NumRegs > 2) 4957e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D2); 49601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson if (NumRegs > 3) 4977e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D3); 498823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 499823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 500823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 501823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 502823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 503d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner if (SrcIsKill) // Add an implicit kill for the super-reg. 504d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 505bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 506b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 507b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 508d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 509b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 510709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MI.eraseFromParent(); 511709d59255a3100c7d440c93069efa1f726677a27Bob Wilson} 512709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 5138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 5148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// register operands to real instructions with D register operands. 5158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 5168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstr &MI = *MBBI; 5178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 5188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 5208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && "NEONLdStTable lookup failed"); 5218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 5228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 5238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RegElts = TableEntry->RegElts; 5248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 5268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 5278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned OpIdx = 0; 5288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // The lane operand is always the 3rd from last operand, before the 2 5298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // predicate operands. 5308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 5318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Adjust the lane and spacing as needed for Q registers. 5338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 5348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == EvenDblSpc && Lane >= RegElts) { 5358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson RegSpc = OddDblSpc; 5368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson Lane -= RegElts; 5378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 5398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 540584520e8e2c1f8cc04bc8dd4dc4ea6c390627317Ted Kremenek unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 541fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned DstReg = 0; 542fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson bool DstIsDead = false; 5438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) { 5448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstIsDead = MI.getOperand(OpIdx).isDead(); 5458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstReg = MI.getOperand(OpIdx++).getReg(); 5468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 547b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 548b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 549b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 5508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 5528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 5548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 5578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the addrmode6 operands. 5608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the am6offset operand. 5638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 5648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Grab the super-register source. 5678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineOperand MO = MI.getOperand(OpIdx++); 5688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableEntry->IsLoad) 5698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 5708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the subregs as sources of the new instruction. 5728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 5738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson getKillRegState(MO.isKill())); 574b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, SrcFlags); 575b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 576b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, SrcFlags); 5778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, SrcFlags); 5798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, SrcFlags); 5818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the lane number operand. 5838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addImm(Lane); 584823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson OpIdx += 1; 585823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 586823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 587823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 588823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the super-register source to be an implicit source. 5918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MO.setImplicit(true); 5928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MO); 5938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) 5948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add an implicit def for the super-register. 5958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 5968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TransferImpOps(MI, MIB, MIB); 5978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MI.eraseFromParent(); 5988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 5998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 600bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 601bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// register operands to real instructions with D register operands. 602bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilsonvoid ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 603bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned Opc, bool IsExt, unsigned NumRegs) { 604bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstr &MI = *MBBI; 605bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 606bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 607bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 608bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned OpIdx = 0; 609bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 610bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Transfer the destination register operand. 611bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 612bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (IsExt) 613bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 614bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 615bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 616bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 617bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned D0, D1, D2, D3; 618bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 619bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D0).addReg(D1); 620bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (NumRegs > 2) 621bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D2); 622bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (NumRegs > 3) 623bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D3); 624bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 625bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Copy the other source register operand. 626823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 627823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 628823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 629823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 630823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 631bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 632d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner if (SrcIsKill) // Add an implicit kill for the super-reg. 633d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 634bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 635bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MI.eraseFromParent(); 636bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson} 637bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 6389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengvoid ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 6399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI) { 6409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 6419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 6429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PredReg = 0; 6439fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); 6449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 6459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 6469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 6479fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 6489fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder LO16, HI16; 6499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6509fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!STI->hasV6T2Ops() && 6519fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 6529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Expand into a movi + orr. 6539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 6549fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 6559fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 6569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 6579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6589fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 6599fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned ImmVal = (unsigned)MO.getImm(); 6609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 6619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 6629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(SOImmValV1); 6639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(SOImmValV2); 664d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 665d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 6669fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg).addReg(0); 6679fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg).addReg(0); 6689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 6699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 6709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return; 6719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 672b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 6739fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LO16Opc = 0; 6749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned HI16Opc = 0; 6759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 6769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::t2MOVi16; 6779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::t2MOVTi16; 6789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else { 6799fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::MOVi16; 6809fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::MOVTi16; 6819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 682b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 6839fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 6849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 6859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 6869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 6879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (MO.isImm()) { 6899fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Imm = MO.getImm(); 6909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Lo16 = Imm & 0xffff; 6919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Hi16 = (Imm >> 16) & 0xffff; 6929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(Lo16); 6939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(Hi16); 6949fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else { 6959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO.getGlobal(); 6969fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO.getTargetFlags(); 6979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 6989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 6999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 700709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 701d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 702d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 7039fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg); 7049fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg); 7059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 7069fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 7079fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 7089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 7099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 7109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 7119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI) { 7129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 7139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 7149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng switch (Opcode) { 7159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng default: 7169fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 717f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVScc: 718f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVDcc: { 719f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; 720f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 721f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.getOperand(1).getReg()) 722f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addReg(MI.getOperand(2).getReg(), 723f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach getKillRegState(MI.getOperand(2).isKill())) 724f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 725f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addReg(MI.getOperand(4).getReg()); 726f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach 727f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.eraseFromParent(); 728f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach return true; 729f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach } 730d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach case ARM::MOVCCr: { 731d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr), 732d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.getOperand(1).getReg()) 733d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(2).getReg(), 734d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach getKillRegState(MI.getOperand(2).isKill())) 735d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 736d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(4).getReg()) 737d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 738d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 739d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 740d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 741d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 742d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach case ARM::MOVCCs: { 743d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 744d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach (MI.getOperand(1).getReg())) 745d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(2).getReg(), 746d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach getKillRegState(MI.getOperand(2).isKill())) 747d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(3).getReg(), 748d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach getKillRegState(MI.getOperand(3).isKill())) 749d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(4).getImm()) 750d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(5).getImm()) // 'pred' 751d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(MI.getOperand(6).getReg()) 752d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 7533906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach 7543906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 7553906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 7563906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 7573906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi16: { 7583906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16), 7593906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 7603906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 7613906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 7623906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(MI.getOperand(4).getReg()); 7633906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach 7643906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 7653906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 7663906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 7673906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi: { 7683906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), 7693906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 7703906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 7713906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 7723906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(MI.getOperand(4).getReg()) 7733906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(0); // 's' bit 774e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach 775e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.eraseFromParent(); 776e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach return true; 777e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach } 778e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach case ARM::MVNCCi: { 779e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), 780e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.getOperand(1).getReg()) 781e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(2).getImm()) 782e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 783e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addReg(MI.getOperand(4).getReg()) 784e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addReg(0); // 's' bit 785d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 786d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 787d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 788d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 789e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach case ARM::Int_eh_sjlj_dispatchsetup: { 790e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MachineFunction &MF = *MI.getParent()->getParent(); 791e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *AII = 792e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach static_cast<const ARMBaseInstrInfo*>(TII); 793e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 794e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // For functions using a base pointer, we rematerialize it (via the frame 795e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 796e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // for us. Otherwise, expand to nothing. 797e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (RI.hasBasePointer(MF)) { 798e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int32_t NumBytes = AFI->getFramePtrSpillOffset(); 799e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned FramePtr = RI.getFrameRegister(MF); 80016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 8017920d96964d707a3af85332c98d95b2fabc3d5c9Benjamin Kramer "base pointer without frame pointer?"); 802e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 803e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (AFI->isThumb2Function()) { 804e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 805e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 806e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else if (AFI->isThumbFunction()) { 80757caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov llvm::emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 80857caad7a33ff145b71545f10dcfbbf2fd0f595d3Anton Korobeynikov FramePtr, -NumBytes, *TII, RI); 809e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else { 810e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 811e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach FramePtr, -NumBytes, ARMCC::AL, 0, 812e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach *TII); 813e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 8148b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // If there's dynamic realignment, adjust for it. 815b8e67fc92b0a508e3782b782baa98a6d56d5d7eaJim Grosbach if (RI.needsStackRealignment(MF)) { 8168b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 8178b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 8188b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 8198b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // Emit bic r6, r6, MaxAlign 8208b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned bicOpc = AFI->isThumbFunction() ? 8218b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach ARM::t2BICri : ARM::BICri; 8228b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 8238b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach TII->get(bicOpc), ARM::R6) 8248b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addReg(ARM::R6, RegState::Kill) 8258b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addImm(MaxAlign-1))); 8268b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach } 827e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 828e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 829e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MI.eraseFromParent(); 8309fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 831e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 832e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 8337032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsrl_flag: 8347032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsra_flag: { 8357032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // These are just fancy MOVs insructions. 836dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 837dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands MI.getOperand(0).getReg()) 8389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 8399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(0) 8409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr 8419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng : ARM_AM::asr), 1))) 8429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(ARM::CPSR, RegState::Define); 8437032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 8449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 8457032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 8467032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::RRX: { 8477032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // This encodes as "MOVs Rd, Rm, rrx 8487032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MachineInstrBuilder MIB = 8497032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 8507032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.getOperand(0).getReg()) 8519fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 8529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 8539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 8547032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addReg(0); 8557032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach TransferImpOps(MI, MIB, MIB); 8567032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 8579fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 8587032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 859a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim case ARM::TPsoft: { 860971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson MachineInstrBuilder MIB = 861a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim BuildMI(MBB, MBBI, MI.getDebugLoc(), 862a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim TII->get(ARM::BL)) 863a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim .addExternalSymbol("__aeabi_read_tp", 0); 864a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim 865d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 866a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim TransferImpOps(MI, MIB, MIB); 867a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim MI.eraseFromParent(); 8689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 8692fe813af23e682b418ecd477144fe070be325419Bill Wendling } 870bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::tLDRpci_pic: 871b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng case ARM::t2LDRpci_pic: { 872b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 873971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson ? ARM::tLDRpci : ARM::t2LDRpci; 874b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 875431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 876431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB1 = 877971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 878971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson TII->get(NewLdOpc), DstReg) 879971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson .addOperand(MI.getOperand(1))); 880d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 881431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 882431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TII->get(ARM::tPICADD)) 88301b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 884431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg) 885431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addOperand(MI.getOperand(2)); 886431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, MIB1, MIB2); 887b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 8889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 889b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 890431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 89153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_dyn: 89253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel: 89353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel_ldr: 89453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOV_ga_dyn: 89553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOV_ga_pcrel: { 89653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 8979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LabelId = AFI->createPICLabelUId(); 898b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 899431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 9009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI.getOperand(1); 9019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO1.getGlobal(); 9029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO1.getTargetFlags(); 903670350bb782f6268126f7f8afefe86ab05b5b23dOwen Anderson bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode != ARM::t2MOV_ga_dyn); 90453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn); 90553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 90653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel : ARM::t2MOVTi16_ga_pcrel; 90753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned LO16TF = isPIC 90853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY; 90953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned HI16TF = isPIC 91053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY; 9119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PICAddOpc = isARM 91253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 9139fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng : ARM::tPICADD; 9149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 9159fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(LO16Opc), DstReg) 91653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 9179fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 91853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 91953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TII->get(HI16Opc), DstReg) 9209fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg) 92153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 9229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 92353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (!isPIC) { 92453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TransferImpOps(MI, MIB1, MIB2); 92553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MI.eraseFromParent(); 92653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng return true; 92753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng } 92853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng 92953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 9309fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(PICAddOpc)) 93101b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 9329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg).addImm(LabelId); 9339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (isARM) { 93453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng AddDefaultPred(MIB3); 93553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_pcrel_ldr) 936d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 9375de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng } 93853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TransferImpOps(MI, MIB1, MIB3); 939b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 9409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 941d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng } 942d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng 9439fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVi32imm: 9449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVCCi32imm: 9459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVi32imm: 9469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVCCi32imm: 9479fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ExpandMOV32BitImm(MBB, MBBI); 9489fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 950d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng case ARM::VMOVQQ: { 951d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 952d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 953558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0); 954558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1); 955d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng unsigned SrcReg = MI.getOperand(1).getReg(); 956d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng bool SrcIsKill = MI.getOperand(1).isKill(); 957558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0); 958558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1); 959d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MachineInstrBuilder Even = 960d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 961d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TII->get(ARM::VMOVQ)) 9629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(EvenDst, 9639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng RegState::Define | getDeadRegState(DstIsDead)) 9649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(EvenSrc, getKillRegState(SrcIsKill))); 965d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MachineInstrBuilder Odd = 966d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 967d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TII->get(ARM::VMOVQ)) 9689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(OddDst, 9699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng RegState::Define | getDeadRegState(DstIsDead)) 9709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(OddSrc, getKillRegState(SrcIsKill))); 971d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TransferImpOps(MI, Even, Odd); 972d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MI.eraseFromParent(); 9739fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 974b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 975709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 976848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VLDMQIA: { 977848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VLDMDIA; 9789d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 97973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 9809d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 98173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9829d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register destination. 9839d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 9849d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 98573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 98673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the source register. 9879d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 98873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9899d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 9909d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 9919d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 99273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9939d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the destination operands (D subregs). 9949d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 9959d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 9969d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 9979d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 99873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 9999d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add an implicit def for the super-register. 10009d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 10019d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 10029d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 10039fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 10049d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 10059d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 1006848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VSTMQIA: { 1007848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VSTMDIA; 10089d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 100973fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 10109d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 101173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 10129d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register source. 10139d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 10149d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 101573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 101673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the destination register. 10179d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 101873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 10199d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 10209d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 10219d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 102273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 10239d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the source operands (D subregs). 10249d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 10259d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 10269d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0).addReg(D1); 102773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1028d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner if (SrcIsKill) // Add an implicit kill for the Q register. 1029d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 103073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 10319d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 10329d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 10339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 10349d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 103565dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach case ARM::VDUPfqf: 103665dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach case ARM::VDUPfdf:{ 10378b8515c225c799e9df69bde8ffffa3c72cec9445Jim Grosbach unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : 10388b8515c225c799e9df69bde8ffffa3c72cec9445Jim Grosbach ARM::VDUPLN32d; 103965dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MachineInstrBuilder MIB = 104065dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 104165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned OpIdx = 0; 104265dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned SrcReg = MI.getOperand(1).getReg(); 104365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned Lane = getARMRegisterNumbering(SrcReg) & 1; 104465dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach unsigned DReg = TRI->getMatchingSuperReg(SrcReg, 1045b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3Jim Grosbach Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, 1046b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3Jim Grosbach &ARM::DPR_VFP2RegClass); 104765dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // The lane is [0,1] for the containing DReg superregister. 104865dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Copy the dst/src register operands. 104965dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 105065dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addReg(DReg); 105165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach ++OpIdx; 105265dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Add the lane select operand. 105365dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addImm(Lane); 105465dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach // Add the predicate operands. 105565dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 105665dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MIB.addOperand(MI.getOperand(OpIdx++)); 105765dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach 105865dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach TransferImpOps(MI, MIB, MIB); 105965dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach MI.eraseFromParent(); 10609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 106165dc30340cf874307eae11ec1195a1cd6d27fb13Jim Grosbach } 10629d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 1063ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q8Pseudo: 1064ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q16Pseudo: 1065ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q32Pseudo: 1066ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q64Pseudo: 1067ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q8Pseudo_UPD: 1068ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q16Pseudo_UPD: 1069ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q32Pseudo_UPD: 1070ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q64Pseudo_UPD: 1071ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d8Pseudo: 1072ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d16Pseudo: 1073ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d32Pseudo: 1074ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo: 1075ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo: 1076ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo: 1077ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d8Pseudo_UPD: 1078ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d16Pseudo_UPD: 1079ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d32Pseudo_UPD: 1080ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo_UPD: 1081ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo_UPD: 1082ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo_UPD: 1083f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo: 1084f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo: 1085f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo: 1086ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo: 1087f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo_UPD: 1088f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo_UPD: 1089f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo_UPD: 1090ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo_UPD: 1091f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8Pseudo_UPD: 1092f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16Pseudo_UPD: 1093f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32Pseudo_UPD: 10947de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q8oddPseudo: 10957de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q16oddPseudo: 10967de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q32oddPseudo: 1097f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8oddPseudo_UPD: 1098f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16oddPseudo_UPD: 1099f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32oddPseudo_UPD: 1100f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo: 1101f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo: 1102f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo: 1103ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo: 1104f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo_UPD: 1105f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo_UPD: 1106f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo_UPD: 1107ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo_UPD: 1108f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8Pseudo_UPD: 1109f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16Pseudo_UPD: 1110f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32Pseudo_UPD: 11117de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q8oddPseudo: 11127de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q16oddPseudo: 11137de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q32oddPseudo: 1114f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8oddPseudo_UPD: 1115f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16oddPseudo_UPD: 1116f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32oddPseudo_UPD: 11172a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq8Pseudo: 11182a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq16Pseudo: 11192a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq32Pseudo: 11202a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq8Pseudo_UPD: 11212a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq16Pseudo_UPD: 11222a0e97431ecef2aa6a24a16ced207d5b53fcfc2dBob Wilson case ARM::VLD1DUPq32Pseudo_UPD: 1123b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd8Pseudo: 1124b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd16Pseudo: 1125b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd32Pseudo: 1126b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd8Pseudo_UPD: 1127b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd16Pseudo_UPD: 1128b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson case ARM::VLD2DUPd32Pseudo_UPD: 112986c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo: 113086c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo: 113186c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo: 113286c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo_UPD: 113386c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo_UPD: 113486c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo_UPD: 11356c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo: 11366c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo: 11376c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo: 11386c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo_UPD: 11396c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo_UPD: 11406c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo_UPD: 11418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVLD(MBBI); 11429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1143ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 1144e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q8Pseudo: 1145e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q16Pseudo: 1146e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q32Pseudo: 1147e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q64Pseudo: 1148e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q8Pseudo_UPD: 1149e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q16Pseudo_UPD: 1150e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q32Pseudo_UPD: 1151e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q64Pseudo_UPD: 1152e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d8Pseudo: 1153e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d16Pseudo: 1154e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d32Pseudo: 1155e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo: 1156e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo: 1157e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo: 1158e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d8Pseudo_UPD: 1159e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d16Pseudo_UPD: 1160e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d32Pseudo_UPD: 1161e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo_UPD: 1162e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo_UPD: 1163e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo_UPD: 116401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo: 116501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo: 116601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo: 116701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo: 116801ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo_UPD: 116901ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo_UPD: 117001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo_UPD: 117101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo_UPD: 117201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8Pseudo_UPD: 117301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16Pseudo_UPD: 117401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32Pseudo_UPD: 11757de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q8oddPseudo: 11767de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q16oddPseudo: 11777de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q32oddPseudo: 117801ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8oddPseudo_UPD: 117901ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16oddPseudo_UPD: 118001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32oddPseudo_UPD: 1181709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo: 1182709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo: 1183709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo: 118470e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo: 1185709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo_UPD: 1186709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo_UPD: 1187709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo_UPD: 118870e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo_UPD: 1189709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8Pseudo_UPD: 1190709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16Pseudo_UPD: 1191709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32Pseudo_UPD: 11927de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q8oddPseudo: 11937de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q16oddPseudo: 11947de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q32oddPseudo: 1195709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8oddPseudo_UPD: 1196709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16oddPseudo_UPD: 1197709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32oddPseudo_UPD: 11988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVST(MBBI); 11999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 12008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1201b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo: 1202b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo: 1203b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo: 1204b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo_UPD: 1205b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo_UPD: 1206b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo_UPD: 12078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo: 12088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo: 12098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo: 12108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo: 12118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo: 12128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo_UPD: 12138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo_UPD: 12148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo_UPD: 12158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo_UPD: 12168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo_UPD: 12178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo: 12188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo: 12198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo: 12208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo: 12218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo: 12228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo_UPD: 12238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo_UPD: 12248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo_UPD: 12258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo_UPD: 12268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo_UPD: 12278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo: 12288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo: 12298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo: 12308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo: 12318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo: 12328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo_UPD: 12338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo_UPD: 12348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo_UPD: 12358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo_UPD: 12368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo_UPD: 1237d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo: 1238d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo: 1239d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo: 1240d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo_UPD: 1241d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo_UPD: 1242d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo_UPD: 12438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo: 12448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo: 12458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo: 12468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo: 12478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo: 12488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo_UPD: 12498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo_UPD: 12508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo_UPD: 12518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo_UPD: 12528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo_UPD: 12538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo: 12548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo: 12558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo: 12568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo: 12578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo: 12588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo_UPD: 12598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo_UPD: 12608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo_UPD: 12618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo_UPD: 12628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo_UPD: 12638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo: 12648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo: 12658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo: 12668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo: 12678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo: 12688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo_UPD: 12698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo_UPD: 12708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo_UPD: 12718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo_UPD: 12728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo_UPD: 12738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandLaneOp(MBBI); 12749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 12759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); return true; 12779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); return true; 12789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); return true; 12799fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); return true; 12809fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); return true; 12819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); return true; 12829fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 12839fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 12859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 1286709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 12879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 12889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool Modified = false; 12899fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 12909fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 12919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng while (MBBI != E) { 12929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator NMBBI = llvm::next(MBBI); 12939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Modified |= ExpandMI(MBB, MBBI); 1294b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MBBI = NMBBI; 1295b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 1296b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1297b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1298b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1299b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1300b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 130153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng const TargetMachine &TM = MF.getTarget(); 130253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo()); 130353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TRI = TM.getRegisterInfo(); 130453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng STI = &TM.getSubtarget<ARMSubtarget>(); 13059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng AFI = MF.getInfo<ARMFunctionInfo>(); 1306b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1307b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 1308b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1309b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng ++MFI) 1310b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng Modified |= ExpandMBB(*MFI); 1311b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1312b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1313b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1314b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1315b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// expansion pass. 1316b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan ChengFunctionPass *llvm::createARMExpandPseudoPass() { 1317b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return new ARMExpandPseudo(); 1318b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1319