ARMExpandPseudoInsts.cpp revision fe3ac088ee0a536f60b3c30ad97703d5d6cd2167
1b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=// 2b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 3b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// The LLVM Compiler Infrastructure 4b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 5b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// This file is distributed under the University of Illinois Open Source 6b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// License. See LICENSE.TXT for details. 7b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 8b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 9b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 10656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// This file contains a pass that expands pseudo instructions into target 11b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// instructions to allow proper scheduling, if-conversion, and other late 12b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// optimizations. This pass should be run after register allocation but before 13656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// the post-regalloc scheduling pass. 14b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 15b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 16b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 17b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#define DEBUG_TYPE "arm-pseudo" 18b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARM.h" 19b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARMBaseInstrInfo.h" 20b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineFunctionPass.h" 21b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 224dbbe3433f7339ed277af55037ff6847f484e5abChris Lattner#include "llvm/Target/TargetRegisterInfo.h" 23b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengusing namespace llvm; 24b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 25b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengnamespace { 26b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng class ARMExpandPseudo : public MachineFunctionPass { 27b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng public: 28b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng static char ID; 2990c579de5a383cee278acc3f7e7b9d0a656e6a35Owen Anderson ARMExpandPseudo() : MachineFunctionPass(ID) {} 30b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 31b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng const TargetInstrInfo *TII; 32d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng const TargetRegisterInfo *TRI; 33b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 34b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual bool runOnMachineFunction(MachineFunction &Fn); 35b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 36b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng virtual const char *getPassName() const { 37b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return "ARM pseudo instruction expansion pass"; 38b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 39b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 40b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng private: 41431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng void TransferImpOps(MachineInstr &OldMI, 42431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 43b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool ExpandMBB(MachineBasicBlock &MBB); 448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVLD(MachineBasicBlock::iterator &MBBI); 458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVST(MachineBasicBlock::iterator &MBBI); 468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 47bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 48bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned Opc, bool IsExt, unsigned NumRegs); 49b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng }; 50b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng char ARMExpandPseudo::ID = 0; 51b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 52b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 53431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// TransferImpOps - Transfer implicit operands on the pseudo instruction to 54431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// the instructions created from the expansion. 55431300797b84600fc9b4eb8ca283277d3e0674ebEvan Chengvoid ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 56431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, 57431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &DefMI) { 58431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const TargetInstrDesc &Desc = OldMI.getDesc(); 59431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 60431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng i != e; ++i) { 61431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const MachineOperand &MO = OldMI.getOperand(i); 62431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng assert(MO.isReg() && MO.getReg()); 63431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isUse()) 6463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson UseMI.addOperand(MO); 65431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng else 6663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson DefMI.addOperand(MO); 67431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } 68431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng} 69431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonnamespace { 718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Constants for register spacing in NEON load/store instructions. 728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // For quad-register load-lane and store-lane pseudo instructors, the 738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // spacing is initially assumed to be EvenDblSpc, and that is changed to 748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // OddDblSpc depending on the lane number operand. 758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson enum NEONRegSpacing { 768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson SingleSpc, 778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson EvenDblSpc, 788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson OddDblSpc 798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Entries for NEON load/store information table. The table is sorted by 828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // PseudoOpc for fast binary-search lookups. 838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson struct NEONLdStTableEntry { 848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned PseudoOpc; 858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RealOpc; 868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool IsLoad; 878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool HasWriteBack; 888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpacing; 898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char NumRegs; // D registers loaded or stored 908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned char RegElts; // elements per D register; used for lane ops 918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Comparison methods for binary search of the table. 938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool operator<(const NEONLdStTableEntry &TE) const { 948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return TE.PseudoOpc < PseudoOpc; 988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson friend bool ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 1008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry &TE) { 1018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 1058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry NEONLdStTable[] = { 1078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, 1088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, 1098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 }, 1108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 }, 1118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 }, 1138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 }, 1148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 }, 1158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 }, 1168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 }, 1178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 }, 1188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 }, 1198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 }, 1208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 }, 1228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 }, 1238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 }, 1248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 }, 1258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 }, 1268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 }, 1278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 }, 1288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 }, 1298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 }, 1308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 }, 1318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 }, 1338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 }, 1348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 }, 1358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 }, 1368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 }, 1378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 }, 1388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 }, 1408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 }, 1418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 }, 1428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 }, 1438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 }, 1448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 }, 1458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 }, 1478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 }, 1488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 }, 1498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 }, 1508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 }, 1518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 }, 1528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 }, 1538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 }, 1548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 }, 1558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 }, 1568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 }, 1588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 }, 1598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 }, 1608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 }, 1618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 }, 1628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 }, 1638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 }, 1658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 }, 1668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 }, 1678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 }, 1688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 }, 1698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 }, 1708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 }, 1728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 }, 1738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 }, 1748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 }, 1758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 }, 1768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 }, 1778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 }, 1788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 }, 1798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 }, 1808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 }, 1818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 }, 1838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 }, 1848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 }, 1858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 }, 1868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 }, 1878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 }, 1888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 }, 1908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 }, 1918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 }, 1928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 }, 1938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 }, 1948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 }, 1958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 }, 1978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 }, 1988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 }, 1998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 }, 2008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 }, 2028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 }, 2038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 }, 2048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 }, 2058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 }, 2068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 }, 2078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 }, 2088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 }, 2098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 }, 2118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 }, 2128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 }, 2138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 }, 2148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 }, 2158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 }, 2168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4}, 2178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4}, 2188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2}, 2198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2}, 2208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 }, 2228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 }, 2238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 }, 2248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 }, 2258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 }, 2268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 }, 2278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 }, 2298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 }, 2308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 }, 2318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 }, 2328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 }, 2338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 }, 2348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 }, 2368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 }, 2378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 }, 2388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 }, 2398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 }, 2408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 }, 2418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4}, 2428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4}, 2438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2}, 2448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2}, 2458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 }, 2478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 }, 2488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 }, 2498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 }, 2508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 }, 2518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 }, 2528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 }, 2548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 }, 2558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 }, 2568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 }, 2578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 }, 2588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 }, 2598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 }, 2618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 }, 2628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 }, 2638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 }, 2648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 }, 2658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 }, 2668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4}, 2678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4}, 2688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2}, 2698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2}, 2708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 }, 2728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 }, 2738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 }, 2748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 }, 2758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 }, 2768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 }, 2778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 }, 2798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 }, 2808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 }, 2818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 }, 2828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 }, 2838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson{ ARM::VST4q8oddPseudo_UPD , ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 } 2848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson}; 2858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 2878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// load or store pseudo instruction. 2888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 2898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumEntries = array_lengthof(NEONLdStTable); 2908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 2918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#ifndef NDEBUG 2928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Make sure the table is sorted. 2938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson static bool TableChecked = false; 2948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableChecked) { 2958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson for (unsigned i = 0; i != NumEntries-1; ++i) 2968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(NEONLdStTable[i] < NEONLdStTable[i+1] && 2978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson "NEONLdStTable is not sorted!"); 2988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TableChecked = true; 2998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 3008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#endif 3018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *I = 3038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); 3048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) 3058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return I; 3068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return NULL; 3078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 3108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// corresponding to the specified register spacing. Not all of the results 3118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// are necessarily valid, e.g., a Q register only has 2 D subregisters. 3128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 3138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const TargetRegisterInfo *TRI, unsigned &D0, 3148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned &D1, unsigned &D2, unsigned &D3) { 3158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == SingleSpc) { 3168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_1); 3188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_2); 3198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_3); 3208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else if (RegSpc == EvenDblSpc) { 3218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_2); 3238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_4); 3248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_6); 3258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else { 3268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc == OddDblSpc && "unknown register spacing"); 3278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_1); 3288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_3); 3298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_5); 3308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_7); 331bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson } 3328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 33482a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 33582a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// operands to real VLD instructions with D register operands. 3368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 337ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineInstr &MI = *MBBI; 338ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 339ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 3408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 3418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 3428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 3438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 3448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 3468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 347ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned OpIdx = 0; 348ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 349ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 350ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 351ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned D0, D1, D2, D3; 3528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 353f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 354f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 355ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson if (NumRegs > 2) 356f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 357ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson if (NumRegs > 3) 358f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 359ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 3608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 36163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 36263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 363ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson // Copy the addrmode6 operands. 36463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 36563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 36663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 3678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 36863569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 369ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 370ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MIB = AddDefaultPred(MIB); 37119d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // For an instruction writing double-spaced subregs, the pseudo instruction 37219d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // has an extra operand that is a use of the super-register. Copy that over 37319d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // to the new instruction as an implicit operand. 37419d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) { 37519d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MachineOperand MO = MI.getOperand(OpIdx); 37619d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MO.setImplicit(true); 37719d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MIB.addOperand(MO); 37819d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson } 379f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson // Add an implicit def for the super-register. 380f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 38119d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson TransferImpOps(MI, MIB, MIB); 382ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MI.eraseFromParent(); 383ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson} 384ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 38501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 38601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// operands to real VST instructions with D register operands. 3878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 388709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineInstr &MI = *MBBI; 389709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 390709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 3918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 3928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 3938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 3948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 3958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 3978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 398709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned OpIdx = 0; 3998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 40063569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 402709d59255a3100c7d440c93069efa1f726677a27Bob Wilson // Copy the addrmode6 operands. 40363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40463569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 4068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 40763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 408709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 409709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 410709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx).getReg(); 411709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned D0, D1, D2, D3; 4128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 4137e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D0).addReg(D1); 414e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson if (NumRegs > 2) 4157e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D2); 41601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson if (NumRegs > 3) 4177e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson MIB.addReg(D3); 418709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MIB = AddDefaultPred(MIB); 4197e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson if (SrcIsKill) 4207e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson // Add an implicit kill for the super-reg. 4217e701979ad20796bc930b21de3888ccfa0d8b33dBob Wilson (*MIB).addRegisterKilled(SrcReg, TRI, true); 422bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 423709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MI.eraseFromParent(); 424709d59255a3100c7d440c93069efa1f726677a27Bob Wilson} 425709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 4278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// register operands to real instructions with D register operands. 4288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 4298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstr &MI = *MBBI; 4308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 4318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && "NEONLdStTable lookup failed"); 4348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson NEONRegSpacing RegSpc = TableEntry->RegSpacing; 4358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RegElts = TableEntry->RegElts; 4378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 4398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 4408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned OpIdx = 0; 4418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // The lane operand is always the 3rd from last operand, before the 2 4428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // predicate operands. 4438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 4448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Adjust the lane and spacing as needed for Q registers. 4468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 4478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == EvenDblSpc && Lane >= RegElts) { 4488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson RegSpc = OddDblSpc; 4498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson Lane -= RegElts; 4508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 4518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 4528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 453fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned D0, D1, D2, D3; 454fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned DstReg = 0; 455fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson bool DstIsDead = false; 4568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) { 4578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstIsDead = MI.getOperand(OpIdx).isDead(); 4588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstReg = MI.getOperand(OpIdx++).getReg(); 4598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 4608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 4618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 4628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 4638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 4648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 4658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 4668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 4678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 4698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 4708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the addrmode6 operands. 4728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 4738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 4748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the am6offset operand. 4758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->HasWriteBack) 4768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 4778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Grab the super-register source. 4798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineOperand MO = MI.getOperand(OpIdx++); 4808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableEntry->IsLoad) 4818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 4828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the subregs as sources of the new instruction. 4848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 4858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson getKillRegState(MO.isKill())); 4868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D0, SrcFlags).addReg(D1, SrcFlags); 4878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 4888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, SrcFlags); 4898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 4908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, SrcFlags); 4918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the lane number operand. 4938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addImm(Lane); 4948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB = AddDefaultPred(MIB); 4968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the super-register source to be an implicit source. 4978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MO.setImplicit(true); 4988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MO); 4998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) 5008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add an implicit def for the super-register. 5018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 5028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TransferImpOps(MI, MIB, MIB); 5038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MI.eraseFromParent(); 5048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 5058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 506bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 507bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// register operands to real instructions with D register operands. 508bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilsonvoid ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 509bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned Opc, bool IsExt, unsigned NumRegs) { 510bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstr &MI = *MBBI; 511bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 512bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 513bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 514bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned OpIdx = 0; 515bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 516bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Transfer the destination register operand. 517bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 518bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (IsExt) 519bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 520bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 521bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 522bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 523bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned D0, D1, D2, D3; 524bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 525bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D0).addReg(D1); 526bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (NumRegs > 2) 527bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D2); 528bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (NumRegs > 3) 529bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addReg(D3); 530bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 531bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Copy the other source register operand. 532bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx)); 533bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 534bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB = AddDefaultPred(MIB); 535bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (SrcIsKill) 536bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Add an implicit kill for the super-reg. 537bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson (*MIB).addRegisterKilled(SrcReg, TRI, true); 538bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 539bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MI.eraseFromParent(); 540bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson} 541bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 542b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 543b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 544b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 545b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 546b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng while (MBBI != E) { 547b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MachineInstr &MI = *MBBI; 5487896c9f436a4eda5ec15e882a7505ba482a2fcd0Chris Lattner MachineBasicBlock::iterator NMBBI = llvm::next(MBBI); 549b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 550709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool ModifiedOp = true; 551b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned Opcode = MI.getOpcode(); 552b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng switch (Opcode) { 553709d59255a3100c7d440c93069efa1f726677a27Bob Wilson default: 554709d59255a3100c7d440c93069efa1f726677a27Bob Wilson ModifiedOp = false; 555709d59255a3100c7d440c93069efa1f726677a27Bob Wilson break; 556709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 557bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::tLDRpci_pic: 558b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng case ARM::t2LDRpci_pic: { 559b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 560b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng ? ARM::tLDRpci : ARM::t2LDRpci; 561b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 562431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 563431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB1 = 564431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 565431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TII->get(NewLdOpc), DstReg) 566431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addOperand(MI.getOperand(1))); 567431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 568431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 569431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TII->get(ARM::tPICADD)) 570431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) 571431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg) 572431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addOperand(MI.getOperand(2)); 573431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, MIB1, MIB2); 574b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 575b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng break; 576b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 577431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 5786d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov case ARM::MOVi32imm: 579b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng case ARM::t2MOVi32imm: { 580431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned PredReg = 0; 581431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); 582b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 583431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 584431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const MachineOperand &MO = MI.getOperand(1); 585431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder LO16, HI16; 586431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 5876d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 5886d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov TII->get(Opcode == ARM::MOVi32imm ? 5896d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov ARM::MOVi16 : ARM::t2MOVi16), 590431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng DstReg); 5916d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 5926d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov TII->get(Opcode == ARM::MOVi32imm ? 5936d1e29d2f203093e3e03f15173c0f36637d3afe3Anton Korobeynikov ARM::MOVTi16 : ARM::t2MOVTi16)) 594431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) 595431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg); 596431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 597431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isImm()) { 598431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned Imm = MO.getImm(); 599431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned Lo16 = Imm & 0xffff; 600431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned Hi16 = (Imm >> 16) & 0xffff; 601431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng LO16 = LO16.addImm(Lo16); 602431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng HI16 = HI16.addImm(Hi16); 603431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } else { 604431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const GlobalValue *GV = MO.getGlobal(); 605431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng unsigned TF = MO.getTargetFlags(); 606431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 607431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 608b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 609431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng (*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 610431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng (*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 611431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng LO16.addImm(Pred).addReg(PredReg); 612431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng HI16.addImm(Pred).addReg(PredReg); 613431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, LO16, HI16); 614b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 615d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng break; 616d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng } 617d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng 618d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng case ARM::VMOVQQ: { 619d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 620d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 621558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0); 622558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1); 623d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng unsigned SrcReg = MI.getOperand(1).getReg(); 624d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng bool SrcIsKill = MI.getOperand(1).isKill(); 625558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0); 626558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1); 627d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MachineInstrBuilder Even = 628d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 629d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TII->get(ARM::VMOVQ)) 63018f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(EvenDst, 63118f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach getDefRegState(true) | getDeadRegState(DstIsDead)) 63218f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(EvenSrc, getKillRegState(SrcIsKill))); 633d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MachineInstrBuilder Odd = 634d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 635d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TII->get(ARM::VMOVQ)) 63618f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(OddDst, 63718f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach getDefRegState(true) | getDeadRegState(DstIsDead)) 63818f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach .addReg(OddSrc, getKillRegState(SrcIsKill))); 639d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TransferImpOps(MI, Even, Odd); 640d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng MI.eraseFromParent(); 641b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 642709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 643ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q8Pseudo: 644ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q16Pseudo: 645ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q32Pseudo: 646ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q64Pseudo: 647ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q8Pseudo_UPD: 648ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q16Pseudo_UPD: 649ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q32Pseudo_UPD: 650ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1q64Pseudo_UPD: 651ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d8Pseudo: 652ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d16Pseudo: 653ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d32Pseudo: 654ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo: 655ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo: 656ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo: 657ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d8Pseudo_UPD: 658ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d16Pseudo_UPD: 659ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2d32Pseudo_UPD: 660ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo_UPD: 661ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo_UPD: 662ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo_UPD: 663f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo: 664f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo: 665f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo: 666ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo: 667f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo_UPD: 668f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo_UPD: 669f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo_UPD: 670ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo_UPD: 671f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8Pseudo_UPD: 672f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16Pseudo_UPD: 673f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32Pseudo_UPD: 674f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8oddPseudo_UPD: 675f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16oddPseudo_UPD: 676f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32oddPseudo_UPD: 677f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo: 678f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo: 679f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo: 680ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo: 681f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo_UPD: 682f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo_UPD: 683f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo_UPD: 684ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo_UPD: 685f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8Pseudo_UPD: 686f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16Pseudo_UPD: 687f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32Pseudo_UPD: 688f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8oddPseudo_UPD: 689f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16oddPseudo_UPD: 690f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32oddPseudo_UPD: 6918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVLD(MBBI); 6928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson break; 693ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 694e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q8Pseudo: 695e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q16Pseudo: 696e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q32Pseudo: 697e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q64Pseudo: 698e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q8Pseudo_UPD: 699e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q16Pseudo_UPD: 700e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q32Pseudo_UPD: 701e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST1q64Pseudo_UPD: 702e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d8Pseudo: 703e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d16Pseudo: 704e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d32Pseudo: 705e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo: 706e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo: 707e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo: 708e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d8Pseudo_UPD: 709e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d16Pseudo_UPD: 710e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2d32Pseudo_UPD: 711e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo_UPD: 712e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo_UPD: 713e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo_UPD: 71401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo: 71501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo: 71601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo: 71701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo: 71801ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo_UPD: 71901ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo_UPD: 72001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo_UPD: 72101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo_UPD: 72201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8Pseudo_UPD: 72301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16Pseudo_UPD: 72401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32Pseudo_UPD: 72501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8oddPseudo_UPD: 72601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16oddPseudo_UPD: 72701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32oddPseudo_UPD: 728709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo: 729709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo: 730709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo: 73170e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo: 732709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo_UPD: 733709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo_UPD: 734709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo_UPD: 73570e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo_UPD: 736709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8Pseudo_UPD: 737709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16Pseudo_UPD: 738709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32Pseudo_UPD: 739709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8oddPseudo_UPD: 740709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16oddPseudo_UPD: 741709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32oddPseudo_UPD: 7428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVST(MBBI); 7438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson break; 7448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 7458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo: 7468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo: 7478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo: 7488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo: 7498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo: 7508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo_UPD: 7518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo_UPD: 7528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo_UPD: 7538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo_UPD: 7548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo_UPD: 7558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo: 7568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo: 7578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo: 7588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo: 7598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo: 7608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo_UPD: 7618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo_UPD: 7628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo_UPD: 7638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo_UPD: 7648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo_UPD: 7658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo: 7668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo: 7678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo: 7688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo: 7698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo: 7708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo_UPD: 7718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo_UPD: 7728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo_UPD: 7738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo_UPD: 7748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo_UPD: 7758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo: 7768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo: 7778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo: 7788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo: 7798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo: 7808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo_UPD: 7818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo_UPD: 7828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo_UPD: 7838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo_UPD: 7848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo_UPD: 7858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo: 7868466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo: 7878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo: 7888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo: 7898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo: 7908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo_UPD: 7918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo_UPD: 7928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo_UPD: 7938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo_UPD: 7948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo_UPD: 7958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo: 7968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo: 7978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo: 7988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo: 7998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo: 8008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo_UPD: 8018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo_UPD: 8028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo_UPD: 8038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo_UPD: 8048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo_UPD: 8058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandLaneOp(MBBI); 8068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson break; 807bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 808bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::VTBL2Pseudo: 809bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break; 810bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::VTBL3Pseudo: 811bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break; 812bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::VTBL4Pseudo: 813bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break; 814bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::VTBX2Pseudo: 815bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break; 816bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::VTBX3Pseudo: 817bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break; 818bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::VTBX4Pseudo: 819bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break; 820b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 821709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 822709d59255a3100c7d440c93069efa1f726677a27Bob Wilson if (ModifiedOp) 823709d59255a3100c7d440c93069efa1f726677a27Bob Wilson Modified = true; 824b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MBBI = NMBBI; 825b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 826b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 827b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 828b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 829b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 830b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 831b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng TII = MF.getTarget().getInstrInfo(); 832d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng TRI = MF.getTarget().getRegisterInfo(); 833b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 834b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 835b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 836b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng ++MFI) 837b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng Modified |= ExpandMBB(*MFI); 838b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 839b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 840b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 841b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// createARMExpandPseudoPass - returns an instance of the pseudo instruction 842b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// expansion pass. 843b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan ChengFunctionPass *llvm::createARMExpandPseudoPass() { 844b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return new ARMExpandPseudo(); 845b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 846