1cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar//===--- HexagonExpandCondsets.cpp ----------------------------------------===// 2cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// 3cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// The LLVM Compiler Infrastructure 4cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// 5cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// This file is distributed under the University of Illinois Open Source 6cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// License. See LICENSE.TXT for details. 7cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// 8cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar//===----------------------------------------------------------------------===// 9cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Replace mux instructions with the corresponding legal instructions. 110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// It is meant to work post-SSA, but still on virtual registers. It was 120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// originally placed between register coalescing and machine instruction 130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// scheduler. 140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// In this place in the optimization sequence, live interval analysis had 150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// been performed, and the live intervals should be preserved. A large part 160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// of the code deals with preserving the liveness information. 170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Liveness tracking aside, the main functionality of this pass is divided 190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// into two steps. The first step is to replace an instruction 200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg0 = C2_mux vreg0, vreg1, vreg2 210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// with a pair of conditional transfers 220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg0 = A2_tfrt vreg0, vreg1 230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg0 = A2_tfrf vreg0, vreg2 240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// It is the intention that the execution of this pass could be terminated 250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// after this step, and the code generated would be functionally correct. 260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// If the uses of the source values vreg1 and vreg2 are kills, and their 280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// definitions are predicable, then in the second step, the conditional 290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// transfers will then be rewritten as predicated instructions. E.g. 300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg0 = A2_or vreg1, vreg2 310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_tfrt vreg99, vreg0<kill> 320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// will be rewritten as 330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_port vreg99, vreg1, vreg2 340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// This replacement has two variants: "up" and "down". Consider this case: 360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg0 = A2_or vreg1, vreg2 370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// ... [intervening instructions] ... 380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_tfrt vreg99, vreg0<kill> 390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// variant "up": 400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_port vreg99, vreg1, vreg2 410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// ... [intervening instructions, vreg0->vreg3] ... 420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// [deleted] 430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// variant "down": 440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// [deleted] 450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// ... [intervening instructions] ... 460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_port vreg99, vreg1, vreg2 470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Both, one or none of these variants may be valid, and checks are made 490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// to rule out inapplicable variants. 500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// As an additional optimization, before either of the two steps above is 520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// executed, the pass attempts to coalesce the target register with one of 530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// the source registers, e.g. given an instruction 540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = C2_mux vreg0, vreg1, vreg2 550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds, 560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// the instruction would then be (for example) 570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = C2_mux vreg0, vreg3, vreg2 580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// and, under certain circumstances, this could result in only one predicated 590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// instruction: 600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_tfrf vreg0, vreg2 610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#define DEBUG_TYPE "expand-condsets" 640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "HexagonTargetMachine.h" 650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/Passes.h" 670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/LiveInterval.h" 680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/LiveIntervalAnalysis.h" 690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/MachineFunction.h" 700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/MachineInstrBuilder.h" 710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/MachineRegisterInfo.h" 720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Target/TargetInstrInfo.h" 730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Target/TargetMachine.h" 740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Target/TargetRegisterInfo.h" 750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Support/CommandLine.h" 760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Support/Debug.h" 770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Support/raw_ostream.h" 780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarusing namespace llvm; 800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarstatic cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit", 820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions")); 830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarstatic cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit", 840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings")); 850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarnamespace llvm { 870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void initializeHexagonExpandCondsetsPass(PassRegistry&); 880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar FunctionPass *createHexagonExpandCondsets(); 890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarnamespace { 920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar class HexagonExpandCondsets : public MachineFunctionPass { 930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar public: 940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar static char ID; 950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar HexagonExpandCondsets() : 960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineFunctionPass(ID), HII(0), TRI(0), MRI(0), 970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS(0), CoaLimitActive(false), 980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TfrLimitActive(false), CoaCounter(0), TfrCounter(0) { 990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (OptCoaLimit.getPosition()) 1000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar CoaLimitActive = true, CoaLimit = OptCoaLimit; 1010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (OptTfrLimit.getPosition()) 1020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TfrLimitActive = true, TfrLimit = OptTfrLimit; 1030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); 1040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 1050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar virtual const char *getPassName() const { 1070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return "Hexagon Expand Condsets"; 1080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 1090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar virtual void getAnalysisUsage(AnalysisUsage &AU) const { 1100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar AU.addRequired<LiveIntervals>(); 1110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar AU.addPreserved<LiveIntervals>(); 1120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar AU.addPreserved<SlotIndexes>(); 1130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineFunctionPass::getAnalysisUsage(AU); 1140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 1150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar virtual bool runOnMachineFunction(MachineFunction &MF); 1160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar private: 1180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const HexagonInstrInfo *HII; 1190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterInfo *TRI; 1200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineRegisterInfo *MRI; 1210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveIntervals *LIS; 1220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool CoaLimitActive, TfrLimitActive; 1240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter; 1250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar struct RegisterRef { 1270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()), 1280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Sub(Op.getSubReg()) {} 1290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} 1300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool operator== (RegisterRef RR) const { 1310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Reg == RR.Reg && Sub == RR.Sub; 1320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 1330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool operator!= (RegisterRef RR) const { return !operator==(RR); } 1340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Reg, Sub; 1350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar }; 1360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar typedef DenseMap<unsigned,unsigned> ReferenceMap; 1380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) }; 1390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar enum { Exec_Then = 0x10, Exec_Else = 0x20 }; 1400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned getMaskForSub(unsigned Sub); 1410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isCondset(const MachineInstr *MI); 1420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec); 1440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec); 1450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator nextSegment(LiveInterval &LI, SlotIndex S); 1470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator prevSegment(LiveInterval &LI, SlotIndex S); 1480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void makeDefined(unsigned Reg, SlotIndex S, bool SetDef); 1490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void makeUndead(unsigned Reg, SlotIndex S); 1500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void shrinkToUses(unsigned Reg, LiveInterval &LI); 1510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void updateKillFlags(unsigned Reg, LiveInterval &LI); 1520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void terminateSegment(LiveInterval::iterator LT, SlotIndex S, 1530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &LI); 1540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void addInstrToLiveness(MachineInstr *MI); 1550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void removeInstrFromLiveness(MachineInstr *MI); 1560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond); 1580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR, 1590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned DstSR, const MachineOperand &PredOp, bool Cond); 1600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool split(MachineInstr *MI); 1610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool splitInBlock(MachineBasicBlock &B); 1620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isPredicable(MachineInstr *MI); 1640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *getReachingDefForPred(RegisterRef RD, 1650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond); 1660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool canMoveOver(MachineInstr *MI, ReferenceMap &Defs, ReferenceMap &Uses); 1670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool canMoveMemTo(MachineInstr *MI, MachineInstr *ToI, bool IsDown); 1680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void predicateAt(RegisterRef RD, MachineInstr *MI, 1690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator Where, unsigned PredR, bool Cond); 1700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR, 1710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Cond, MachineBasicBlock::iterator First, 1720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator Last); 1730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool predicate(MachineInstr *TfrI, bool Cond); 1740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool predicateInBlock(MachineBasicBlock &B); 1750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void postprocessUndefImplicitUses(MachineBasicBlock &B); 1770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void removeImplicitUses(MachineInstr *MI); 1780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void removeImplicitUses(MachineBasicBlock &B); 1790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isIntReg(RegisterRef RR, unsigned &BW); 1810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isIntraBlocks(LiveInterval &LI); 1820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool coalesceRegisters(RegisterRef R1, RegisterRef R2); 1830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool coalesceSegments(MachineFunction &MF); 1840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar }; 1850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 1860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarchar HexagonExpandCondsets::ID = 0; 1880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarunsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) { 1910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar switch (Sub) { 1920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::subreg_loreg: 1930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Sub_Low; 1940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::subreg_hireg: 1950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Sub_High; 1960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::NoSubRegister: 1970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Sub_None; 1980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 1990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar llvm_unreachable("Invalid subregister"); 2000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isCondset(const MachineInstr *MI) { 2040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Opc = MI->getOpcode(); 2050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar switch (Opc) { 2060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_mux: 2070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_muxii: 2080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_muxir: 2090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_muxri: 2100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::MUX64_rr: 2110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 2120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 2130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 2140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 2150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, 2190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Exec) { 2200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Mask = getMaskForSub(RR.Sub) | Exec; 2210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap::iterator F = Map.find(RR.Reg); 2220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (F == Map.end()) 2230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Map.insert(std::make_pair(RR.Reg, Mask)); 2240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else 2250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar F->second |= Mask; 2260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map, 2300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Exec) { 2310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap::iterator F = Map.find(RR.Reg); 2320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (F == Map.end()) 2330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 2340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Mask = getMaskForSub(RR.Sub) | Exec; 2350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Mask & F->second) 2360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 2370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 2380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga NainarLiveInterval::iterator HexagonExpandCondsets::nextSegment(LiveInterval &LI, 2420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex S) { 2430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 2440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (I->start >= S) 2450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return I; 2460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 2470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return LI.end(); 2480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga NainarLiveInterval::iterator HexagonExpandCondsets::prevSegment(LiveInterval &LI, 2520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex S) { 2530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator P = LI.end(); 2540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 2550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (I->end > S) 2560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return P; 2570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar P = I; 2580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 2590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return P; 2600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Find the implicit use of register Reg in slot index S, and make sure 2640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// that the "defined" flag is set to SetDef. While the mux expansion is 2650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// going on, predicated instructions will have implicit uses of the 2660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// registers that are being defined. This is to keep any preceding 2670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// definitions live. If there is no preceding definition, the implicit 2680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// use will be marked as "undef", otherwise it will be "defined". This 2690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// function is used to update the flag. 2700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::makeDefined(unsigned Reg, SlotIndex S, 2710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool SetDef) { 2720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!S.isRegister()) 2730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return; 2740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = LIS->getInstructionFromIndex(S); 2750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(MI && "Expecting instruction"); 2760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 2770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) 2780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 2790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool IsDef = !Op.isUndef(); 2800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Op.isImplicit() && IsDef != SetDef) 2810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setIsUndef(!SetDef); 2820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 2830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::makeUndead(unsigned Reg, SlotIndex S) { 2870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If S is a block boundary, then there can still be a dead def reaching 2880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // this point. Instead of traversing the CFG, queue start points of all 2890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // live segments that begin with a register, and end at a block boundary. 2900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // This may "resurrect" some truly dead definitions, but doing so is 2910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // harmless. 2920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SmallVector<MachineInstr*,8> Defs; 2930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (S.isBlock()) { 2940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &LI = LIS->getInterval(Reg); 2950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 2960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!I->start.isRegister() || !I->end.isBlock()) 2970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 2980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = LIS->getInstructionFromIndex(I->start); 2990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Defs.push_back(MI); 3000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else if (S.isRegister()) { 3020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = LIS->getInstructionFromIndex(S); 3030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Defs.push_back(MI); 3040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0, n = Defs.size(); i < n; ++i) { 3070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = Defs[i]; 3080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 3090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg) 3100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 3110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setIsDead(false); 3120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Shrink the segments in the live interval for a given register to the last 3180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// use before each subsequent def. Unlike LiveIntervals::shrinkToUses, this 3190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// function will not mark any definitions of Reg as dead. The reason for this 3200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// is that this function is used while a MUX instruction is being expanded, 3210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// or while a conditional copy is undergoing predication. During these 3220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// processes, there may be defs present in the instruction sequence that have 3230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// not yet been removed, or there may be missing uses that have not yet been 3240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// added. We want to utilize LiveIntervals::shrinkToUses as much as possible, 3250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// but since it does not extend any intervals that are too short, we need to 3260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// pre-emptively extend them here in anticipation of further changes. 3270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::shrinkToUses(unsigned Reg, LiveInterval &LI) { 3280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SmallVector<MachineInstr*,4> Deads; 3290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS->shrinkToUses(&LI, &Deads); 3300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Need to undo the deadification made by "shrinkToUses". It's easier to 3310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // do it here, since we have a list of all instructions that were just 3320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // marked as dead. 3330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0, n = Deads.size(); i < n; ++i) { 3340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = Deads[i]; 3350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Clear the "dead" flag. 3360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 3370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg) 3380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 3390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setIsDead(false); 3400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Extend the live segment to the beginning of the next one. 3420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator End = LI.end(); 3430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex S = LIS->getInstructionIndex(MI).getRegSlot(); 3440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator T = LI.FindSegmentContaining(S); 3450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(T != End); 3460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator N = std::next(T); 3470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (N != End) 3480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar T->end = N->start; 3490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else 3500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar T->end = LIS->getMBBEndIdx(MI->getParent()); 3510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar updateKillFlags(Reg, LI); 3530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Given an updated live interval LI for register Reg, update the kill flags 3570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// in instructions using Reg to reflect the liveness changes. 3580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::updateKillFlags(unsigned Reg, LiveInterval &LI) { 3590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MRI->clearKillFlags(Reg); 3600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 3610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex EX = I->end; 3620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!EX.isRegister()) 3630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 3640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = LIS->getInstructionFromIndex(EX); 3650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 3660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) 3670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 3680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Only set the kill flag on the first encountered use of Reg in this 3690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // instruction. 3700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setIsKill(true); 3710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 3720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// When adding a new instruction to liveness, the newly added definition 3780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// will start a new live segment. This may happen at a position that falls 3790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// within an existing live segment. In such case that live segment needs to 3800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// be truncated to make room for the new segment. Ultimately, the truncation 3810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// will occur at the last use, but for now the segment can be terminated 3820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// right at the place where the new segment will start. The segments will be 3830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// shrunk-to-uses later. 3840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::terminateSegment(LiveInterval::iterator LT, 3850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex S, LiveInterval &LI) { 3860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Terminate the live segment pointed to by LT within a live interval LI. 3870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (LT == LI.end()) 3880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return; 3890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VNInfo *OldVN = LT->valno; 3910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex EX = LT->end; 3920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LT->end = S; 3930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If LT does not end at a block boundary, the termination is done. 3940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!EX.isBlock()) 3950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return; 3960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If LT ended at a block boundary, it's possible that its value number 3980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // is picked up at the beginning other blocks. Create a new value number 3990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and change such blocks to use it instead. 4000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VNInfo *NewVN = 0; 4010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 4020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!I->start.isBlock() || I->valno != OldVN) 4030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 4040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Generate on-demand a new value number that is defined by the 4050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // block beginning (i.e. -phi). 4060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!NewVN) 4070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NewVN = LI.getNextValue(I->start, LIS->getVNInfoAllocator()); 4080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar I->valno = NewVN; 4090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 4100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 4110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Add the specified instruction to live intervals. This function is used 4140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// to update the live intervals while the program code is being changed. 4150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Neither the expansion of a MUX, nor the predication are atomic, and this 4160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// function is used to update the live intervals while these transformations 4170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// are being done. 4180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::addInstrToLiveness(MachineInstr *MI) { 4190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex MX = LIS->isNotInMIMap(MI) ? LIS->InsertMachineInstrInMaps(MI) 4200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar : LIS->getInstructionIndex(MI); 4210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "adding liveness info for instr\n " << MX << " " << *MI); 4220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MX = MX.getRegSlot(); 4240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Predicated = HII->isPredicated(MI); 4250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock *MB = MI->getParent(); 4260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Strip all implicit uses from predicated instructions. They will be 4280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // added again, according to the updated information. 4290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Predicated) 4300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar removeImplicitUses(MI); 4310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For each def in MI we need to insert a new live segment starting at MX 4330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // into the interval. If there already exists a live segment in the interval 4340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // that contains MX, we need to terminate it at MX. 4350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SmallVector<RegisterRef,2> Defs; 4360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) 4370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Op.isReg() && Op.isDef()) 4380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Defs.push_back(RegisterRef(Op)); 4390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0, n = Defs.size(); i < n; ++i) { 4410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned DefR = Defs[i].Reg; 4420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &LID = LIS->getInterval(DefR); 4430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "adding def " << PrintReg(DefR, TRI) 4440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << " with interval\n " << LID << "\n"); 4450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If MX falls inside of an existing live segment, terminate it. 4460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator LT = LID.FindSegmentContaining(MX); 4470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (LT != LID.end()) 4480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar terminateSegment(LT, MX, LID); 4490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "after terminating segment\n " << LID << "\n"); 4500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Create a new segment starting from MX. 4520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator P = prevSegment(LID, MX), N = nextSegment(LID, MX); 4530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex EX; 4540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VNInfo *VN = LID.getNextValue(MX, LIS->getVNInfoAllocator()); 4550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (N == LID.end()) { 4560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // There is no live segment after MX. End this segment at the end of 4570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the block. 4580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar EX = LIS->getMBBEndIdx(MB); 4590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 4600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the next segment starts at the block boundary, end the new segment 4610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // at the boundary of the preceding block (i.e. the previous index). 4620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Otherwise, end the segment at the beginning of the next segment. In 4630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // either case it will be "shrunk-to-uses" later. 4640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar EX = N->start.isBlock() ? N->start.getPrevIndex() : N->start; 4650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 4660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Predicated) { 4670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Predicated instruction will have an implicit use of the defined 4680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // register. This is necessary so that this definition will not make 4690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // any previous definitions dead. If there are no previous live 4700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // segments, still add the implicit use, but make it "undef". 4710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Because of the implicit use, the preceding definition is not 4720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // dead. Mark is as such (if necessary). 4730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand ImpUse = MachineOperand::CreateReg(DefR, false, true); 4740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ImpUse.setSubReg(Defs[i].Sub); 4750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Undef = false; 4760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (P == LID.end()) 4770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Undef = true; 4780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else { 4790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the previous segment extends to the end of the previous block, 4800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the end index may actually be the beginning of this block. If 4810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the previous segment ends at a block boundary, move it back by one, 4820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // to get the proper block for it. 4830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end; 4840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock *PB = LIS->getMBBFromIndex(PE); 4850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (PB != MB && !LIS->isLiveInToMBB(LID, MB)) 4860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Undef = true; 4870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 4880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Undef) { 4890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar makeUndead(DefR, P->valno->def); 4900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We are adding a live use, so extend the previous segment to 4910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // include it. 4920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar P->end = MX; 4930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 4940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ImpUse.setIsUndef(true); 4950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 4960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 4970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MI->readsRegister(DefR)) 4980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MI->addOperand(ImpUse); 4990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (N != LID.end()) 5000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar makeDefined(DefR, N->start, true); 5010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveRange::Segment NR = LiveRange::Segment(MX, EX, VN); 5030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LID.addSegment(NR); 5040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "added a new segment " << NR << "\n " << LID << "\n"); 5050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar shrinkToUses(DefR, LID); 5060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "updated imp-uses: " << *MI); 5070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LID.verify(); 5080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For each use in MI: 5110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // - If there is no live segment that contains MX for the used register, 5120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // extend the previous one. Ignore implicit uses. 5130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 5140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef()) 5150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 5160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned UseR = Op.getReg(); 5170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &LIU = LIS->getInterval(UseR); 5180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Find the last segment P that starts before MX. 5190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator P = LIU.FindSegmentContaining(MX); 5200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (P == LIU.end()) 5210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar P = prevSegment(LIU, MX); 5220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(P != LIU.end() && "MI uses undefined register?"); 5240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex EX = P->end; 5250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If P contains MX, there is not much to do. 5260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (EX > MX) { 5270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setIsKill(false); 5280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 5290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Otherwise, extend P to "next(MX)". 5310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar P->end = MX.getNextIndex(); 5320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setIsKill(true); 5330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Get the old "kill" instruction, and remove the kill flag. 5340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MachineInstr *KI = LIS->getInstructionFromIndex(MX)) 5350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar KI->clearRegisterKills(UseR, nullptr); 5360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar shrinkToUses(UseR, LIU); 5370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIU.verify(); 5380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 5400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Update the live interval information to reflect the removal of the given 5430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// instruction from the program. As with "addInstrToLiveness", this function 5440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// is called while the program code is being changed. 5450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::removeInstrFromLiveness(MachineInstr *MI) { 5460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex MX = LIS->getInstructionIndex(MI).getRegSlot(); 5470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "removing instr\n " << MX << " " << *MI); 5480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For each def in MI: 5500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If MI starts a live segment, merge this segment with the previous segment. 5510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // 5520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 5530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef()) 5540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 5550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned DefR = Op.getReg(); 5560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &LID = LIS->getInterval(DefR); 5570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator LT = LID.FindSegmentContaining(MX); 5580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(LT != LID.end() && "Expecting live segments"); 5590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "removing def at " << MX << " of " << PrintReg(DefR, TRI) 5600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << " with interval\n " << LID << "\n"); 5610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (LT->start != MX) 5620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 5630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VNInfo *MVN = LT->valno; 5650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (LT != LID.begin()) { 5660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the current live segment is not the first, the task is easy. If 5670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the previous segment continues into the current block, extend it to 5680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the end of the current one, and merge the value numbers. 5690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Otherwise, remove the current segment, and make the end of it "undef". 5700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator P = std::prev(LT); 5710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end; 5720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock *MB = MI->getParent(); 5730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock *PB = LIS->getMBBFromIndex(PE); 5740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (PB != MB && !LIS->isLiveInToMBB(LID, MB)) { 5750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar makeDefined(DefR, LT->end, false); 5760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LID.removeSegment(*LT); 5770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 5780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Make the segments adjacent, so that merge-vn can also merge the 5790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // segments. 5800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar P->end = LT->start; 5810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar makeUndead(DefR, P->valno->def); 5820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LID.MergeValueNumberInto(MVN, P->valno); 5830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 5850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator N = std::next(LT); 5860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator RmB = LT, RmE = N; 5870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar while (N != LID.end()) { 5880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Iterate until the first register-based definition is found 5890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // (i.e. skip all block-boundary entries). 5900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval::iterator Next = std::next(N); 5910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (N->start.isRegister()) { 5920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar makeDefined(DefR, N->start, false); 5930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 5940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (N->end.isRegister()) { 5960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar makeDefined(DefR, N->end, false); 5970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RmE = Next; 5980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 5990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RmE = Next; 6010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar N = Next; 6020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Erase the segments in one shot to avoid invalidating iterators. 6040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LID.segments.erase(RmB, RmE); 6050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool VNUsed = false; 6080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LID.begin(), E = LID.end(); I != E; ++I) { 6090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (I->valno != MVN) 6100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 6110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VNUsed = true; 6120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 6130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!VNUsed) 6150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MVN->markUnused(); 6160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "new interval: "); 6180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!LID.empty()) { 6190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << LID << "\n"); 6200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LID.verify(); 6210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 6220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "<empty>\n"); 6230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS->removeInterval(DefR); 6240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For uses there is nothing to do. The intervals will be updated via 6280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // shrinkToUses. 6290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SmallVector<unsigned,4> Uses; 6300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 6310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isUse()) 6320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 6330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned R = Op.getReg(); 6340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(R)) 6350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 6360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Uses.push_back(R); 6370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS->RemoveMachineInstrFromMaps(MI); 6390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MI->eraseFromParent(); 6400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0, n = Uses.size(); i < n; ++i) { 6410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &LI = LIS->getInterval(Uses[i]); 6420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar shrinkToUses(Uses[i], LI); 6430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 6450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Get the opcode for a conditional transfer of the value in SO (source 6480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// operand). The condition (true/false) is given in Cond. 6490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarunsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO, 6500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Cond) { 6510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar using namespace Hexagon; 6520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (SO.isReg()) { 6530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PhysR; 6540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RS = SO; 6550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) { 6560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg); 6570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(VC->begin() != VC->end() && "Empty register class"); 6580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PhysR = *VC->begin(); 6590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 6600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg)); 6610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PhysR = RS.Reg; 6620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); 6640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); 6650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar switch (RC->getSize()) { 6660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case 4: 6670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Cond ? A2_tfrt : A2_tfrf; 6680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case 8: 6690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Cond ? A2_tfrpt : A2_tfrpf; 6700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar llvm_unreachable("Invalid register operand"); 6720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (SO.isImm() || SO.isFPImm()) 6740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Cond ? C2_cmoveit : C2_cmoveif; 6750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar llvm_unreachable("Unexpected source operand"); 6760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 6770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Generate a conditional transfer, copying the value SrcOp to the 6800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// destination register DstR:DstSR, and using the predicate register from 6810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// PredOp. The Cond argument specifies whether the predicate is to be 6820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// if(PredOp), or if(!PredOp). 6830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga NainarMachineInstr *HexagonExpandCondsets::genTfrFor(MachineOperand &SrcOp, 6840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool Cond) { 6850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = SrcOp.getParent(); 6860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock &B = *MI->getParent(); 6870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator At = MI; 6880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DebugLoc DL = MI->getDebugLoc(); 6890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Don't avoid identity copies here (i.e. if the source and the destination 6910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // are the same registers). It is actually better to generate them here, 6920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // since this would cause the copy to potentially be predicated in the next 6930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // step. The predication will remove such a copy if it is unable to 6940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar /// predicate. 6950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Opc = getCondTfrOpcode(SrcOp, Cond); 6970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *TfrI = BuildMI(B, At, DL, HII->get(Opc)) 6980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar .addReg(DstR, RegState::Define, DstSR) 6990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar .addOperand(PredOp) 7000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar .addOperand(SrcOp); 7010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We don't want any kills yet. 7020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TfrI->clearKillInfo(); 7030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "created an initial copy: " << *TfrI); 7040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return TfrI; 7050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function 7090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// performs all necessary changes to complete the replacement. 7100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::split(MachineInstr *MI) { 7110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TfrLimitActive) { 7120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TfrCounter >= TfrLimit) 7130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TfrCounter++; 7150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "\nsplitting BB#" << MI->getParent()->getNumber() 7170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << ": " << *MI); 7180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MD = MI->getOperand(0); // Definition 7190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MP = MI->getOperand(1); // Predicate register 7200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(MD.isDef()); 7210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned DR = MD.getReg(), DSR = MD.getSubReg(); 7220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // First, create the two invididual conditional transfers, and add each 7240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // of them to the live intervals information. Do that first and then remove 7250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the old instruction from live intervals. 7260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MachineInstr *TfrT = genTfrFor(MI->getOperand(2), DR, DSR, MP, true)) 7270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar addInstrToLiveness(TfrT); 7280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MachineInstr *TfrF = genTfrFor(MI->getOperand(3), DR, DSR, MP, false)) 7290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar addInstrToLiveness(TfrF); 7300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar removeInstrFromLiveness(MI); 7310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 7330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Split all MUX instructions in the given block into pairs of contitional 7370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// transfers. 7380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B) { 7390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 7400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator I, E, NextI; 7410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (I = B.begin(), E = B.end(); I != E; I = NextI) { 7420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NextI = std::next(I); 7430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (isCondset(I)) 7440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= split(I); 7450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 7470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { 7510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (HII->isPredicated(MI) || !HII->isPredicable(MI)) 7520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MI->hasUnmodeledSideEffects() || MI->mayStore()) 7540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Reject instructions with multiple defs (e.g. post-increment loads). 7560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool HasDef = false; 7570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 7580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef()) 7590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (HasDef) 7610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar HasDef = true; 7630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Mo : MI->memoperands()) 7650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Mo->isVolatile()) 7660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 7680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Find the reaching definition for a predicated use of RD. The RD is used 7720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// under the conditions given by PredR and Cond, and this function will ignore 7730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// definitions that set RD under the opposite conditions. 7740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga NainarMachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD, 7750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { 7760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock &B = *UseIt->getParent(); 7770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator I = UseIt, S = B.begin(); 7780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (I == S) 7790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return 0; 7800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool PredValid = true; 7820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar do { 7830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar --I; 7840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 7850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Check if this instruction can be ignored, i.e. if it is predicated 7860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // on the complementary condition. 7870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (PredValid && HII->isPredicated(MI)) { 7880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI))) 7890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Check the defs. If the PredR is defined, invalidate it. If RD is 7930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // defined, return the instruction or 0, depending on the circumstances. 7940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 7950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef()) 7960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RR = Op; 7980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Reg == PredR) { 7990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PredValid = false; 8000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 8010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Reg != RD.Reg) 8030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 8040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the "Reg" part agrees, there is still the subregister to check. 8050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but 8060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // not vreg1 (w/o subregisters). 8070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Sub == RD.Sub) 8080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return MI; 8090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Sub == 0 || RD.Sub == 0) 8100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return 0; 8110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We have different subregisters, so we can continue looking. 8120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } while (I != S); 8140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return 0; 8160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 8170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Check if the instruction MI can be safely moved over a set of instructions 8200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// whose side-effects (in terms of register defs and uses) are expressed in 8210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the maps Defs and Uses. These maps reflect the conditional defs and uses 8220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// that depend on the same predicate register to allow moving instructions 8230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// over instructions predicated on the opposite condition. 8240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::canMoveOver(MachineInstr *MI, ReferenceMap &Defs, 8250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap &Uses) { 8260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // In order to be able to safely move MI over instructions that define 8270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // "Defs" and use "Uses", no def operand from MI can be defined or used 8280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and no use operand can be defined. 8290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 8300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg()) 8310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 8320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RR = Op; 8330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For physical register we would need to check register aliases, etc. 8340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and we don't want to bother with that. It would be of little value 8350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // before the actual register rewriting (from virtual to physical). 8360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(RR.Reg)) 8370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // No redefs for any operand. 8390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (isRefInMap(RR, Defs, Exec_Then)) 8400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For defs, there cannot be uses. 8420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) 8430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 8460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 8470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Check if the instruction accessing memory (TheI) can be moved to the 8500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// location ToI. 8510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::canMoveMemTo(MachineInstr *TheI, MachineInstr *ToI, 8520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool IsDown) { 8530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore(); 8540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!IsLoad && !IsStore) 8550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 8560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI)) 8570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 8580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TheI->hasUnmodeledSideEffects()) 8590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI; 8620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI; 8630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Ordered = TheI->hasOrderedMemoryRef(); 8640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Search for aliased memory reference in (StartI, EndI). 8660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) { 8670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 8680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MI->hasUnmodeledSideEffects()) 8690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool L = MI->mayLoad(), S = MI->mayStore(); 8710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!L && !S) 8720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 8730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Ordered && MI->hasOrderedMemoryRef()) 8740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Conflict = (L && IsStore) || S; 8770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Conflict) 8780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 8810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 8820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Generate a predicated version of MI (where the condition is given via 8850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// PredR and Cond) at the point indicated by Where. 8860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::predicateAt(RegisterRef RD, MachineInstr *MI, 8870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator Where, unsigned PredR, bool Cond) { 8880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The problem with updating live intervals is that we can move one def 8890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // past another def. In particular, this can happen when moving an A2_tfrt 8900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // over an A2_tfrf defining the same register. From the point of view of 8910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // live intervals, these two instructions are two separate definitions, 8920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and each one starts another live segment. LiveIntervals's "handleMove" 8930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // does not allow such moves, so we need to handle it ourselves. To avoid 8940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // invalidating liveness data while we are using it, the move will be 8950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // implemented in 4 steps: (1) add a clone of the instruction MI at the 8960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // target location, (2) update liveness, (3) delete the old instruction, 8970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and (4) update liveness again. 8980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock &B = *MI->getParent(); 9000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction. 9010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Opc = MI->getOpcode(); 9020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PredOpc = HII->getCondOpcode(Opc, !Cond); 9030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc)); 9040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Ox = 0, NP = MI->getNumOperands(); 9050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Skip all defs from MI first. 9060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar while (Ox < NP) { 9070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MO = MI->getOperand(Ox); 9080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MO.isReg() || !MO.isDef()) 9090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 9100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Ox++; 9110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 9120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Add the new def, then the predicate register, then the rest of the 9130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // operands. 9140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MB.addReg(RD.Reg, RegState::Define, RD.Sub); 9150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MB.addReg(PredR); 9160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar while (Ox < NP) { 9170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MO = MI->getOperand(Ox); 9180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MO.isReg() || !MO.isImplicit()) 9190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MB.addOperand(MO); 9200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Ox++; 9210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 9220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineFunction &MF = *B.getParent(); 9240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr::mmo_iterator I = MI->memoperands_begin(); 9250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned NR = std::distance(I, MI->memoperands_end()); 9260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR); 9270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0; i < NR; ++i) 9280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MemRefs[i] = *I++; 9290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MB.setMemRefs(MemRefs, MemRefs+NR); 9300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *NewI = MB; 9320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NewI->clearKillInfo(); 9330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar addInstrToLiveness(NewI); 9340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 9350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// In the range [First, Last], rename all references to the "old" register RO 9380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// to the "new" register RN, but only in instructions predicated on the given 9390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// condition. 9400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, 9410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PredR, bool Cond, MachineBasicBlock::iterator First, 9420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator Last) { 9430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator End = std::next(Last); 9440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = First; I != End; ++I) { 9450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 9460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Do not touch instructions that are not predicated, or are predicated 9470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // on the opposite condition. 9480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!HII->isPredicated(MI)) 9490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 9500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI))) 9510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 9520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 9540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || RO != RegisterRef(Op)) 9550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 9560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setReg(RN.Reg); 9570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setSubReg(RN.Sub); 9580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // In practice, this isn't supposed to see any defs. 9590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(!Op.isDef() && "Not expecting a def"); 9600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 9610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 9620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 9630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// For a given conditional copy, predicate the definition of the source of 9660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the copy under the given condition (using the same predicate register as 9670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the copy). 9680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond) { 9690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi). 9700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Opc = TfrI->getOpcode(); 9710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar (void)Opc; 9720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf); 9730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") 9740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << ": " << *TfrI); 9750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MD = TfrI->getOperand(0); 9770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MP = TfrI->getOperand(1); 9780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MS = TfrI->getOperand(2); 9790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The source operand should be a <kill>. This is not strictly necessary, 9800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // but it makes things a lot simpler. Otherwise, we would need to rename 9810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // some registers, which would complicate the transformation considerably. 9820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MS.isKill()) 9830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 9840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RT(MS); 9860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PredR = MP.getReg(); 9870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); 9880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!DefI || !isPredicable(DefI)) 9890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 9900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "Source def: " << *DefI); 9920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Collect the information about registers defined and used between the 9940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // DefI and the TfrI. 9950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Map: reg -> bitmask of subregs 9960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap Uses, Defs; 9970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI; 9980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Check if the predicate register is valid between DefI and TfrI. 10000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If it is, we can then ignore instructions predicated on the negated 10010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // conditions when collecting def and use information. 10020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool PredValid = true; 10030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) { 10040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!I->modifiesRegister(PredR, 0)) 10050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 10060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PredValid = false; 10070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 10080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) { 10110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 10120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If this instruction is predicated on the same register, it could 10130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // potentially be ignored. 10140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // By default assume that the instruction executes on the same condition 10150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // as TfrI (Exec_Then), and also on the opposite one (Exec_Else). 10160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Exec = Exec_Then | Exec_Else; 10170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR)) 10180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else; 10190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 10210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg()) 10220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 10230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We don't want to deal with physical registers. The reason is that 10240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // they can be aliased with other physical registers. Aliased virtual 10250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // registers must share the same register number, and can only differ 10260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // in the subregisters, which we are keeping track of. Physical 10270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // registers ters no longer have subregisters---their super- and 10280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // subregisters are other physical registers, and we are not checking 10290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // that. 10300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RR = Op; 10310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(RR.Reg)) 10320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 10330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap &Map = Op.isDef() ? Defs : Uses; 10350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar addRefToMap(RR, Map, Exec); 10360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The situation: 10400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // RT = DefI 10410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // ... 10420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // RD = TfrI ..., RT 10430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the register-in-the-middle (RT) is used or redefined between 10450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // DefI and TfrI, we may not be able proceed with this transformation. 10460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We can ignore a def that will not execute together with TfrI, and a 10470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // use that will. If there is such a use (that does execute together with 10480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // TfrI), we will not be able to move DefI down. If there is a use that 10490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // executed if TfrI's condition is false, then RT must be available 10500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // unconditionally (cannot be predicated). 10510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Essentially, we need to be able to rename RT to RD in this segment. 10520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else)) 10530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 10540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RD = MD; 10550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the predicate register is defined between DefI and TfrI, the only 10560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // potential thing to do would be to move the DefI down to TfrI, and then 10570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // predicate. The reaching def (DefI) must be movable down to the location 10580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // of the TfrI. 10590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the target register of the TfrI (RD) is not used or defined between 10600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // DefI and TfrI, consider moving TfrI up to DefI. 10610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool CanUp = canMoveOver(TfrI, Defs, Uses); 10620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool CanDown = canMoveOver(DefI, Defs, Uses); 10630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The TfrI does not access memory, but DefI could. Check if it's safe 10640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // to move DefI down to TfrI. 10650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (DefI->mayLoad() || DefI->mayStore()) 10660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!canMoveMemTo(DefI, TfrI, true)) 10670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar CanDown = false; 10680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no") 10700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << ", can move down: " << (CanDown ? "yes\n" : "no\n")); 10710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator PastDefIt = std::next(DefIt); 10720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (CanUp) 10730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar predicateAt(RD, DefI, PastDefIt, PredR, Cond); 10740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else if (CanDown) 10750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar predicateAt(RD, DefI, TfrIt, PredR, Cond); 10760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else 10770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 10780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RT != RD) 10800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt); 10810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Delete the user of RT first (it should work either way, but this order 10830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // of deleting is more natural). 10840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar removeInstrFromLiveness(TfrI); 10850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar removeInstrFromLiveness(DefI); 10860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 10870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 10880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Predicate all cases of conditional copies in the specified block. 10910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B) { 10920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 10930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator I, E, NextI; 10940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (I = B.begin(), E = B.end(); I != E; I = NextI) { 10950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NextI = std::next(I); 10960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Opc = I->getOpcode(); 10970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) { 10980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Done = predicate(I, (Opc == Hexagon::A2_tfrt)); 10990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Done) { 11000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If we didn't predicate I, we may need to remove it in case it is 11010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1. 11020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) 11030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar removeInstrFromLiveness(I); 11040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= Done; 11060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 11090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::removeImplicitUses(MachineInstr *MI) { 11130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = MI->getNumOperands(); i > 0; --i) { 11140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MO = MI->getOperand(i-1); 11150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MO.isReg() && MO.isUse() && MO.isImplicit()) 11160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MI->RemoveOperand(i-1); 11170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::removeImplicitUses(MachineBasicBlock &B) { 11220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) { 11230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 11240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (HII->isPredicated(MI)) 11250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar removeImplicitUses(MI); 11260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::postprocessUndefImplicitUses(MachineBasicBlock &B) { 11310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Implicit uses that are "undef" are only meaningful (outside of the 11320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // internals of this pass) when the instruction defines a subregister, 11330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and the implicit-undef use applies to the defined register. In such 11340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // cases, the proper way to record the information in the IR is to mark 11350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the definition as "undef", which will be interpreted as "read-undef". 11360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar typedef SmallSet<unsigned,2> RegisterSet; 11370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) { 11380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 11390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterSet Undefs; 11400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = MI->getNumOperands(); i > 0; --i) { 11410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &MO = MI->getOperand(i-1); 11420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.isUndef()) { 11430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MI->RemoveOperand(i-1); 11440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Undefs.insert(MO.getReg()); 11450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 11480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef() || !Op.getSubReg()) 11490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 11500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Undefs.count(Op.getReg())) 11510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setIsUndef(true); 11520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { 11580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(RR.Reg)) 11590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); 11610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RC == &Hexagon::IntRegsRegClass) { 11620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar BW = 32; 11630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 11640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RC == &Hexagon::DoubleRegsRegClass) { 11660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar BW = (RR.Sub != 0) ? 32 : 64; 11670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 11680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) { 11740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 11750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveRange::Segment &LR = *I; 11760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Range must start at a register... 11770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!LR.start.isRegister()) 11780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // ...and end in a register or in a dead slot. 11800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!LR.end.isRegister() && !LR.end.isDead()) 11810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 11840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { 11880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (CoaLimitActive) { 11890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (CoaCounter >= CoaLimit) 11900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar CoaCounter++; 11920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned BW1, BW2; 11940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2) 11950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MRI->isLiveIn(R1.Reg)) 11970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MRI->isLiveIn(R2.Reg)) 11990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 12000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &L1 = LIS->getInterval(R1.Reg); 12020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &L2 = LIS->getInterval(R2.Reg); 12030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Overlap = L1.overlaps(L2); 12040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "compatible registers: (" 12060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << (Overlap ? "overlap" : "disjoint") << ")\n " 12070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " 12080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); 12090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (R1.Sub || R2.Sub) 12100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 12110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Overlap) 12120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 12130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Coalescing could have a negative impact on scheduling, so try to limit 12150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // to some reasonable extent. Only consider coalescing segments, when one 12160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // of them does not cross basic block boundaries. 12170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!isIntraBlocks(L1) && !isIntraBlocks(L2)) 12180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 12190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MRI->replaceRegWith(R2.Reg, R1.Reg); 12210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Move all live segments from L2 to L1. 12230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap; 12240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ValueInfoMap VM; 12250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) { 12260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VNInfo *NewVN, *OldVN = I->valno; 12270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ValueInfoMap::iterator F = VM.find(OldVN); 12280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (F == VM.end()) { 12290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator()); 12300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VM.insert(std::make_pair(OldVN, NewVN)); 12310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 12320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NewVN = F->second; 12330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN)); 12350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar while (L2.begin() != L2.end()) 12370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar L2.removeSegment(*L2.begin()); 12380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar updateKillFlags(R1.Reg, L1); 12400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "coalesced: " << L1 << "\n"); 12410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar L1.verify(); 12420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 12440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 12450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Attempt to coalesce one of the source registers to a MUX intruction with 12480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the destination register. This could lead to having only one predicated 12490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// instruction in the end instead of two. 12500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::coalesceSegments(MachineFunction &MF) { 12510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SmallVector<MachineInstr*,16> Condsets; 12520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { 12530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock &B = *I; 12540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator J = B.begin(), F = B.end(); J != F; ++J) { 12550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*J; 12560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!isCondset(MI)) 12570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 12580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3); 12590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!S1.isReg() && !S2.isReg()) 12600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 12610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Condsets.push_back(MI); 12620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 12660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0, n = Condsets.size(); i < n; ++i) { 12670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *CI = Condsets[i]; 12680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RD = CI->getOperand(0); 12690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RP = CI->getOperand(1); 12700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3); 12710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Done = false; 12720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Consider this case: 12730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg1 = instr1 ... 12740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg2 = instr2 ... 12750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = C2_mux ..., vreg1, vreg2 12760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If vreg0 was coalesced with vreg1, we could end up with the following 12770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // code: 12780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = instr1 ... 12790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg2 = instr2 ... 12800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = A2_tfrf ..., vreg2 12810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // which will later become: 12820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = instr1 ... 12830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = instr2_cNotPt ... 12840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // i.e. there will be an unconditional definition (instr1) of vreg0 12850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // followed by a conditional one. The output dependency was there before 12860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and it unavoidable, but if instr1 is predicable, we will no longer be 12870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // able to predicate it here. 12880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // To avoid this scenario, don't coalesce the destination register with 12890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // a source register that is defined by a predicable instruction. 12900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (S1.isReg()) { 12910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RS = S1; 12920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true); 12930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!RDef || !HII->isPredicable(RDef)) 12940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Done = coalesceRegisters(RD, RegisterRef(S1)); 12950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Done && S2.isReg()) { 12970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RS = S2; 12980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false); 12990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!RDef || !HII->isPredicable(RDef)) 13000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Done = coalesceRegisters(RD, RegisterRef(S2)); 13010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 13020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= Done; 13030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 13040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 13050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 13060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { 13090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo()); 13100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TRI = MF.getSubtarget().getRegisterInfo(); 13110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS = &getAnalysis<LiveIntervals>(); 13120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MRI = &MF.getRegInfo(); 13130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 13150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Try to coalesce the target of a mux with one of its sources. 13170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // This could eliminate a register copy in some circumstances. 13180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= coalesceSegments(MF); 13190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { 13210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // First, simply split all muxes into a pair of conditional transfers 13220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and update the live intervals to reflect the new arrangement. 13230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // This is done mainly to make the live interval update simpler, than it 13240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // would be while trying to predicate instructions at the same time. 13250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= splitInBlock(*I); 13260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Traverse all blocks and collapse predicable instructions feeding 13270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // conditional transfers into predicated instructions. 13280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Walk over all the instructions again, so we may catch pre-existing 13290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // cases that were not created in the previous step. 13300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= predicateInBlock(*I); 13310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 13320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 13340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar postprocessUndefImplicitUses(*I); 13350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 13360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 13370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar//===----------------------------------------------------------------------===// 13400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Public Constructor Functions 13410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar//===----------------------------------------------------------------------===// 13420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarstatic void initializePassOnce(PassRegistry &Registry) { 13440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const char *Name = "Hexagon Expand Condsets"; 13450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PassInfo *PI = new PassInfo(Name, "expand-condsets", 13460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar &HexagonExpandCondsets::ID, 0, false, false); 13470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Registry.registerPass(*PI, true); 13480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 13490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid llvm::initializeHexagonExpandCondsetsPass(PassRegistry &Registry) { 13510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar CALL_ONCE_INITIALIZATION(initializePassOnce) 13520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 13530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga NainarFunctionPass *llvm::createHexagonExpandCondsets() { 13560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return new HexagonExpandCondsets(); 13570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 1358