1cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar//===--- HexagonGenPredicate.cpp ------------------------------------------===// 2cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// 3cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// The LLVM Compiler Infrastructure 4cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// 5cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// This file is distributed under the University of Illinois Open Source 6cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// License. See LICENSE.TXT for details. 7cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar// 8cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar//===----------------------------------------------------------------------===// 9cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 10cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#define DEBUG_TYPE "gen-pred" 11cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 12cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/ADT/SetVector.h" 13cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/CodeGen/Passes.h" 14cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/CodeGen/MachineDominators.h" 15cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/CodeGen/MachineFunctionPass.h" 16cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/CodeGen/MachineInstrBuilder.h" 17cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/CodeGen/MachineLoopInfo.h" 18cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/CodeGen/MachineRegisterInfo.h" 19cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/Support/CommandLine.h" 20cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/Support/Debug.h" 21cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/Support/raw_ostream.h" 22cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/Target/TargetMachine.h" 23cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "llvm/Target/TargetInstrInfo.h" 24cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include "HexagonTargetMachine.h" 25cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 26cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include <functional> 27cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include <queue> 28cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include <set> 29cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar#include <vector> 30cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 31cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarusing namespace llvm; 32cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 33cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarnamespace llvm { 34cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar void initializeHexagonGenPredicatePass(PassRegistry& Registry); 35cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar FunctionPass *createHexagonGenPredicate(); 36cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 37cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 38cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarnamespace { 39cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar struct Register { 40cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned R, S; 41cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register(unsigned r = 0, unsigned s = 0) : R(r), S(s) {} 42cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {} 43cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool operator== (const Register &Reg) const { 44cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return R == Reg.R && S == Reg.S; 45cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 46cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool operator< (const Register &Reg) const { 47cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return R < Reg.R || (R == Reg.R && S < Reg.S); 48cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 49cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar }; 50cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar struct PrintRegister { 51cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {} 52cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR); 53cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar private: 54cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register Reg; 55cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterInfo &TRI; 56cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar }; 57cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) 58cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar LLVM_ATTRIBUTE_UNUSED; 59cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { 60cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); 61cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 62cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 63cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar class HexagonGenPredicate : public MachineFunctionPass { 64cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar public: 65cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar static char ID; 66cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar HexagonGenPredicate() : MachineFunctionPass(ID), TII(0), TRI(0), MRI(0) { 67cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar initializeHexagonGenPredicatePass(*PassRegistry::getPassRegistry()); 68cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 69cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual const char *getPassName() const { 70cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return "Hexagon generate predicate operations"; 71cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 72cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual void getAnalysisUsage(AnalysisUsage &AU) const { 73cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar AU.addRequired<MachineDominatorTree>(); 74cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar AU.addPreserved<MachineDominatorTree>(); 75cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineFunctionPass::getAnalysisUsage(AU); 76cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 77cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar virtual bool runOnMachineFunction(MachineFunction &MF); 78cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 79cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar private: 80cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar typedef SetVector<MachineInstr*> VectOfInst; 81cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar typedef std::set<Register> SetOfReg; 82cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar typedef std::map<Register,Register> RegToRegMap; 83cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 84cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const HexagonInstrInfo *TII; 85cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const HexagonRegisterInfo *TRI; 86cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineRegisterInfo *MRI; 87cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar SetOfReg PredGPRs; 88cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar VectOfInst PUsers; 89cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar RegToRegMap G2P; 90cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 91cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool isPredReg(unsigned R); 92cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar void collectPredicateGPR(MachineFunction &MF); 93cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar void processPredicateGPR(const Register &Reg); 94cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned getPredForm(unsigned Opc); 95cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool isConvertibleToPredForm(const MachineInstr *MI); 96cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool isScalarCmp(unsigned Opc); 97cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool isScalarPred(Register PredReg); 98cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register getPredRegFor(const Register &Reg); 99cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool convertToPredForm(MachineInstr *MI); 100cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool eliminatePredCopies(MachineFunction &MF); 101cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar }; 102cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 103cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar char HexagonGenPredicate::ID = 0; 104cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 105cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 106cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarINITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred", 107cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar "Hexagon generate predicate operations", false, false) 108cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarINITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 109cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarINITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred", 110cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar "Hexagon generate predicate operations", false, false) 111cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 112cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarbool HexagonGenPredicate::isPredReg(unsigned R) { 113cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(R)) 114cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 115cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *RC = MRI->getRegClass(R); 116cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return RC == &Hexagon::PredRegsRegClass; 117cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 118cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 119cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 120cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarunsigned HexagonGenPredicate::getPredForm(unsigned Opc) { 121cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar using namespace Hexagon; 122cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 123cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar switch (Opc) { 124cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A2_and: 125cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A2_andp: 126cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C2_and; 127cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A4_andn: 128cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A4_andnp: 129cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C2_andn; 130cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case M4_and_and: 131cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C4_and_and; 132cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case M4_and_andn: 133cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C4_and_andn; 134cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case M4_and_or: 135cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C4_and_or; 136cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 137cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A2_or: 138cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A2_orp: 139cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C2_or; 140cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A4_orn: 141cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A4_ornp: 142cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C2_orn; 143cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case M4_or_and: 144cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C4_or_and; 145cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case M4_or_andn: 146cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C4_or_andn; 147cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case M4_or_or: 148cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C4_or_or; 149cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 150cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A2_xor: 151cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case A2_xorp: 152cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return C2_xor; 153cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 154cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case C2_tfrrp: 155cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return COPY; 156cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 157cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // The opcode corresponding to 0 is TargetOpcode::PHI. We can use 0 here 158cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // to denote "none", but we need to make sure that none of the valid opcodes 159cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // that we return will ever be 0. 160cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(PHI == 0 && "Use different value for <none>"); 161cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return 0; 162cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 163cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 164cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 165cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarbool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) { 166cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned Opc = MI->getOpcode(); 167cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (getPredForm(Opc) != 0) 168cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return true; 169cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 170cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Comparisons against 0 are also convertible. This does not apply to 171cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // A4_rcmpeqi or A4_rcmpneqi, since they produce values 0 or 1, which 172cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // may not match the value that the predicate register would have if 173cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // it was converted to a predicate form. 174cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar switch (Opc) { 175cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpeqi: 176cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmpneqi: 177cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) 178cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return true; 179cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar break; 180cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 181cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 182cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 183cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 184cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 185cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarvoid HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) { 186cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (MachineFunction::iterator A = MF.begin(), Z = MF.end(); A != Z; ++A) { 187cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineBasicBlock &B = *A; 188cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) { 189cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstr *MI = &*I; 190cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned Opc = MI->getOpcode(); 191cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar switch (Opc) { 192cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_tfrpr: 193cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case TargetOpcode::COPY: 194cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (isPredReg(MI->getOperand(1).getReg())) { 195cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register RD = MI->getOperand(0); 196cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (TargetRegisterInfo::isVirtualRegister(RD.R)) 197cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar PredGPRs.insert(RD); 198cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 199cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar break; 200cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 201cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 202cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 203cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 204cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 205cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 206cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarvoid HexagonGenPredicate::processPredicateGPR(const Register &Reg) { 207cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " 208cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar << PrintReg(Reg.R, TRI, Reg.S) << "\n"); 209cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar typedef MachineRegisterInfo::use_iterator use_iterator; 210cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end(); 211cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (I == E) { 212cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n'); 213cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstr *DefI = MRI->getVRegDef(Reg.R); 214cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DefI->eraseFromParent(); 215cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return; 216cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 217cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 218cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (; I != E; ++I) { 219cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstr *UseI = I->getParent(); 220cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (isConvertibleToPredForm(UseI)) 221cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar PUsers.insert(UseI); 222cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 223cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 224cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 225cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 226cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarRegister HexagonGenPredicate::getPredRegFor(const Register &Reg) { 227cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Create a predicate register for a given Reg. The newly created register 228cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // will have its value copied from Reg, so that it can be later used as 229cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // an operand in other instructions. 230cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(TargetRegisterInfo::isVirtualRegister(Reg.R)); 231cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar RegToRegMap::iterator F = G2P.find(Reg); 232cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (F != G2P.end()) 233cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return F->second; 234cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 235cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << PrintRegister(Reg, *TRI)); 236cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstr *DefI = MRI->getVRegDef(Reg.R); 237cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(DefI); 238cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned Opc = DefI->getOpcode(); 239cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) { 240cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); 241cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register PR = DefI->getOperand(1); 242cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar G2P.insert(std::make_pair(Reg, PR)); 243cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); 244cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return PR; 245cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 246cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 247cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineBasicBlock &B = *DefI->getParent(); 248cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DebugLoc DL = DefI->getDebugLoc(); 249cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; 250cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned NewPR = MRI->createVirtualRegister(PredRC); 251cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 252cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // For convertible instructions, do not modify them, so that they can 253cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // be converted later. Generate a copy from Reg to NewPR. 254cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (isConvertibleToPredForm(DefI)) { 255cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineBasicBlock::iterator DefIt = DefI; 256cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR) 257cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar .addReg(Reg.R, 0, Reg.S); 258cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar G2P.insert(std::make_pair(Reg, Register(NewPR))); 259cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) << '\n'); 260cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return Register(NewPR); 261cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 262cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 263cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar llvm_unreachable("Invalid argument"); 264cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 265cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 266cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 267cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarbool HexagonGenPredicate::isScalarCmp(unsigned Opc) { 268cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar switch (Opc) { 269cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpeq: 270cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgt: 271cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgtu: 272cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpeqp: 273cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgtp: 274cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgtup: 275cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpeqi: 276cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgti: 277cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgtui: 278cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgei: 279cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpgeui: 280cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmpneqi: 281cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmpltei: 282cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmplteui: 283cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmpneq: 284cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmplte: 285cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmplteu: 286cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpbeq: 287cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpbeqi: 288cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpbgtu: 289cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpbgtui: 290cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpbgt: 291cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpbgti: 292cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpheq: 293cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmphgt: 294cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmphgtu: 295cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmpheqi: 296cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmphgti: 297cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::A4_cmphgtui: 298cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return true; 299cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 300cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 301cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 302cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 303cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 304cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarbool HexagonGenPredicate::isScalarPred(Register PredReg) { 305cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar std::queue<Register> WorkQ; 306cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar WorkQ.push(PredReg); 307cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 308cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar while (!WorkQ.empty()) { 309cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register PR = WorkQ.front(); 310cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar WorkQ.pop(); 311cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const MachineInstr *DefI = MRI->getVRegDef(PR.R); 312cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!DefI) 313cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 314cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned DefOpc = DefI->getOpcode(); 315cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar switch (DefOpc) { 316cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case TargetOpcode::COPY: { 317cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; 318cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (MRI->getRegClass(PR.R) != PredRC) 319cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 320cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // If it is a copy between two predicate registers, fall through. 321cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 322cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_and: 323cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_andn: 324cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_and_and: 325cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_and_andn: 326cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_and_or: 327cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_or: 328cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_orn: 329cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_or_and: 330cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_or_andn: 331cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_or_or: 332cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_or_orn: 333cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_xor: 334cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Add operands to the queue. 335cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (ConstMIOperands Mo(DefI); Mo.isValid(); ++Mo) 336cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (Mo->isReg() && Mo->isUse()) 337cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar WorkQ.push(Register(Mo->getReg())); 338cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar break; 339cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 340cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // All non-vector compares are ok, everything else is bad. 341cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar default: 342cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return isScalarCmp(DefOpc); 343cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 344cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 345cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 346cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return true; 347cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 348cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 349cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 350cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarbool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) { 351cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << MI << " " << *MI); 352cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 353cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned Opc = MI->getOpcode(); 354cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(isConvertibleToPredForm(MI)); 355cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned NumOps = MI->getNumOperands(); 356cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (unsigned i = 0; i < NumOps; ++i) { 357cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineOperand &MO = MI->getOperand(i); 358cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!MO.isReg() || !MO.isUse()) 359cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar continue; 360cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register Reg(MO); 361cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (Reg.S && Reg.S != Hexagon::subreg_loreg) 362cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 363cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!PredGPRs.count(Reg)) 364cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 365cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 366cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 367cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineBasicBlock &B = *MI->getParent(); 368cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DebugLoc DL = MI->getDebugLoc(); 369cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 370cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned NewOpc = getPredForm(Opc); 371cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Special case for comparisons against 0. 372cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (NewOpc == 0) { 373cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar switch (Opc) { 374cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C2_cmpeqi: 375cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar NewOpc = Hexagon::C2_not; 376cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar break; 377cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar case Hexagon::C4_cmpneqi: 378cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar NewOpc = TargetOpcode::COPY; 379cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar break; 380cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar default: 381cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 382cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 383cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 384cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // If it's a scalar predicate register, then all bits in it are 385cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // the same. Otherwise, to determine whether all bits are 0 or not 386cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // we would need to use any8. 387cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register PR = getPredRegFor(MI->getOperand(1)); 388cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!isScalarPred(PR)) 389cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return false; 390cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // This will skip the immediate argument when creating the predicate 391cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // version instruction. 392cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar NumOps = 2; 393cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 394cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 395cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Some sanity: check that def is in operand #0. 396cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineOperand &Op0 = MI->getOperand(0); 397cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(Op0.isDef()); 398cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register OutR(Op0); 399cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 400cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Don't use getPredRegFor, since it will create an association between 401cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // the argument and a created predicate register (i.e. it will insert a 402cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // copy if a new predicate register is created). 403cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; 404cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register NewPR = MRI->createVirtualRegister(PredRC); 405cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); 406cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 407cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Add predicate counterparts of the GPRs. 408cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (unsigned i = 1; i < NumOps; ++i) { 409cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register GPR = MI->getOperand(i); 410cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register Pred = getPredRegFor(GPR); 411cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MIB.addReg(Pred.R, 0, Pred.S); 412cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 413cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << "generated: " << *MIB); 414cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 415cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Generate a copy-out: NewGPR = NewPR, and replace all uses of OutR 416cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // with NewGPR. 417cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *RC = MRI->getRegClass(OutR.R); 418cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar unsigned NewOutR = MRI->createVirtualRegister(RC); 419cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR) 420cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar .addReg(NewPR.R, 0, NewPR.S); 421cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MRI->replaceRegWith(OutR.R, NewOutR); 422cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MI->eraseFromParent(); 423cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 424cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // If the processed instruction was C2_tfrrp (i.e. Rn = Pm; Pk = Rn), 425cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // then the output will be a predicate register. Do not visit the 426cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // users of it. 427cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!isPredReg(NewOutR)) { 428cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register R(NewOutR); 429cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar PredGPRs.insert(R); 430cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar processPredicateGPR(R); 431cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 432cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return true; 433cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 434cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 435cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 436cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarbool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) { 437cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar DEBUG(dbgs() << LLVM_FUNCTION_NAME << "\n"); 438cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; 439cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool Changed = false; 440cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar VectOfInst Erase; 441cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 442cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // First, replace copies 443cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // IntR = PredR1 444cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // PredR2 = IntR 445cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // with 446cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // PredR2 = PredR1 447cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // Such sequences can be generated when a copy-into-pred is generated from 448cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // a gpr register holding a result of a convertible instruction. After 449cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // the convertible instruction is converted, its predicate result will be 450cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar // copied back into the original gpr. 451cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 452cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (MachineFunction::iterator A = MF.begin(), Z = MF.end(); A != Z; ++A) { 453cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineBasicBlock &B = *A; 454cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) { 455cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (I->getOpcode() != TargetOpcode::COPY) 456cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar continue; 457cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register DR = I->getOperand(0); 458cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Register SR = I->getOperand(1); 459cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(DR.R)) 460cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar continue; 461cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(SR.R)) 462cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar continue; 463cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (MRI->getRegClass(DR.R) != PredRC) 464cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar continue; 465cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (MRI->getRegClass(SR.R) != PredRC) 466cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar continue; 467cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar assert(!DR.S && !SR.S && "Unexpected subregister"); 468cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MRI->replaceRegWith(DR.R, SR.R); 469cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Erase.insert(I); 470cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Changed = true; 471cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 472cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 473cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 474cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (VectOfInst::iterator I = Erase.begin(), E = Erase.end(); I != E; ++I) 475cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar (*I)->eraseFromParent(); 476cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 477cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return Changed; 478cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 479cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 480cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 481cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainarbool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) { 482cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); 483cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar TRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); 484cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MRI = &MF.getRegInfo(); 485cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar PredGPRs.clear(); 486cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar PUsers.clear(); 487cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar G2P.clear(); 488cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 489cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool Changed = false; 490cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar collectPredicateGPR(MF); 491cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (SetOfReg::iterator I = PredGPRs.begin(), E = PredGPRs.end(); I != E; ++I) 492cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar processPredicateGPR(*I); 493cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 494cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool Again; 495cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar do { 496cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Again = false; 497cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar VectOfInst Processed, Copy; 498cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 499cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar typedef VectOfInst::iterator iterator; 500cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Copy = PUsers; 501cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar for (iterator I = Copy.begin(), E = Copy.end(); I != E; ++I) { 502cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar MachineInstr *MI = *I; 503cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar bool Done = convertToPredForm(MI); 504cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar if (Done) { 505cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Processed.insert(MI); 506cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Again = true; 507cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 508cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } 509cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Changed |= Again; 510cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 511cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar auto Done = [Processed] (MachineInstr *MI) -> bool { 512cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return Processed.count(MI); 513cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar }; 514cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar PUsers.remove_if(Done); 515cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar } while (Again); 516cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 517cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar Changed |= eliminatePredCopies(MF); 518cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return Changed; 519cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 520cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 521cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 522cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga NainarFunctionPass *llvm::createHexagonGenPredicate() { 523cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar return new HexagonGenPredicate(); 524cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar} 525cddc3e03e4ec99c0268c03a126195173e519ed58Pirama Arumuga Nainar 526