1b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==// 2b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 3b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// The LLVM Compiler Infrastructure 4b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 5b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// This file is distributed under the University of Illinois Open Source 6b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// License. See LICENSE.TXT for details. 7b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 8b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum//===----------------------------------------------------------------------===// 9b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 10b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// This file contains the Hexagon implementation of the TargetRegisterInfo 11b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// class. 12b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 13b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum//===----------------------------------------------------------------------===// 14b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 1537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H 1637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H 17b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 1879aa3417eb6f58d668aadfedf075240a41d35a26Craig Topper#include "llvm/MC/MachineLocation.h" 19a1514e24cc24b050f53a12650e047799358833a1Chandler Carruth#include "llvm/Target/TargetRegisterInfo.h" 2079aa3417eb6f58d668aadfedf075240a41d35a26Craig Topper 21b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#define GET_REGINFO_HEADER 22b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#include "HexagonGenRegisterInfo.inc" 23b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 24b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 25b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// We try not to hard code the reserved registers in our code, 26b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// so the following two macros were defined. However, there 27b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// are still a few places that R11 and R10 are hard wired. 28b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// See below. If, in the future, we decided to change the reserved 29b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// register. Don't forget changing the following places. 30b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 31b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td 32b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td 33b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 3. the definition of "IntRegs" in HexagonRegisterInfo.td 34b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td 35b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum// 36b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#define HEXAGON_RESERVED_REG_1 Hexagon::R10 37b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#define HEXAGON_RESERVED_REG_2 Hexagon::R11 38b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 39b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicumnamespace llvm { 406948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarclass HexagonRegisterInfo : public HexagonGenRegisterInfo { 416948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarpublic: 424c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar HexagonRegisterInfo(); 43b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 44b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum /// Code Generation virtual methods... 456948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) 466948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar const override; 47b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 48b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 49dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BitVector getReservedRegs(const MachineFunction &MF) const override; 50b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 516948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 526948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; 53b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 546948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// Returns true since we may need scavenging for a temporary register 556948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// when generating hardware loop instructions. 56dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool requiresRegisterScavenging(const MachineFunction &MF) const override { 57b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum return true; 58b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum } 59b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 606948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// Returns true. Spill code for predicate registers might need an extra 616948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// register. 626948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool requiresFrameIndexScavenging(const MachineFunction &MF) const override { 636948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar return true; 646948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar } 656948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 666948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar /// Returns true if the frame pointer is valid. 676948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool useFPForScavengingIndex(const MachineFunction &MF) const override; 686948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 69dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { 706a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return true; 716a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd } 726a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 73b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum // Debug information queries. 74b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned getRARegister() const; 75dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned getFrameRegister(const MachineFunction &MF) const override; 76b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned getFrameRegister() const; 77b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum unsigned getStackRegister() const; 786948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 796948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF) const; 806948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 816948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar unsigned getFirstCallerSavedNonParamReg() const; 826948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar 836948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isEHReturnCalleeSaveReg(unsigned Reg) const; 846948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar bool isCalleeSaveReg(unsigned Reg) const; 85b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum}; 86b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 87b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum} // end namespace llvm 88b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum 89b4b54153ad760c69a00a08531abef4ed434a5092Tony Linthicum#endif 90