MipsRegisterInfo.cpp revision 7067d4e4de8e0d795fb16c7c10fcf98028ca7577
1//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MIPS implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-reg-info" 15 16#include "MipsRegisterInfo.h" 17#include "Mips.h" 18#include "MipsAnalyzeImmediate.h" 19#include "MipsSubtarget.h" 20#include "MipsMachineFunction.h" 21#include "llvm/Constants.h" 22#include "llvm/Type.h" 23#include "llvm/Function.h" 24#include "llvm/CodeGen/ValueTypes.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/Target/TargetFrameLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/BitVector.h" 37#include "llvm/ADT/STLExtras.h" 38#include "llvm/Analysis/DebugInfo.h" 39 40#define GET_REGINFO_TARGET_DESC 41#include "MipsGenRegisterInfo.inc" 42 43using namespace llvm; 44 45MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, 46 const TargetInstrInfo &tii) 47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {} 48 49unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 50 51//===----------------------------------------------------------------------===// 52// Callee Saved Registers methods 53//===----------------------------------------------------------------------===// 54 55/// Mips Callee Saved Registers 56const uint16_t* MipsRegisterInfo:: 57getCalleeSavedRegs(const MachineFunction *MF) const 58{ 59 if (Subtarget.isSingleFloat()) 60 return CSR_SingleFloatOnly_SaveList; 61 else if (!Subtarget.hasMips64()) 62 return CSR_O32_SaveList; 63 else if (Subtarget.isABI_N32()) 64 return CSR_N32_SaveList; 65 66 assert(Subtarget.isABI_N64()); 67 return CSR_N64_SaveList; 68} 69 70const uint32_t* 71MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const 72{ 73 if (Subtarget.isSingleFloat()) 74 return CSR_SingleFloatOnly_RegMask; 75 else if (!Subtarget.hasMips64()) 76 return CSR_O32_RegMask; 77 else if (Subtarget.isABI_N32()) 78 return CSR_N32_RegMask; 79 80 assert(Subtarget.isABI_N64()); 81 return CSR_N64_RegMask; 82} 83 84BitVector MipsRegisterInfo:: 85getReservedRegs(const MachineFunction &MF) const { 86 static const uint16_t ReservedCPURegs[] = { 87 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, 88 Mips::SP, Mips::FP, Mips::RA 89 }; 90 91 static const uint16_t ReservedCPU64Regs[] = { 92 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, 93 Mips::SP_64, Mips::FP_64, Mips::RA_64 94 }; 95 96 BitVector Reserved(getNumRegs()); 97 typedef TargetRegisterClass::iterator RegIter; 98 99 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I) 100 Reserved.set(ReservedCPURegs[I]); 101 102 if (Subtarget.hasMips64()) { 103 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I) 104 Reserved.set(ReservedCPU64Regs[I]); 105 106 // Reserve all registers in AFGR64. 107 for (RegIter Reg = Mips::AFGR64RegisterClass->begin(); 108 Reg != Mips::AFGR64RegisterClass->end(); ++Reg) 109 Reserved.set(*Reg); 110 } 111 else { 112 // Reserve all registers in CPU64Regs & FGR64. 113 for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin(); 114 Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg) 115 Reserved.set(*Reg); 116 117 for (RegIter Reg = Mips::FGR64RegisterClass->begin(); 118 Reg != Mips::FGR64RegisterClass->end(); ++Reg) 119 Reserved.set(*Reg); 120 } 121 122 // If GP is dedicated as a global base register, reserve it. 123 if (MF.getInfo<MipsFunctionInfo>()->globalBaseRegFixed()) { 124 Reserved.set(Mips::GP); 125 Reserved.set(Mips::GP_64); 126 } 127 128 // Reserve hardware registers. 129 Reserved.set(Mips::HWR29); 130 Reserved.set(Mips::HWR29_64); 131 132 return Reserved; 133} 134 135// This function eliminate ADJCALLSTACKDOWN, 136// ADJCALLSTACKUP pseudo instructions 137void MipsRegisterInfo:: 138eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 139 MachineBasicBlock::iterator I) const { 140 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 141 MBB.erase(I); 142} 143 144// FrameIndex represent objects inside a abstract stack. 145// We must replace FrameIndex with an stack/frame pointer 146// direct reference. 147void MipsRegisterInfo:: 148eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 149 RegScavenger *RS) const { 150 MachineInstr &MI = *II; 151 MachineFunction &MF = *MI.getParent()->getParent(); 152 MachineFrameInfo *MFI = MF.getFrameInfo(); 153 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 154 155 unsigned i = 0; 156 while (!MI.getOperand(i).isFI()) { 157 ++i; 158 assert(i < MI.getNumOperands() && 159 "Instr doesn't have FrameIndex operand!"); 160 } 161 162 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n"; 163 errs() << "<--------->\n" << MI); 164 165 int FrameIndex = MI.getOperand(i).getIndex(); 166 uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 167 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 168 169 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 170 << "spOffset : " << spOffset << "\n" 171 << "stackSize : " << stackSize << "\n"); 172 173 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 174 int MinCSFI = 0; 175 int MaxCSFI = -1; 176 177 if (CSI.size()) { 178 MinCSFI = CSI[0].getFrameIdx(); 179 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); 180 } 181 182 // The following stack frame objects are always referenced relative to $sp: 183 // 1. Outgoing arguments. 184 // 2. Pointer to dynamically allocated stack space. 185 // 3. Locations for callee-saved registers. 186 // Everything else is referenced relative to whatever register 187 // getFrameRegister() returns. 188 unsigned FrameReg; 189 190 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) || 191 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) 192 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 193 else 194 FrameReg = getFrameRegister(MF); 195 196 // Calculate final offset. 197 // - There is no need to change the offset if the frame object is one of the 198 // following: an outgoing argument, pointer to a dynamically allocated 199 // stack space or a $gp restore location, 200 // - If the frame object is any of the following, its offset must be adjusted 201 // by adding the size of the stack: 202 // incoming argument, callee-saved register location or local variable. 203 int64_t Offset; 204 205 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) || 206 MipsFI->isDynAllocFI(FrameIndex)) 207 Offset = spOffset; 208 else 209 Offset = spOffset + (int64_t)stackSize; 210 211 Offset += MI.getOperand(i+1).getImm(); 212 213 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); 214 215 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate 216 // field. 217 if (!MI.isDebugValue() && !isInt<16>(Offset)) { 218 MachineBasicBlock &MBB = *MI.getParent(); 219 DebugLoc DL = II->getDebugLoc(); 220 MipsAnalyzeImmediate AnalyzeImm; 221 unsigned Size = Subtarget.isABI_N64() ? 64 : 32; 222 unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi; 223 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; 224 unsigned ZEROReg = Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 225 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT; 226 const MipsAnalyzeImmediate::InstSeq &Seq = 227 AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */); 228 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 229 230 // FIXME: change this when mips goes MC". 231 BuildMI(MBB, II, DL, TII.get(Mips::NOAT)); 232 233 // The first instruction can be a LUi, which is different from other 234 // instructions (ADDiu, ORI and SLL) in that it does not have a register 235 // operand. 236 if (Inst->Opc == LUi) 237 BuildMI(MBB, II, DL, TII.get(LUi), ATReg) 238 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 239 else 240 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg) 241 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 242 243 // Build the remaining instructions in Seq except for the last one. 244 for (++Inst; Inst != Seq.end() - 1; ++Inst) 245 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg) 246 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 247 248 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg); 249 250 FrameReg = ATReg; 251 Offset = SignExtend64<16>(Inst->ImmOpnd); 252 BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO)); 253 } 254 255 MI.getOperand(i).ChangeToRegister(FrameReg, false); 256 MI.getOperand(i+1).ChangeToImmediate(Offset); 257} 258 259unsigned MipsRegisterInfo:: 260getFrameRegister(const MachineFunction &MF) const { 261 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 262 bool IsN64 = Subtarget.isABI_N64(); 263 264 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 265 (IsN64 ? Mips::SP_64 : Mips::SP); 266} 267 268unsigned MipsRegisterInfo:: 269getEHExceptionRegister() const { 270 llvm_unreachable("What is the exception register"); 271} 272 273unsigned MipsRegisterInfo:: 274getEHHandlerRegister() const { 275 llvm_unreachable("What is the exception handler register"); 276} 277