MipsRegisterInfo.cpp revision 79aa3417eb6f58d668aadfedf075240a41d35a26 
1//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-reg-info"
15
16#include "MipsRegisterInfo.h"
17#include "Mips.h"
18#include "MipsAnalyzeImmediate.h"
19#include "MipsSubtarget.h"
20#include "MipsMachineFunction.h"
21#include "llvm/Constants.h"
22#include "llvm/Type.h"
23#include "llvm/Function.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/Target/TargetFrameLowering.h"
29#include "llvm/Target/TargetMachine.h"
30#include "llvm/Target/TargetOptions.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/ErrorHandling.h"
35#include "llvm/Support/raw_ostream.h"
36#include "llvm/ADT/BitVector.h"
37#include "llvm/ADT/STLExtras.h"
38#include "llvm/Analysis/DebugInfo.h"
39
40#define GET_REGINFO_TARGET_DESC
41#include "MipsGenRegisterInfo.inc"
42
43using namespace llvm;
44
45MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
46                                   const TargetInstrInfo &tii)
47  : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
48
49unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
50
51//===----------------------------------------------------------------------===//
52// Callee Saved Registers methods
53//===----------------------------------------------------------------------===//
54
55/// Mips Callee Saved Registers
56const uint16_t* MipsRegisterInfo::
57getCalleeSavedRegs(const MachineFunction *MF) const
58{
59  if (Subtarget.isSingleFloat())
60    return CSR_SingleFloatOnly_SaveList;
61  else if (!Subtarget.hasMips64())
62    return CSR_O32_SaveList;
63  else if (Subtarget.isABI_N32())
64    return CSR_N32_SaveList;
65
66  assert(Subtarget.isABI_N64());
67  return CSR_N64_SaveList;
68}
69
70const uint32_t*
71MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const
72{
73  if (Subtarget.isSingleFloat())
74    return CSR_SingleFloatOnly_RegMask;
75  else if (!Subtarget.hasMips64())
76    return CSR_O32_RegMask;
77  else if (Subtarget.isABI_N32())
78    return CSR_N32_RegMask;
79
80  assert(Subtarget.isABI_N64());
81  return CSR_N64_RegMask;
82}
83
84BitVector MipsRegisterInfo::
85getReservedRegs(const MachineFunction &MF) const {
86  static const uint16_t ReservedCPURegs[] = {
87    Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
88    Mips::SP, Mips::FP, Mips::RA
89  };
90
91  static const uint16_t ReservedCPU64Regs[] = {
92    Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
93    Mips::SP_64, Mips::FP_64, Mips::RA_64
94  };
95
96  BitVector Reserved(getNumRegs());
97  typedef TargetRegisterClass::iterator RegIter;
98
99  for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
100    Reserved.set(ReservedCPURegs[I]);
101
102  if (Subtarget.hasMips64()) {
103    for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
104      Reserved.set(ReservedCPU64Regs[I]);
105
106    // Reserve all registers in AFGR64.
107    for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
108         Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
109      Reserved.set(*Reg);
110  }
111  else {
112    // Reserve all registers in CPU64Regs & FGR64.
113    for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
114         Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
115      Reserved.set(*Reg);
116
117    for (RegIter Reg = Mips::FGR64RegisterClass->begin();
118         Reg != Mips::FGR64RegisterClass->end(); ++Reg)
119      Reserved.set(*Reg);
120  }
121
122  // If GP is dedicated as a global base register, reserve it.
123  if (MF.getInfo<MipsFunctionInfo>()->globalBaseRegFixed()) {
124    Reserved.set(Mips::GP);
125    Reserved.set(Mips::GP_64);
126  }
127
128  return Reserved;
129}
130
131// This function eliminate ADJCALLSTACKDOWN,
132// ADJCALLSTACKUP pseudo instructions
133void MipsRegisterInfo::
134eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
135                              MachineBasicBlock::iterator I) const {
136  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
137  MBB.erase(I);
138}
139
140// FrameIndex represent objects inside a abstract stack.
141// We must replace FrameIndex with an stack/frame pointer
142// direct reference.
143void MipsRegisterInfo::
144eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
145                    RegScavenger *RS) const {
146  MachineInstr &MI = *II;
147  MachineFunction &MF = *MI.getParent()->getParent();
148  MachineFrameInfo *MFI = MF.getFrameInfo();
149  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
150
151  unsigned i = 0;
152  while (!MI.getOperand(i).isFI()) {
153    ++i;
154    assert(i < MI.getNumOperands() &&
155           "Instr doesn't have FrameIndex operand!");
156  }
157
158  DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
159        errs() << "<--------->\n" << MI);
160
161  int FrameIndex = MI.getOperand(i).getIndex();
162  uint64_t stackSize = MF.getFrameInfo()->getStackSize();
163  int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
164
165  DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
166               << "spOffset   : " << spOffset << "\n"
167               << "stackSize  : " << stackSize << "\n");
168
169  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
170  int MinCSFI = 0;
171  int MaxCSFI = -1;
172
173  if (CSI.size()) {
174    MinCSFI = CSI[0].getFrameIdx();
175    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
176  }
177
178  // The following stack frame objects are always referenced relative to $sp:
179  //  1. Outgoing arguments.
180  //  2. Pointer to dynamically allocated stack space.
181  //  3. Locations for callee-saved registers.
182  // Everything else is referenced relative to whatever register
183  // getFrameRegister() returns.
184  unsigned FrameReg;
185
186  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
187      (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
188    FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
189  else
190    FrameReg = getFrameRegister(MF);
191
192  // Calculate final offset.
193  // - There is no need to change the offset if the frame object is one of the
194  //   following: an outgoing argument, pointer to a dynamically allocated
195  //   stack space or a $gp restore location,
196  // - If the frame object is any of the following, its offset must be adjusted
197  //   by adding the size of the stack:
198  //   incoming argument, callee-saved register location or local variable.
199  int64_t Offset;
200
201  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
202      MipsFI->isDynAllocFI(FrameIndex))
203    Offset = spOffset;
204  else
205    Offset = spOffset + (int64_t)stackSize;
206
207  Offset    += MI.getOperand(i+1).getImm();
208
209  DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
210
211  // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
212  // field.
213  if (!MI.isDebugValue() && !isInt<16>(Offset)) {
214    MachineBasicBlock &MBB = *MI.getParent();
215    DebugLoc DL = II->getDebugLoc();
216    MipsAnalyzeImmediate AnalyzeImm;
217    unsigned Size = Subtarget.isABI_N64() ? 64 : 32;
218    unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi;
219    unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
220    unsigned ZEROReg = Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
221    unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
222    const MipsAnalyzeImmediate::InstSeq &Seq =
223      AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
224    MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
225
226    // FIXME: change this when mips goes MC".
227    BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
228
229    // The first instruction can be a LUi, which is different from other
230    // instructions (ADDiu, ORI and SLL) in that it does not have a register
231    // operand.
232    if (Inst->Opc == LUi)
233      BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
234        .addImm(SignExtend64<16>(Inst->ImmOpnd));
235    else
236      BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
237        .addImm(SignExtend64<16>(Inst->ImmOpnd));
238
239    // Build the remaining instructions in Seq except for the last one.
240    for (++Inst; Inst != Seq.end() - 1; ++Inst)
241      BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
242        .addImm(SignExtend64<16>(Inst->ImmOpnd));
243
244    BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg);
245
246    FrameReg = ATReg;
247    Offset = SignExtend64<16>(Inst->ImmOpnd);
248    BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
249  }
250
251  MI.getOperand(i).ChangeToRegister(FrameReg, false);
252  MI.getOperand(i+1).ChangeToImmediate(Offset);
253}
254
255unsigned MipsRegisterInfo::
256getFrameRegister(const MachineFunction &MF) const {
257  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
258  bool IsN64 = Subtarget.isABI_N64();
259
260  return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
261                          (IsN64 ? Mips::SP_64 : Mips::SP);
262}
263
264unsigned MipsRegisterInfo::
265getEHExceptionRegister() const {
266  llvm_unreachable("What is the exception register");
267}
268
269unsigned MipsRegisterInfo::
270getEHHandlerRegister() const {
271  llvm_unreachable("What is the exception handler register");
272}
273