MipsRegisterInfo.cpp revision 81a424b3c5e7be03d66d5c7fd241f2aac47d1a2c
1//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MIPS implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-reg-info" 15 16#include "MipsRegisterInfo.h" 17#include "Mips.h" 18#include "MipsAnalyzeImmediate.h" 19#include "MipsSubtarget.h" 20#include "MipsMachineFunction.h" 21#include "llvm/Constants.h" 22#include "llvm/Type.h" 23#include "llvm/Function.h" 24#include "llvm/CodeGen/ValueTypes.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/Target/TargetFrameLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/BitVector.h" 37#include "llvm/ADT/STLExtras.h" 38#include "llvm/Analysis/DebugInfo.h" 39 40#define GET_REGINFO_TARGET_DESC 41#include "MipsGenRegisterInfo.inc" 42 43using namespace llvm; 44 45MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, 46 const TargetInstrInfo &tii) 47 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {} 48 49unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 50 51//===----------------------------------------------------------------------===// 52// Callee Saved Registers methods 53//===----------------------------------------------------------------------===// 54 55/// Mips Callee Saved Registers 56const uint16_t* MipsRegisterInfo:: 57getCalleeSavedRegs(const MachineFunction *MF) const 58{ 59 if (Subtarget.isSingleFloat()) 60 return CSR_SingleFloatOnly_SaveList; 61 else if (!Subtarget.hasMips64()) 62 return CSR_O32_SaveList; 63 else if (Subtarget.isABI_N32()) 64 return CSR_N32_SaveList; 65 66 assert(Subtarget.isABI_N64()); 67 return CSR_N64_SaveList; 68} 69 70const uint32_t* 71MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const 72{ 73 if (Subtarget.isSingleFloat()) 74 return CSR_SingleFloatOnly_RegMask; 75 else if (!Subtarget.hasMips64()) 76 return CSR_O32_RegMask; 77 else if (Subtarget.isABI_N32()) 78 return CSR_N32_RegMask; 79 80 assert(Subtarget.isABI_N64()); 81 return CSR_N64_RegMask; 82} 83 84BitVector MipsRegisterInfo:: 85getReservedRegs(const MachineFunction &MF) const { 86 static const uint16_t ReservedCPURegs[] = { 87 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, 88 Mips::SP, Mips::FP, Mips::RA 89 }; 90 91 static const uint16_t ReservedCPU64Regs[] = { 92 Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64, 93 Mips::SP_64, Mips::FP_64, Mips::RA_64 94 }; 95 96 BitVector Reserved(getNumRegs()); 97 typedef TargetRegisterClass::iterator RegIter; 98 99 for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I) 100 Reserved.set(ReservedCPURegs[I]); 101 102 if (Subtarget.hasMips64()) { 103 for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I) 104 Reserved.set(ReservedCPU64Regs[I]); 105 106 // Reserve all registers in AFGR64. 107 for (RegIter Reg = Mips::AFGR64RegisterClass->begin(); 108 Reg != Mips::AFGR64RegisterClass->end(); ++Reg) 109 Reserved.set(*Reg); 110 } 111 else { 112 // Reserve all registers in CPU64Regs & FGR64. 113 for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin(); 114 Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg) 115 Reserved.set(*Reg); 116 117 for (RegIter Reg = Mips::FGR64RegisterClass->begin(); 118 Reg != Mips::FGR64RegisterClass->end(); ++Reg) 119 Reserved.set(*Reg); 120 } 121 122 // If GP is dedicated as a global base register, reserve it. 123 if (MF.getInfo<MipsFunctionInfo>()->globalBaseRegFixed()) { 124 Reserved.set(Mips::GP); 125 Reserved.set(Mips::GP_64); 126 } 127 128 // Reserve hardware registers. 129 Reserved.set(Mips::HWR29); 130 Reserved.set(Mips::HWR29_64); 131 132 return Reserved; 133} 134 135bool 136MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 137 return true; 138} 139 140// This function eliminate ADJCALLSTACKDOWN, 141// ADJCALLSTACKUP pseudo instructions 142void MipsRegisterInfo:: 143eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 144 MachineBasicBlock::iterator I) const { 145 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 146 MBB.erase(I); 147} 148 149// FrameIndex represent objects inside a abstract stack. 150// We must replace FrameIndex with an stack/frame pointer 151// direct reference. 152void MipsRegisterInfo:: 153eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 154 RegScavenger *RS) const { 155 MachineInstr &MI = *II; 156 MachineFunction &MF = *MI.getParent()->getParent(); 157 MachineFrameInfo *MFI = MF.getFrameInfo(); 158 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 159 160 unsigned i = 0; 161 while (!MI.getOperand(i).isFI()) { 162 ++i; 163 assert(i < MI.getNumOperands() && 164 "Instr doesn't have FrameIndex operand!"); 165 } 166 167 DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n"; 168 errs() << "<--------->\n" << MI); 169 170 int FrameIndex = MI.getOperand(i).getIndex(); 171 uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 172 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 173 174 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 175 << "spOffset : " << spOffset << "\n" 176 << "stackSize : " << stackSize << "\n"); 177 178 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 179 int MinCSFI = 0; 180 int MaxCSFI = -1; 181 182 if (CSI.size()) { 183 MinCSFI = CSI[0].getFrameIdx(); 184 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); 185 } 186 187 // The following stack frame objects are always referenced relative to $sp: 188 // 1. Outgoing arguments. 189 // 2. Pointer to dynamically allocated stack space. 190 // 3. Locations for callee-saved registers. 191 // Everything else is referenced relative to whatever register 192 // getFrameRegister() returns. 193 unsigned FrameReg; 194 195 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) || 196 (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) 197 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 198 else 199 FrameReg = getFrameRegister(MF); 200 201 // Calculate final offset. 202 // - There is no need to change the offset if the frame object is one of the 203 // following: an outgoing argument, pointer to a dynamically allocated 204 // stack space or a $gp restore location, 205 // - If the frame object is any of the following, its offset must be adjusted 206 // by adding the size of the stack: 207 // incoming argument, callee-saved register location or local variable. 208 int64_t Offset; 209 210 if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) || 211 MipsFI->isDynAllocFI(FrameIndex)) 212 Offset = spOffset; 213 else 214 Offset = spOffset + (int64_t)stackSize; 215 216 Offset += MI.getOperand(i+1).getImm(); 217 218 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); 219 220 // If MI is not a debug value, make sure Offset fits in the 16-bit immediate 221 // field. 222 if (!MI.isDebugValue() && !isInt<16>(Offset)) { 223 MachineBasicBlock &MBB = *MI.getParent(); 224 DebugLoc DL = II->getDebugLoc(); 225 MipsAnalyzeImmediate AnalyzeImm; 226 unsigned Size = Subtarget.isABI_N64() ? 64 : 32; 227 unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi; 228 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; 229 unsigned ZEROReg = Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 230 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT; 231 const MipsAnalyzeImmediate::InstSeq &Seq = 232 AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */); 233 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 234 235 MipsFI->setEmitNOAT(); 236 237 // The first instruction can be a LUi, which is different from other 238 // instructions (ADDiu, ORI and SLL) in that it does not have a register 239 // operand. 240 if (Inst->Opc == LUi) 241 BuildMI(MBB, II, DL, TII.get(LUi), ATReg) 242 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 243 else 244 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg) 245 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 246 247 // Build the remaining instructions in Seq except for the last one. 248 for (++Inst; Inst != Seq.end() - 1; ++Inst) 249 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg) 250 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 251 252 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg); 253 254 FrameReg = ATReg; 255 Offset = SignExtend64<16>(Inst->ImmOpnd); 256 } 257 258 MI.getOperand(i).ChangeToRegister(FrameReg, false); 259 MI.getOperand(i+1).ChangeToImmediate(Offset); 260} 261 262unsigned MipsRegisterInfo:: 263getFrameRegister(const MachineFunction &MF) const { 264 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 265 bool IsN64 = Subtarget.isABI_N64(); 266 267 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 268 (IsN64 ? Mips::SP_64 : Mips::SP); 269} 270 271unsigned MipsRegisterInfo:: 272getEHExceptionRegister() const { 273 llvm_unreachable("What is the exception register"); 274} 275 276unsigned MipsRegisterInfo:: 277getEHHandlerRegister() const { 278 llvm_unreachable("What is the exception handler register"); 279} 280