MipsRegisterInfo.cpp revision b1dcff0fe372d6a691f37413a24d5a6564f1a361 
1//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-reg-info"
15
16#include "Mips.h"
17#include "MipsSubtarget.h"
18#include "MipsRegisterInfo.h"
19#include "MipsMachineFunction.h"
20#include "llvm/Constants.h"
21#include "llvm/Type.h"
22#include "llvm/Function.h"
23#include "llvm/CodeGen/ValueTypes.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/Target/TargetFrameLowering.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetOptions.h"
30#include "llvm/Target/TargetInstrInfo.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/ADT/BitVector.h"
36#include "llvm/ADT/STLExtras.h"
37#include "llvm/Analysis/DebugInfo.h"
38
39#define GET_REGINFO_TARGET_DESC
40#include "MipsGenRegisterInfo.inc"
41
42using namespace llvm;
43
44MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
45                                   const TargetInstrInfo &tii)
46  : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
47
48/// getRegisterNumbering - Given the enum value for some register, e.g.
49/// Mips::RA, return the number that it corresponds to (e.g. 31).
50unsigned MipsRegisterInfo::
51getRegisterNumbering(unsigned RegEnum)
52{
53  switch (RegEnum) {
54    case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
55    case Mips::AT   : case Mips::F1 : return 1;
56    case Mips::V0   : case Mips::F2 : case Mips::D1 : return 2;
57    case Mips::V1   : case Mips::F3 : return 3;
58    case Mips::A0   : case Mips::F4 : case Mips::D2 : return 4;
59    case Mips::A1   : case Mips::F5 : return 5;
60    case Mips::A2   : case Mips::F6 : case Mips::D3 : return 6;
61    case Mips::A3   : case Mips::F7 : return 7;
62    case Mips::T0   : case Mips::F8 : case Mips::D4 : return 8;
63    case Mips::T1   : case Mips::F9 : return 9;
64    case Mips::T2   : case Mips::F10: case Mips::D5: return 10;
65    case Mips::T3   : case Mips::F11: return 11;
66    case Mips::T4   : case Mips::F12: case Mips::D6: return 12;
67    case Mips::T5   : case Mips::F13: return 13;
68    case Mips::T6   : case Mips::F14: case Mips::D7: return 14;
69    case Mips::T7   : case Mips::F15: return 15;
70    case Mips::S0   : case Mips::F16: case Mips::D8: return 16;
71    case Mips::S1   : case Mips::F17: return 17;
72    case Mips::S2   : case Mips::F18: case Mips::D9: return 18;
73    case Mips::S3   : case Mips::F19: return 19;
74    case Mips::S4   : case Mips::F20: case Mips::D10: return 20;
75    case Mips::S5   : case Mips::F21: return 21;
76    case Mips::S6   : case Mips::F22: case Mips::D11: return 22;
77    case Mips::S7   : case Mips::F23: return 23;
78    case Mips::T8   : case Mips::F24: case Mips::D12: return 24;
79    case Mips::T9   : case Mips::F25: return 25;
80    case Mips::K0   : case Mips::F26: case Mips::D13: return 26;
81    case Mips::K1   : case Mips::F27: return 27;
82    case Mips::GP   : case Mips::F28: case Mips::D14: return 28;
83    case Mips::SP   : case Mips::F29: return 29;
84    case Mips::FP   : case Mips::F30: case Mips::D15: return 30;
85    case Mips::RA   : case Mips::F31: return 31;
86    default: llvm_unreachable("Unknown register number!");
87  }
88  return 0; // Not reached
89}
90
91unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
92
93//===----------------------------------------------------------------------===//
94// Callee Saved Registers methods
95//===----------------------------------------------------------------------===//
96
97/// Mips Callee Saved Registers
98const unsigned* MipsRegisterInfo::
99getCalleeSavedRegs(const MachineFunction *MF) const
100{
101  // Mips callee-save register range is $16-$23, $f20-$f30
102  static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
103    Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
104    Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
105    Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
106    Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
107  };
108
109  static const unsigned Mips32CalleeSavedRegs[] = {
110    Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
111    Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
112    Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
113  };
114
115  static const unsigned N32CalleeSavedRegs[] = {
116    Mips::D31_64, Mips::D29_64, Mips::D27_64, Mips::D25_64, Mips::D23_64,
117    Mips::D21_64,
118    Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
119    Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
120    Mips::S0_64, 0
121  };
122
123  static const unsigned N64CalleeSavedRegs[] = {
124    Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64,
125    Mips::D26_64, Mips::D25_64, Mips::D24_64,
126    Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
127    Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
128    Mips::S0_64, 0
129  };
130
131  if (Subtarget.isSingleFloat())
132    return SingleFloatOnlyCalleeSavedRegs;
133  else if (!Subtarget.hasMips64())
134    return Mips32CalleeSavedRegs;
135  else if (Subtarget.isABI_N32())
136    return N32CalleeSavedRegs;
137
138  assert(Subtarget.isABI_N64());
139  return N64CalleeSavedRegs;
140}
141
142BitVector MipsRegisterInfo::
143getReservedRegs(const MachineFunction &MF) const {
144  static const unsigned ReservedCPURegs[] = {
145    Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
146    Mips::GP, Mips::SP, Mips::FP, Mips::RA, 0
147  };
148
149  static const unsigned ReservedCPU64Regs[] = {
150    Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
151    Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 0
152  };
153
154  BitVector Reserved(getNumRegs());
155  typedef TargetRegisterClass::iterator RegIter;
156
157  for (const unsigned *Reg = ReservedCPURegs; *Reg; ++Reg)
158    Reserved.set(*Reg);
159
160  if (Subtarget.hasMips64()) {
161    for (const unsigned *Reg = ReservedCPU64Regs; *Reg; ++Reg)
162      Reserved.set(*Reg);
163
164    // Reserve all registers in AFGR64.
165    for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
166         Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
167      Reserved.set(*Reg);
168  }
169  else {
170    // Reserve all registers in CPU64Regs & FGR64.
171    for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
172         Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
173      Reserved.set(*Reg);
174
175    for (RegIter Reg = Mips::FGR64RegisterClass->begin();
176         Reg != Mips::FGR64RegisterClass->end(); ++Reg)
177      Reserved.set(*Reg);
178  }
179
180  return Reserved;
181}
182
183// This function eliminate ADJCALLSTACKDOWN,
184// ADJCALLSTACKUP pseudo instructions
185void MipsRegisterInfo::
186eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
187                              MachineBasicBlock::iterator I) const {
188  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
189  MBB.erase(I);
190}
191
192// FrameIndex represent objects inside a abstract stack.
193// We must replace FrameIndex with an stack/frame pointer
194// direct reference.
195void MipsRegisterInfo::
196eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
197                    RegScavenger *RS) const {
198  MachineInstr &MI = *II;
199  MachineFunction &MF = *MI.getParent()->getParent();
200  MachineFrameInfo *MFI = MF.getFrameInfo();
201  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
202
203  unsigned i = 0;
204  while (!MI.getOperand(i).isFI()) {
205    ++i;
206    assert(i < MI.getNumOperands() &&
207           "Instr doesn't have FrameIndex operand!");
208  }
209
210  DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
211        errs() << "<--------->\n" << MI);
212
213  int FrameIndex = MI.getOperand(i).getIndex();
214  int stackSize  = MF.getFrameInfo()->getStackSize();
215  int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
216
217  DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
218               << "spOffset   : " << spOffset << "\n"
219               << "stackSize  : " << stackSize << "\n");
220
221  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
222  int MinCSFI = 0;
223  int MaxCSFI = -1;
224
225  if (CSI.size()) {
226    MinCSFI = CSI[0].getFrameIdx();
227    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
228  }
229
230  // The following stack frame objects are always referenced relative to $sp:
231  //  1. Outgoing arguments.
232  //  2. Pointer to dynamically allocated stack space.
233  //  3. Locations for callee-saved registers.
234  // Everything else is referenced relative to whatever register
235  // getFrameRegister() returns.
236  unsigned FrameReg;
237
238  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
239      (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
240    FrameReg = Mips::SP;
241  else
242    FrameReg = getFrameRegister(MF);
243
244  // Calculate final offset.
245  // - There is no need to change the offset if the frame object is one of the
246  //   following: an outgoing argument, pointer to a dynamically allocated
247  //   stack space or a $gp restore location,
248  // - If the frame object is any of the following, its offset must be adjusted
249  //   by adding the size of the stack:
250  //   incoming argument, callee-saved register location or local variable.
251  int Offset;
252
253  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
254      MipsFI->isDynAllocFI(FrameIndex))
255    Offset = spOffset;
256  else
257    Offset = spOffset + stackSize;
258
259  Offset    += MI.getOperand(i+1).getImm();
260
261  DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
262
263  // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
264  // field.
265  if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
266    MachineBasicBlock &MBB = *MI.getParent();
267    DebugLoc DL = II->getDebugLoc();
268    int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
269                ((Offset & 0x8000) != 0);
270
271    // FIXME: change this when mips goes MC".
272    BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
273    BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
274    BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
275                                                       .addReg(Mips::AT);
276    FrameReg = Mips::AT;
277    Offset = (short)(Offset & 0xffff);
278
279    BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
280  }
281
282  MI.getOperand(i).ChangeToRegister(FrameReg, false);
283  MI.getOperand(i+1).ChangeToImmediate(Offset);
284}
285
286unsigned MipsRegisterInfo::
287getFrameRegister(const MachineFunction &MF) const {
288  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
289
290  return TFI->hasFP(MF) ? Mips::FP : Mips::SP;
291}
292
293unsigned MipsRegisterInfo::
294getEHExceptionRegister() const {
295  llvm_unreachable("What is the exception register");
296  return 0;
297}
298
299unsigned MipsRegisterInfo::
300getEHHandlerRegister() const {
301  llvm_unreachable("What is the exception handler register");
302  return 0;
303}
304