MipsRegisterInfo.cpp revision c23197a26f34f559ea9797de51e187087c039c42
1//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MIPS implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "mips-reg-info" 15 16#include "Mips.h" 17#include "MipsSubtarget.h" 18#include "MipsRegisterInfo.h" 19#include "MipsMachineFunction.h" 20#include "llvm/Constants.h" 21#include "llvm/Type.h" 22#include "llvm/Function.h" 23#include "llvm/CodeGen/ValueTypes.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineLocation.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/ADT/BitVector.h" 36#include "llvm/ADT/STLExtras.h" 37 38using namespace llvm; 39 40MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, 41 const TargetInstrInfo &tii) 42 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), 43 Subtarget(ST), TII(tii) {} 44 45/// getRegisterNumbering - Given the enum value for some register, e.g. 46/// Mips::RA, return the number that it corresponds to (e.g. 31). 47unsigned MipsRegisterInfo:: 48getRegisterNumbering(unsigned RegEnum) 49{ 50 switch (RegEnum) { 51 case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0; 52 case Mips::AT : case Mips::F1 : return 1; 53 case Mips::V0 : case Mips::F2 : case Mips::D1 : return 2; 54 case Mips::V1 : case Mips::F3 : return 3; 55 case Mips::A0 : case Mips::F4 : case Mips::D2 : return 4; 56 case Mips::A1 : case Mips::F5 : return 5; 57 case Mips::A2 : case Mips::F6 : case Mips::D3 : return 6; 58 case Mips::A3 : case Mips::F7 : return 7; 59 case Mips::T0 : case Mips::F8 : case Mips::D4 : return 8; 60 case Mips::T1 : case Mips::F9 : return 9; 61 case Mips::T2 : case Mips::F10: case Mips::D5: return 10; 62 case Mips::T3 : case Mips::F11: return 11; 63 case Mips::T4 : case Mips::F12: case Mips::D6: return 12; 64 case Mips::T5 : case Mips::F13: return 13; 65 case Mips::T6 : case Mips::F14: case Mips::D7: return 14; 66 case Mips::T7 : case Mips::F15: return 15; 67 case Mips::T8 : case Mips::F16: case Mips::D8: return 16; 68 case Mips::T9 : case Mips::F17: return 17; 69 case Mips::S0 : case Mips::F18: case Mips::D9: return 18; 70 case Mips::S1 : case Mips::F19: return 19; 71 case Mips::S2 : case Mips::F20: case Mips::D10: return 20; 72 case Mips::S3 : case Mips::F21: return 21; 73 case Mips::S4 : case Mips::F22: case Mips::D11: return 22; 74 case Mips::S5 : case Mips::F23: return 23; 75 case Mips::S6 : case Mips::F24: case Mips::D12: return 24; 76 case Mips::S7 : case Mips::F25: return 25; 77 case Mips::K0 : case Mips::F26: case Mips::D13: return 26; 78 case Mips::K1 : case Mips::F27: return 27; 79 case Mips::GP : case Mips::F28: case Mips::D14: return 28; 80 case Mips::SP : case Mips::F29: return 29; 81 case Mips::FP : case Mips::F30: case Mips::D15: return 30; 82 case Mips::RA : case Mips::F31: return 31; 83 default: llvm_unreachable("Unknown register number!"); 84 } 85 return 0; // Not reached 86} 87 88unsigned MipsRegisterInfo::getPICCallReg(void) { return Mips::T9; } 89 90//===----------------------------------------------------------------------===// 91// Callee Saved Registers methods 92//===----------------------------------------------------------------------===// 93 94/// Mips Callee Saved Registers 95const unsigned* MipsRegisterInfo:: 96getCalleeSavedRegs(const MachineFunction *MF) const 97{ 98 // Mips callee-save register range is $16-$23, $f20-$f30 99 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = { 100 Mips::S0, Mips::S1, Mips::S2, Mips::S3, 101 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 102 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, 103 Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0 104 }; 105 106 static const unsigned BitMode32CalleeSavedRegs[] = { 107 Mips::S0, Mips::S1, Mips::S2, Mips::S3, 108 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 109 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 110 Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,0 111 }; 112 113 if (Subtarget.isSingleFloat()) 114 return SingleFloatOnlyCalleeSavedRegs; 115 else 116 return BitMode32CalleeSavedRegs; 117} 118 119/// Mips Callee Saved Register Classes 120const TargetRegisterClass* const* 121MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const 122{ 123 static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = { 124 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 125 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 126 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 127 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 128 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 129 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 130 &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0 131 }; 132 133 static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = { 134 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 135 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 136 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 137 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 138 &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass, 139 &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, 140 &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, 0 141 }; 142 143 if (Subtarget.isSingleFloat()) 144 return SingleFloatOnlyCalleeSavedRC; 145 else 146 return BitMode32CalleeSavedRC; 147} 148 149BitVector MipsRegisterInfo:: 150getReservedRegs(const MachineFunction &MF) const 151{ 152 BitVector Reserved(getNumRegs()); 153 Reserved.set(Mips::ZERO); 154 Reserved.set(Mips::AT); 155 Reserved.set(Mips::K0); 156 Reserved.set(Mips::K1); 157 Reserved.set(Mips::GP); 158 Reserved.set(Mips::SP); 159 Reserved.set(Mips::FP); 160 Reserved.set(Mips::RA); 161 162 // SRV4 requires that odd register can't be used. 163 if (!Subtarget.isSingleFloat()) 164 for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2) 165 Reserved.set(FReg); 166 167 return Reserved; 168} 169 170//===----------------------------------------------------------------------===// 171// 172// Stack Frame Processing methods 173// +----------------------------+ 174// 175// The stack is allocated decrementing the stack pointer on 176// the first instruction of a function prologue. Once decremented, 177// all stack referencesare are done thought a positive offset 178// from the stack/frame pointer, so the stack is considering 179// to grow up! Otherwise terrible hacks would have to be made 180// to get this stack ABI compliant :) 181// 182// The stack frame required by the ABI (after call): 183// Offset 184// 185// 0 ---------- 186// 4 Args to pass 187// . saved $GP (used in PIC) 188// . Alloca allocations 189// . Local Area 190// . CPU "Callee Saved" Registers 191// . saved FP 192// . saved RA 193// . FPU "Callee Saved" Registers 194// StackSize ----------- 195// 196// Offset - offset from sp after stack allocation on function prologue 197// 198// The sp is the stack pointer subtracted/added from the stack size 199// at the Prologue/Epilogue 200// 201// References to the previous stack (to obtain arguments) are done 202// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) 203// 204// Examples: 205// - reference to the actual stack frame 206// for any local area var there is smt like : FI >= 0, StackOffset: 4 207// sw REGX, 4(SP) 208// 209// - reference to previous stack frame 210// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. 211// The emitted instruction will be something like: 212// lw REGX, 16+StackSize(SP) 213// 214// Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all 215// stack references (ObjectOffset) created to reference the function 216// arguments, are negative numbers. This way, on eliminateFrameIndex it's 217// possible to detect those references and the offsets are adjusted to 218// their real location. 219// 220//===----------------------------------------------------------------------===// 221 222void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const 223{ 224 MachineFrameInfo *MFI = MF.getFrameInfo(); 225 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 226 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 227 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 228 229 // Min and Max CSI FrameIndex. 230 int MinCSFI = -1, MaxCSFI = -1; 231 232 // See the description at MipsMachineFunction.h 233 int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1; 234 235 // Replace the dummy '0' SPOffset by the negative offsets, as explained on 236 // LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid 237 // the approach done by calculateFrameObjectOffsets to the stack frame. 238 MipsFI->adjustLoadArgsFI(MFI); 239 MipsFI->adjustStoreVarArgsFI(MFI); 240 241 // It happens that the default stack frame allocation order does not directly 242 // map to the convention used for mips. So we must fix it. We move the callee 243 // save register slots after the local variables area, as described in the 244 // stack frame above. 245 unsigned CalleeSavedAreaSize = 0; 246 if (!CSI.empty()) { 247 MinCSFI = CSI[0].getFrameIdx(); 248 MaxCSFI = CSI[CSI.size()-1].getFrameIdx(); 249 } 250 for (unsigned i = 0, e = CSI.size(); i != e; ++i) 251 CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx()); 252 253 // Adjust local variables. They should come on the stack right 254 // after the arguments. 255 int LastOffsetFI = -1; 256 for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { 257 if (i >= MinCSFI && i <= MaxCSFI) 258 continue; 259 if (MFI->isDeadObjectIndex(i)) 260 continue; 261 unsigned Offset = MFI->getObjectOffset(i) - CalleeSavedAreaSize; 262 if (LastOffsetFI == -1) 263 LastOffsetFI = i; 264 if (Offset > MFI->getObjectOffset(LastOffsetFI)) 265 LastOffsetFI = i; 266 MFI->setObjectOffset(i, Offset); 267 } 268 269 // Adjust CPU Callee Saved Registers Area. Registers RA and FP must 270 // be saved in this CPU Area there is the need. This whole Area must 271 // be aligned to the default Stack Alignment requirements. 272 unsigned StackOffset = 0; 273 unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8; 274 275 if (LastOffsetFI >= 0) 276 StackOffset = MFI->getObjectOffset(LastOffsetFI)+ 277 MFI->getObjectSize(LastOffsetFI); 278 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); 279 280 for (unsigned i = 0, e = CSI.size(); i != e ; ++i) { 281 if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass) 282 break; 283 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset); 284 TopCPUSavedRegOff = StackOffset; 285 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx()); 286 } 287 288 if (hasFP(MF)) { 289 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize), 290 StackOffset); 291 MipsFI->setFPStackOffset(StackOffset); 292 TopCPUSavedRegOff = StackOffset; 293 StackOffset += RegSize; 294 } 295 296 if (MFI->hasCalls()) { 297 MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize), 298 StackOffset); 299 MipsFI->setRAStackOffset(StackOffset); 300 TopCPUSavedRegOff = StackOffset; 301 StackOffset += RegSize; 302 } 303 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); 304 305 // Adjust FPU Callee Saved Registers Area. This Area must be 306 // aligned to the default Stack Alignment requirements. 307 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 308 if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass) 309 continue; 310 MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset); 311 TopFPUSavedRegOff = StackOffset; 312 StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx()); 313 } 314 StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); 315 316 // Update frame info 317 MFI->setStackSize(StackOffset); 318 319 // Recalculate the final tops offset. The final values must be '0' 320 // if there isn't a callee saved register for CPU or FPU, otherwise 321 // a negative offset is needed. 322 if (TopCPUSavedRegOff >= 0) 323 MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset); 324 325 if (TopFPUSavedRegOff >= 0) 326 MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset); 327} 328 329// hasFP - Return true if the specified function should have a dedicated frame 330// pointer register. This is true if the function has variable sized allocas or 331// if frame pointer elimination is disabled. 332bool MipsRegisterInfo:: 333hasFP(const MachineFunction &MF) const { 334 const MachineFrameInfo *MFI = MF.getFrameInfo(); 335 return NoFramePointerElim || MFI->hasVarSizedObjects(); 336} 337 338// This function eliminate ADJCALLSTACKDOWN, 339// ADJCALLSTACKUP pseudo instructions 340void MipsRegisterInfo:: 341eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 342 MachineBasicBlock::iterator I) const { 343 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 344 MBB.erase(I); 345} 346 347// FrameIndex represent objects inside a abstract stack. 348// We must replace FrameIndex with an stack/frame pointer 349// direct reference. 350void MipsRegisterInfo:: 351eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 352 RegScavenger *RS) const 353{ 354 MachineInstr &MI = *II; 355 MachineFunction &MF = *MI.getParent()->getParent(); 356 357 unsigned i = 0; 358 while (!MI.getOperand(i).isFI()) { 359 ++i; 360 assert(i < MI.getNumOperands() && 361 "Instr doesn't have FrameIndex operand!"); 362 } 363 364 #ifndef NDEBUG 365 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n"; 366 DOUT << "<--------->\n"; 367 MI.print(DOUT); 368 #endif 369 370 int FrameIndex = MI.getOperand(i).getIndex(); 371 int stackSize = MF.getFrameInfo()->getStackSize(); 372 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 373 374 #ifndef NDEBUG 375 DOUT << "FrameIndex : " << FrameIndex << "\n"; 376 DOUT << "spOffset : " << spOffset << "\n"; 377 DOUT << "stackSize : " << stackSize << "\n"; 378 #endif 379 380 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets 381 // and adjust SPOffsets considering the final stack size. 382 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset)); 383 Offset += MI.getOperand(i-1).getImm(); 384 385 #ifndef NDEBUG 386 DOUT << "Offset : " << Offset << "\n"; 387 DOUT << "<--------->\n"; 388 #endif 389 390 MI.getOperand(i-1).ChangeToImmediate(Offset); 391 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false); 392} 393 394void MipsRegisterInfo:: 395emitPrologue(MachineFunction &MF) const 396{ 397 MachineBasicBlock &MBB = MF.front(); 398 MachineFrameInfo *MFI = MF.getFrameInfo(); 399 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 400 MachineBasicBlock::iterator MBBI = MBB.begin(); 401 DebugLoc dl = (MBBI != MBB.end() ? 402 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 403 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); 404 405 // Get the right frame order for Mips. 406 adjustMipsStackFrame(MF); 407 408 // Get the number of bytes to allocate from the FrameInfo. 409 unsigned StackSize = MFI->getStackSize(); 410 411 // No need to allocate space on the stack. 412 if (StackSize == 0 && !MFI->hasCalls()) return; 413 414 int FPOffset = MipsFI->getFPStackOffset(); 415 int RAOffset = MipsFI->getRAStackOffset(); 416 417 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); 418 419 // TODO: check need from GP here. 420 if (isPIC && Subtarget.isABI_O32()) 421 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg()); 422 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); 423 424 // Adjust stack : addi sp, sp, (-imm) 425 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) 426 .addReg(Mips::SP).addImm(-StackSize); 427 428 // Save the return address only if the function isnt a leaf one. 429 // sw $ra, stack_loc($sp) 430 if (MFI->hasCalls()) { 431 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) 432 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); 433 } 434 435 // if framepointer enabled, save it and set it 436 // to point to the stack pointer 437 if (hasFP(MF)) { 438 // sw $fp,stack_loc($sp) 439 BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) 440 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP); 441 442 // move $fp, $sp 443 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP) 444 .addReg(Mips::SP).addReg(Mips::ZERO); 445 } 446 447 // PIC speficic function prologue 448 if ((isPIC) && (MFI->hasCalls())) { 449 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)) 450 .addImm(MipsFI->getGPStackOffset()); 451 } 452} 453 454void MipsRegisterInfo:: 455emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const 456{ 457 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 458 MachineFrameInfo *MFI = MF.getFrameInfo(); 459 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 460 DebugLoc dl = MBBI->getDebugLoc(); 461 462 // Get the number of bytes from FrameInfo 463 int NumBytes = (int) MFI->getStackSize(); 464 465 // Get the FI's where RA and FP are saved. 466 int FPOffset = MipsFI->getFPStackOffset(); 467 int RAOffset = MipsFI->getRAStackOffset(); 468 469 // if framepointer enabled, restore it and restore the 470 // stack pointer 471 if (hasFP(MF)) { 472 // move $sp, $fp 473 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP) 474 .addReg(Mips::FP).addReg(Mips::ZERO); 475 476 // lw $fp,stack_loc($sp) 477 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP) 478 .addImm(FPOffset).addReg(Mips::SP); 479 } 480 481 // Restore the return address only if the function isnt a leaf one. 482 // lw $ra, stack_loc($sp) 483 if (MFI->hasCalls()) { 484 BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA) 485 .addImm(RAOffset).addReg(Mips::SP); 486 } 487 488 // adjust stack : insert addi sp, sp, (imm) 489 if (NumBytes) { 490 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) 491 .addReg(Mips::SP).addImm(NumBytes); 492 } 493} 494 495 496void MipsRegisterInfo:: 497processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 498 // Set the SPOffset on the FI where GP must be saved/loaded. 499 MachineFrameInfo *MFI = MF.getFrameInfo(); 500 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); 501 if (MFI->hasCalls() && isPIC) { 502 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 503 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset()); 504 } 505} 506 507unsigned MipsRegisterInfo:: 508getRARegister() const { 509 return Mips::RA; 510} 511 512unsigned MipsRegisterInfo:: 513getFrameRegister(MachineFunction &MF) const { 514 return hasFP(MF) ? Mips::FP : Mips::SP; 515} 516 517unsigned MipsRegisterInfo:: 518getEHExceptionRegister() const { 519 llvm_unreachable("What is the exception register"); 520 return 0; 521} 522 523unsigned MipsRegisterInfo:: 524getEHHandlerRegister() const { 525 llvm_unreachable("What is the exception handler register"); 526 return 0; 527} 528 529int MipsRegisterInfo:: 530getDwarfRegNum(unsigned RegNum, bool isEH) const { 531 llvm_unreachable("What is the dwarf register number"); 532 return -1; 533} 534 535#include "MipsGenRegisterInfo.inc" 536 537