MipsSEISelLowering.cpp revision 3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36
37  clearRegisterClasses();
38
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP()) {
45    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
46
47    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
49
50      // Expand all builtin opcodes.
51      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52        setOperationAction(Opc, VecTys[i], Expand);
53
54      setOperationAction(ISD::ADD, VecTys[i], Legal);
55      setOperationAction(ISD::SUB, VecTys[i], Legal);
56      setOperationAction(ISD::LOAD, VecTys[i], Legal);
57      setOperationAction(ISD::STORE, VecTys[i], Legal);
58      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
59    }
60
61    // Expand all truncating stores and extending loads.
62    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
64
65    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67        setTruncStoreAction((MVT::SimpleValueType)VT0,
68                            (MVT::SimpleValueType)VT1, Expand);
69
70      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
73    }
74
75    setTargetDAGCombine(ISD::SHL);
76    setTargetDAGCombine(ISD::SRA);
77    setTargetDAGCombine(ISD::SRL);
78    setTargetDAGCombine(ISD::SETCC);
79    setTargetDAGCombine(ISD::VSELECT);
80  }
81
82  if (Subtarget->hasDSPR2())
83    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84
85  if (Subtarget->hasMSA()) {
86    addMSAType(MVT::v16i8, &Mips::MSA128BRegClass);
87    addMSAType(MVT::v8i16, &Mips::MSA128HRegClass);
88    addMSAType(MVT::v4i32, &Mips::MSA128WRegClass);
89    addMSAType(MVT::v2i64, &Mips::MSA128DRegClass);
90    addMSAType(MVT::v8f16, &Mips::MSA128HRegClass);
91    addMSAType(MVT::v4f32, &Mips::MSA128WRegClass);
92    addMSAType(MVT::v2f64, &Mips::MSA128DRegClass);
93  }
94
95  if (!Subtarget->mipsSEUsesSoftFloat()) {
96    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
97
98    // When dealing with single precision only, use libcalls
99    if (!Subtarget->isSingleFloat()) {
100      if (Subtarget->isFP64bit())
101        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
102      else
103        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
104    }
105  }
106
107  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
108  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
109  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
110  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
111
112  if (HasMips64) {
113    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
114    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
115    setOperationAction(ISD::MUL,              MVT::i64, Custom);
116  }
117
118  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
119  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
120
121  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
122  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
123  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
124  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
125  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
126  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
127  setOperationAction(ISD::STORE,              MVT::i32, Custom);
128
129  setTargetDAGCombine(ISD::ADDE);
130  setTargetDAGCombine(ISD::SUBE);
131  setTargetDAGCombine(ISD::MUL);
132
133  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
135  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
136
137  if (NoDPLoadStore) {
138    setOperationAction(ISD::LOAD, MVT::f64, Custom);
139    setOperationAction(ISD::STORE, MVT::f64, Custom);
140  }
141
142  computeRegisterProperties();
143}
144
145const MipsTargetLowering *
146llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
147  return new MipsSETargetLowering(TM);
148}
149
150void MipsSETargetLowering::
151addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
152  addRegisterClass(Ty, RC);
153
154  // Expand all builtin opcodes.
155  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
156    setOperationAction(Opc, Ty, Expand);
157
158  setOperationAction(ISD::LOAD, Ty, Legal);
159  setOperationAction(ISD::STORE, Ty, Legal);
160  setOperationAction(ISD::BITCAST, Ty, Legal);
161}
162
163bool
164MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
165  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
166
167  switch (SVT) {
168  case MVT::i64:
169  case MVT::i32:
170    if (Fast)
171      *Fast = true;
172    return true;
173  default:
174    return false;
175  }
176}
177
178SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
179                                             SelectionDAG &DAG) const {
180  switch(Op.getOpcode()) {
181  case ISD::LOAD:  return lowerLOAD(Op, DAG);
182  case ISD::STORE: return lowerSTORE(Op, DAG);
183  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
184  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
185  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
186  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
187  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
188  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
189  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
190                                          DAG);
191  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
192  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
193  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
194  }
195
196  return MipsTargetLowering::LowerOperation(Op, DAG);
197}
198
199// selectMADD -
200// Transforms a subgraph in CurDAG if the following pattern is found:
201//  (addc multLo, Lo0), (adde multHi, Hi0),
202// where,
203//  multHi/Lo: product of multiplication
204//  Lo0: initial value of Lo register
205//  Hi0: initial value of Hi register
206// Return true if pattern matching was successful.
207static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
208  // ADDENode's second operand must be a flag output of an ADDC node in order
209  // for the matching to be successful.
210  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
211
212  if (ADDCNode->getOpcode() != ISD::ADDC)
213    return false;
214
215  SDValue MultHi = ADDENode->getOperand(0);
216  SDValue MultLo = ADDCNode->getOperand(0);
217  SDNode *MultNode = MultHi.getNode();
218  unsigned MultOpc = MultHi.getOpcode();
219
220  // MultHi and MultLo must be generated by the same node,
221  if (MultLo.getNode() != MultNode)
222    return false;
223
224  // and it must be a multiplication.
225  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
226    return false;
227
228  // MultLo amd MultHi must be the first and second output of MultNode
229  // respectively.
230  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
231    return false;
232
233  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
234  // of the values of MultNode, in which case MultNode will be removed in later
235  // phases.
236  // If there exist users other than ADDENode or ADDCNode, this function returns
237  // here, which will result in MultNode being mapped to a single MULT
238  // instruction node rather than a pair of MULT and MADD instructions being
239  // produced.
240  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
241    return false;
242
243  SDLoc DL(ADDENode);
244
245  // Initialize accumulator.
246  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
247                                  ADDCNode->getOperand(1),
248                                  ADDENode->getOperand(1));
249
250  // create MipsMAdd(u) node
251  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
252
253  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
254                                 MultNode->getOperand(0),// Factor 0
255                                 MultNode->getOperand(1),// Factor 1
256                                 ACCIn);
257
258  // replace uses of adde and addc here
259  if (!SDValue(ADDCNode, 0).use_empty()) {
260    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
261    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
262                                    LoIdx);
263    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
264  }
265  if (!SDValue(ADDENode, 0).use_empty()) {
266    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
267    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
268                                    HiIdx);
269    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
270  }
271
272  return true;
273}
274
275// selectMSUB -
276// Transforms a subgraph in CurDAG if the following pattern is found:
277//  (addc Lo0, multLo), (sube Hi0, multHi),
278// where,
279//  multHi/Lo: product of multiplication
280//  Lo0: initial value of Lo register
281//  Hi0: initial value of Hi register
282// Return true if pattern matching was successful.
283static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
284  // SUBENode's second operand must be a flag output of an SUBC node in order
285  // for the matching to be successful.
286  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
287
288  if (SUBCNode->getOpcode() != ISD::SUBC)
289    return false;
290
291  SDValue MultHi = SUBENode->getOperand(1);
292  SDValue MultLo = SUBCNode->getOperand(1);
293  SDNode *MultNode = MultHi.getNode();
294  unsigned MultOpc = MultHi.getOpcode();
295
296  // MultHi and MultLo must be generated by the same node,
297  if (MultLo.getNode() != MultNode)
298    return false;
299
300  // and it must be a multiplication.
301  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
302    return false;
303
304  // MultLo amd MultHi must be the first and second output of MultNode
305  // respectively.
306  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
307    return false;
308
309  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
310  // of the values of MultNode, in which case MultNode will be removed in later
311  // phases.
312  // If there exist users other than SUBENode or SUBCNode, this function returns
313  // here, which will result in MultNode being mapped to a single MULT
314  // instruction node rather than a pair of MULT and MSUB instructions being
315  // produced.
316  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
317    return false;
318
319  SDLoc DL(SUBENode);
320
321  // Initialize accumulator.
322  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
323                                  SUBCNode->getOperand(0),
324                                  SUBENode->getOperand(0));
325
326  // create MipsSub(u) node
327  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
328
329  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
330                                 MultNode->getOperand(0),// Factor 0
331                                 MultNode->getOperand(1),// Factor 1
332                                 ACCIn);
333
334  // replace uses of sube and subc here
335  if (!SDValue(SUBCNode, 0).use_empty()) {
336    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
337    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
338                                    LoIdx);
339    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
340  }
341  if (!SDValue(SUBENode, 0).use_empty()) {
342    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
343    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
344                                    HiIdx);
345    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
346  }
347
348  return true;
349}
350
351static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
352                                  TargetLowering::DAGCombinerInfo &DCI,
353                                  const MipsSubtarget *Subtarget) {
354  if (DCI.isBeforeLegalize())
355    return SDValue();
356
357  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
358      selectMADD(N, &DAG))
359    return SDValue(N, 0);
360
361  return SDValue();
362}
363
364static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
365                                  TargetLowering::DAGCombinerInfo &DCI,
366                                  const MipsSubtarget *Subtarget) {
367  if (DCI.isBeforeLegalize())
368    return SDValue();
369
370  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
371      selectMSUB(N, &DAG))
372    return SDValue(N, 0);
373
374  return SDValue();
375}
376
377static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
378                            EVT ShiftTy, SelectionDAG &DAG) {
379  // Clear the upper (64 - VT.sizeInBits) bits.
380  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
381
382  // Return 0.
383  if (C == 0)
384    return DAG.getConstant(0, VT);
385
386  // Return x.
387  if (C == 1)
388    return X;
389
390  // If c is power of 2, return (shl x, log2(c)).
391  if (isPowerOf2_64(C))
392    return DAG.getNode(ISD::SHL, DL, VT, X,
393                       DAG.getConstant(Log2_64(C), ShiftTy));
394
395  unsigned Log2Ceil = Log2_64_Ceil(C);
396  uint64_t Floor = 1LL << Log2_64(C);
397  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
398
399  // If |c - floor_c| <= |c - ceil_c|,
400  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
401  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
402  if (C - Floor <= Ceil - C) {
403    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
404    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
405    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
406  }
407
408  // If |c - floor_c| > |c - ceil_c|,
409  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
410  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
411  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
412  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
413}
414
415static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
416                                 const TargetLowering::DAGCombinerInfo &DCI,
417                                 const MipsSETargetLowering *TL) {
418  EVT VT = N->getValueType(0);
419
420  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
421    if (!VT.isVector())
422      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
423                          VT, TL->getScalarShiftAmountTy(VT), DAG);
424
425  return SDValue(N, 0);
426}
427
428static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
429                                      SelectionDAG &DAG,
430                                      const MipsSubtarget *Subtarget) {
431  // See if this is a vector splat immediate node.
432  APInt SplatValue, SplatUndef;
433  unsigned SplatBitSize;
434  bool HasAnyUndefs;
435  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
436  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
437
438  if (!BV ||
439      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
440                           EltSize, !Subtarget->isLittle()) ||
441      (SplatBitSize != EltSize) ||
442      (SplatValue.getZExtValue() >= EltSize))
443    return SDValue();
444
445  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
446                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
447}
448
449static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
450                                 TargetLowering::DAGCombinerInfo &DCI,
451                                 const MipsSubtarget *Subtarget) {
452  EVT Ty = N->getValueType(0);
453
454  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
455    return SDValue();
456
457  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
458}
459
460static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
461                                 TargetLowering::DAGCombinerInfo &DCI,
462                                 const MipsSubtarget *Subtarget) {
463  EVT Ty = N->getValueType(0);
464
465  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
466    return SDValue();
467
468  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
469}
470
471
472static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
473                                 TargetLowering::DAGCombinerInfo &DCI,
474                                 const MipsSubtarget *Subtarget) {
475  EVT Ty = N->getValueType(0);
476
477  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
478    return SDValue();
479
480  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
481}
482
483static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
484  bool IsV216 = (Ty == MVT::v2i16);
485
486  switch (CC) {
487  case ISD::SETEQ:
488  case ISD::SETNE:  return true;
489  case ISD::SETLT:
490  case ISD::SETLE:
491  case ISD::SETGT:
492  case ISD::SETGE:  return IsV216;
493  case ISD::SETULT:
494  case ISD::SETULE:
495  case ISD::SETUGT:
496  case ISD::SETUGE: return !IsV216;
497  default:          return false;
498  }
499}
500
501static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
502  EVT Ty = N->getValueType(0);
503
504  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
505    return SDValue();
506
507  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
508    return SDValue();
509
510  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
511                     N->getOperand(1), N->getOperand(2));
512}
513
514static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
515  EVT Ty = N->getValueType(0);
516
517  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
518    return SDValue();
519
520  SDValue SetCC = N->getOperand(0);
521
522  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
523    return SDValue();
524
525  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
526                     SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
527                     N->getOperand(2), SetCC.getOperand(2));
528}
529
530SDValue
531MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
532  SelectionDAG &DAG = DCI.DAG;
533  SDValue Val;
534
535  switch (N->getOpcode()) {
536  case ISD::ADDE:
537    return performADDECombine(N, DAG, DCI, Subtarget);
538  case ISD::SUBE:
539    return performSUBECombine(N, DAG, DCI, Subtarget);
540  case ISD::MUL:
541    return performMULCombine(N, DAG, DCI, this);
542  case ISD::SHL:
543    return performSHLCombine(N, DAG, DCI, Subtarget);
544  case ISD::SRA:
545    return performSRACombine(N, DAG, DCI, Subtarget);
546  case ISD::SRL:
547    return performSRLCombine(N, DAG, DCI, Subtarget);
548  case ISD::VSELECT:
549    return performVSELECTCombine(N, DAG);
550  case ISD::SETCC: {
551    Val = performSETCCCombine(N, DAG);
552    break;
553  }
554  }
555
556  if (Val.getNode())
557    return Val;
558
559  return MipsTargetLowering::PerformDAGCombine(N, DCI);
560}
561
562MachineBasicBlock *
563MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
564                                                  MachineBasicBlock *BB) const {
565  switch (MI->getOpcode()) {
566  default:
567    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
568  case Mips::BPOSGE32_PSEUDO:
569    return emitBPOSGE32(MI, BB);
570  case Mips::SNZ_B_PSEUDO:
571    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
572  case Mips::SNZ_H_PSEUDO:
573    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
574  case Mips::SNZ_W_PSEUDO:
575    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
576  case Mips::SNZ_D_PSEUDO:
577    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
578  case Mips::SNZ_V_PSEUDO:
579    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
580  case Mips::SZ_B_PSEUDO:
581    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
582  case Mips::SZ_H_PSEUDO:
583    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
584  case Mips::SZ_W_PSEUDO:
585    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
586  case Mips::SZ_D_PSEUDO:
587    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
588  case Mips::SZ_V_PSEUDO:
589    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
590  }
591}
592
593bool MipsSETargetLowering::
594isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
595                                  unsigned NextStackOffset,
596                                  const MipsFunctionInfo& FI) const {
597  if (!EnableMipsTailCalls)
598    return false;
599
600  // Return false if either the callee or caller has a byval argument.
601  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
602    return false;
603
604  // Return true if the callee's argument area is no larger than the
605  // caller's.
606  return NextStackOffset <= FI.getIncomingArgSize();
607}
608
609void MipsSETargetLowering::
610getOpndList(SmallVectorImpl<SDValue> &Ops,
611            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
612            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
613            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
614  // T9 should contain the address of the callee function if
615  // -reloction-model=pic or it is an indirect call.
616  if (IsPICCall || !GlobalOrExternal) {
617    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
618    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
619  } else
620    Ops.push_back(Callee);
621
622  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
623                                  InternalLinkage, CLI, Callee, Chain);
624}
625
626SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
627  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
628
629  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
630    return MipsTargetLowering::lowerLOAD(Op, DAG);
631
632  // Replace a double precision load with two i32 loads and a buildpair64.
633  SDLoc DL(Op);
634  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
635  EVT PtrVT = Ptr.getValueType();
636
637  // i32 load from lower address.
638  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
639                           MachinePointerInfo(), Nd.isVolatile(),
640                           Nd.isNonTemporal(), Nd.isInvariant(),
641                           Nd.getAlignment());
642
643  // i32 load from higher address.
644  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
645  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
646                           MachinePointerInfo(), Nd.isVolatile(),
647                           Nd.isNonTemporal(), Nd.isInvariant(),
648                           Nd.getAlignment());
649
650  if (!Subtarget->isLittle())
651    std::swap(Lo, Hi);
652
653  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
654  SDValue Ops[2] = {BP, Hi.getValue(1)};
655  return DAG.getMergeValues(Ops, 2, DL);
656}
657
658SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
659  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
660
661  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
662    return MipsTargetLowering::lowerSTORE(Op, DAG);
663
664  // Replace a double precision store with two extractelement64s and i32 stores.
665  SDLoc DL(Op);
666  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
667  EVT PtrVT = Ptr.getValueType();
668  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
669                           Val, DAG.getConstant(0, MVT::i32));
670  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
671                           Val, DAG.getConstant(1, MVT::i32));
672
673  if (!Subtarget->isLittle())
674    std::swap(Lo, Hi);
675
676  // i32 store to lower address.
677  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
678                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
679                       Nd.getTBAAInfo());
680
681  // i32 store to higher address.
682  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
683  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
684                      Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
685                      Nd.getTBAAInfo());
686}
687
688SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
689                                          bool HasLo, bool HasHi,
690                                          SelectionDAG &DAG) const {
691  EVT Ty = Op.getOperand(0).getValueType();
692  SDLoc DL(Op);
693  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
694                             Op.getOperand(0), Op.getOperand(1));
695  SDValue Lo, Hi;
696
697  if (HasLo)
698    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
699                     DAG.getConstant(Mips::sub_lo, MVT::i32));
700  if (HasHi)
701    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
702                     DAG.getConstant(Mips::sub_hi, MVT::i32));
703
704  if (!HasLo || !HasHi)
705    return HasLo ? Lo : Hi;
706
707  SDValue Vals[] = { Lo, Hi };
708  return DAG.getMergeValues(Vals, 2, DL);
709}
710
711
712static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
713  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
714                             DAG.getConstant(0, MVT::i32));
715  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
716                             DAG.getConstant(1, MVT::i32));
717  return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
718}
719
720static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
721  SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
722                           DAG.getConstant(Mips::sub_lo, MVT::i32));
723  SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
724                           DAG.getConstant(Mips::sub_hi, MVT::i32));
725  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
726}
727
728// This function expands mips intrinsic nodes which have 64-bit input operands
729// or output values.
730//
731// out64 = intrinsic-node in64
732// =>
733// lo = copy (extract-element (in64, 0))
734// hi = copy (extract-element (in64, 1))
735// mips-specific-node
736// v0 = copy lo
737// v1 = copy hi
738// out64 = merge-values (v0, v1)
739//
740static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
741  SDLoc DL(Op);
742  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
743  SmallVector<SDValue, 3> Ops;
744  unsigned OpNo = 0;
745
746  // See if Op has a chain input.
747  if (HasChainIn)
748    Ops.push_back(Op->getOperand(OpNo++));
749
750  // The next operand is the intrinsic opcode.
751  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
752
753  // See if the next operand has type i64.
754  SDValue Opnd = Op->getOperand(++OpNo), In64;
755
756  if (Opnd.getValueType() == MVT::i64)
757    In64 = initAccumulator(Opnd, DL, DAG);
758  else
759    Ops.push_back(Opnd);
760
761  // Push the remaining operands.
762  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
763    Ops.push_back(Op->getOperand(OpNo));
764
765  // Add In64 to the end of the list.
766  if (In64.getNode())
767    Ops.push_back(In64);
768
769  // Scan output.
770  SmallVector<EVT, 2> ResTys;
771
772  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
773       I != E; ++I)
774    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
775
776  // Create node.
777  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
778  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
779
780  if (!HasChainIn)
781    return Out;
782
783  assert(Val->getValueType(1) == MVT::Other);
784  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
785  return DAG.getMergeValues(Vals, 2, DL);
786}
787
788static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
789  SDLoc DL(Op);
790  SDValue Value = Op->getOperand(1);
791  EVT ResTy = Op->getValueType(0);
792
793  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
794
795  return Result;
796}
797
798SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
799                                                      SelectionDAG &DAG) const {
800  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
801  default:
802    return SDValue();
803  case Intrinsic::mips_shilo:
804    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
805  case Intrinsic::mips_dpau_h_qbl:
806    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
807  case Intrinsic::mips_dpau_h_qbr:
808    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
809  case Intrinsic::mips_dpsu_h_qbl:
810    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
811  case Intrinsic::mips_dpsu_h_qbr:
812    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
813  case Intrinsic::mips_dpa_w_ph:
814    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
815  case Intrinsic::mips_dps_w_ph:
816    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
817  case Intrinsic::mips_dpax_w_ph:
818    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
819  case Intrinsic::mips_dpsx_w_ph:
820    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
821  case Intrinsic::mips_mulsa_w_ph:
822    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
823  case Intrinsic::mips_mult:
824    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
825  case Intrinsic::mips_multu:
826    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
827  case Intrinsic::mips_madd:
828    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
829  case Intrinsic::mips_maddu:
830    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
831  case Intrinsic::mips_msub:
832    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
833  case Intrinsic::mips_msubu:
834    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
835  case Intrinsic::mips_bnz_b:
836  case Intrinsic::mips_bnz_h:
837  case Intrinsic::mips_bnz_w:
838  case Intrinsic::mips_bnz_d:
839    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
840  case Intrinsic::mips_bnz_v:
841    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
842  case Intrinsic::mips_bz_b:
843  case Intrinsic::mips_bz_h:
844  case Intrinsic::mips_bz_w:
845  case Intrinsic::mips_bz_d:
846    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
847  case Intrinsic::mips_bz_v:
848    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
849  }
850}
851
852static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
853  SDLoc DL(Op);
854  SDValue ChainIn = Op->getOperand(0);
855  SDValue Address = Op->getOperand(2);
856  SDValue Offset  = Op->getOperand(3);
857  EVT ResTy = Op->getValueType(0);
858  EVT PtrTy = Address->getValueType(0);
859
860  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
861
862  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
863                     false, false, 16);
864}
865
866SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
867                                                     SelectionDAG &DAG) const {
868  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
869  switch (Intr) {
870  default:
871    return SDValue();
872  case Intrinsic::mips_extp:
873    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
874  case Intrinsic::mips_extpdp:
875    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
876  case Intrinsic::mips_extr_w:
877    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
878  case Intrinsic::mips_extr_r_w:
879    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
880  case Intrinsic::mips_extr_rs_w:
881    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
882  case Intrinsic::mips_extr_s_h:
883    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
884  case Intrinsic::mips_mthlip:
885    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
886  case Intrinsic::mips_mulsaq_s_w_ph:
887    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
888  case Intrinsic::mips_maq_s_w_phl:
889    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
890  case Intrinsic::mips_maq_s_w_phr:
891    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
892  case Intrinsic::mips_maq_sa_w_phl:
893    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
894  case Intrinsic::mips_maq_sa_w_phr:
895    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
896  case Intrinsic::mips_dpaq_s_w_ph:
897    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
898  case Intrinsic::mips_dpsq_s_w_ph:
899    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
900  case Intrinsic::mips_dpaq_sa_l_w:
901    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
902  case Intrinsic::mips_dpsq_sa_l_w:
903    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
904  case Intrinsic::mips_dpaqx_s_w_ph:
905    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
906  case Intrinsic::mips_dpaqx_sa_w_ph:
907    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
908  case Intrinsic::mips_dpsqx_s_w_ph:
909    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
910  case Intrinsic::mips_dpsqx_sa_w_ph:
911    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
912  case Intrinsic::mips_ld_b:
913  case Intrinsic::mips_ld_h:
914  case Intrinsic::mips_ld_w:
915  case Intrinsic::mips_ld_d:
916  case Intrinsic::mips_ldx_b:
917  case Intrinsic::mips_ldx_h:
918  case Intrinsic::mips_ldx_w:
919  case Intrinsic::mips_ldx_d:
920   return lowerMSALoadIntr(Op, DAG, Intr);
921  }
922}
923
924static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
925  SDLoc DL(Op);
926  SDValue ChainIn = Op->getOperand(0);
927  SDValue Value   = Op->getOperand(2);
928  SDValue Address = Op->getOperand(3);
929  SDValue Offset  = Op->getOperand(4);
930  EVT PtrTy = Address->getValueType(0);
931
932  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
933
934  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
935                      false, 16);
936}
937
938SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
939                                                  SelectionDAG &DAG) const {
940  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
941  switch (Intr) {
942  default:
943    return SDValue();
944  case Intrinsic::mips_st_b:
945  case Intrinsic::mips_st_h:
946  case Intrinsic::mips_st_w:
947  case Intrinsic::mips_st_d:
948  case Intrinsic::mips_stx_b:
949  case Intrinsic::mips_stx_h:
950  case Intrinsic::mips_stx_w:
951  case Intrinsic::mips_stx_d:
952    return lowerMSAStoreIntr(Op, DAG, Intr);
953  }
954}
955
956MachineBasicBlock * MipsSETargetLowering::
957emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
958  // $bb:
959  //  bposge32_pseudo $vr0
960  //  =>
961  // $bb:
962  //  bposge32 $tbb
963  // $fbb:
964  //  li $vr2, 0
965  //  b $sink
966  // $tbb:
967  //  li $vr1, 1
968  // $sink:
969  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
970
971  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
972  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
973  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
974  DebugLoc DL = MI->getDebugLoc();
975  const BasicBlock *LLVM_BB = BB->getBasicBlock();
976  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
977  MachineFunction *F = BB->getParent();
978  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
979  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
980  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
981  F->insert(It, FBB);
982  F->insert(It, TBB);
983  F->insert(It, Sink);
984
985  // Transfer the remainder of BB and its successor edges to Sink.
986  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
987               BB->end());
988  Sink->transferSuccessorsAndUpdatePHIs(BB);
989
990  // Add successors.
991  BB->addSuccessor(FBB);
992  BB->addSuccessor(TBB);
993  FBB->addSuccessor(Sink);
994  TBB->addSuccessor(Sink);
995
996  // Insert the real bposge32 instruction to $BB.
997  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
998
999  // Fill $FBB.
1000  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1001  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1002    .addReg(Mips::ZERO).addImm(0);
1003  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1004
1005  // Fill $TBB.
1006  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1007  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1008    .addReg(Mips::ZERO).addImm(1);
1009
1010  // Insert phi function to $Sink.
1011  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1012          MI->getOperand(0).getReg())
1013    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1014
1015  MI->eraseFromParent();   // The pseudo instruction is gone now.
1016  return Sink;
1017}
1018
1019MachineBasicBlock * MipsSETargetLowering::
1020emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1021                     unsigned BranchOp) const{
1022  // $bb:
1023  //  vany_nonzero $rd, $ws
1024  //  =>
1025  // $bb:
1026  //  bnz.b $ws, $tbb
1027  //  b $fbb
1028  // $fbb:
1029  //  li $rd1, 0
1030  //  b $sink
1031  // $tbb:
1032  //  li $rd2, 1
1033  // $sink:
1034  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
1035
1036  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1037  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1038  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1039  DebugLoc DL = MI->getDebugLoc();
1040  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1041  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1042  MachineFunction *F = BB->getParent();
1043  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1044  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1045  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1046  F->insert(It, FBB);
1047  F->insert(It, TBB);
1048  F->insert(It, Sink);
1049
1050  // Transfer the remainder of BB and its successor edges to Sink.
1051  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1052               BB->end());
1053  Sink->transferSuccessorsAndUpdatePHIs(BB);
1054
1055  // Add successors.
1056  BB->addSuccessor(FBB);
1057  BB->addSuccessor(TBB);
1058  FBB->addSuccessor(Sink);
1059  TBB->addSuccessor(Sink);
1060
1061  // Insert the real bnz.b instruction to $BB.
1062  BuildMI(BB, DL, TII->get(BranchOp))
1063    .addReg(MI->getOperand(1).getReg())
1064    .addMBB(TBB);
1065
1066  // Fill $FBB.
1067  unsigned RD1 = RegInfo.createVirtualRegister(RC);
1068  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1069    .addReg(Mips::ZERO).addImm(0);
1070  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1071
1072  // Fill $TBB.
1073  unsigned RD2 = RegInfo.createVirtualRegister(RC);
1074  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1075    .addReg(Mips::ZERO).addImm(1);
1076
1077  // Insert phi function to $Sink.
1078  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1079          MI->getOperand(0).getReg())
1080    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1081
1082  MI->eraseFromParent();   // The pseudo instruction is gone now.
1083  return Sink;
1084}
1085