MipsSEISelLowering.cpp revision 57cd3bc4064bd71eb6572d3cba5e23471ab25863 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
37
38  if (HasMips64)
39    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
40
41  if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
42    // Expand all truncating stores and extending loads.
43    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
44    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
45
46    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
47      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
48        setTruncStoreAction((MVT::SimpleValueType)VT0,
49                            (MVT::SimpleValueType)VT1, Expand);
50
51      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
52      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
53      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
54    }
55  }
56
57  if (Subtarget->hasDSP()) {
58    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
59
60    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
61      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
62
63      // Expand all builtin opcodes.
64      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
65        setOperationAction(Opc, VecTys[i], Expand);
66
67      setOperationAction(ISD::ADD, VecTys[i], Legal);
68      setOperationAction(ISD::SUB, VecTys[i], Legal);
69      setOperationAction(ISD::LOAD, VecTys[i], Legal);
70      setOperationAction(ISD::STORE, VecTys[i], Legal);
71      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
72    }
73
74    setTargetDAGCombine(ISD::SHL);
75    setTargetDAGCombine(ISD::SRA);
76    setTargetDAGCombine(ISD::SRL);
77    setTargetDAGCombine(ISD::SETCC);
78    setTargetDAGCombine(ISD::VSELECT);
79  }
80
81  if (Subtarget->hasDSPR2())
82    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
83
84  if (Subtarget->hasMSA()) {
85    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
86    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
87    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
88    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
89    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
90    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
91    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
92
93    setTargetDAGCombine(ISD::AND);
94    setTargetDAGCombine(ISD::SRA);
95    setTargetDAGCombine(ISD::VSELECT);
96    setTargetDAGCombine(ISD::XOR);
97  }
98
99  if (!Subtarget->mipsSEUsesSoftFloat()) {
100    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
101
102    // When dealing with single precision only, use libcalls
103    if (!Subtarget->isSingleFloat()) {
104      if (Subtarget->isFP64bit())
105        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
106      else
107        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
108    }
109  }
110
111  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
112  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
113  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
114  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
115
116  if (HasMips64) {
117    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
118    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
119    setOperationAction(ISD::MUL,              MVT::i64, Custom);
120  }
121
122  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
123  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
124
125  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
126  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
127  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
128  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
129  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
130  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
131  setOperationAction(ISD::STORE,              MVT::i32, Custom);
132
133  setTargetDAGCombine(ISD::ADDE);
134  setTargetDAGCombine(ISD::SUBE);
135  setTargetDAGCombine(ISD::MUL);
136
137  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
138  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
139  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
140
141  if (NoDPLoadStore) {
142    setOperationAction(ISD::LOAD, MVT::f64, Custom);
143    setOperationAction(ISD::STORE, MVT::f64, Custom);
144  }
145
146  computeRegisterProperties();
147}
148
149const MipsTargetLowering *
150llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
151  return new MipsSETargetLowering(TM);
152}
153
154// Enable MSA support for the given integer type and Register class.
155void MipsSETargetLowering::
156addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
157  addRegisterClass(Ty, RC);
158
159  // Expand all builtin opcodes.
160  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
161    setOperationAction(Opc, Ty, Expand);
162
163  setOperationAction(ISD::BITCAST, Ty, Legal);
164  setOperationAction(ISD::LOAD, Ty, Legal);
165  setOperationAction(ISD::STORE, Ty, Legal);
166  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
167  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
168  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
169
170  setOperationAction(ISD::ADD, Ty, Legal);
171  setOperationAction(ISD::AND, Ty, Legal);
172  setOperationAction(ISD::CTLZ, Ty, Legal);
173  setOperationAction(ISD::CTPOP, Ty, Legal);
174  setOperationAction(ISD::MUL, Ty, Legal);
175  setOperationAction(ISD::OR, Ty, Legal);
176  setOperationAction(ISD::SDIV, Ty, Legal);
177  setOperationAction(ISD::SREM, Ty, Legal);
178  setOperationAction(ISD::SHL, Ty, Legal);
179  setOperationAction(ISD::SRA, Ty, Legal);
180  setOperationAction(ISD::SRL, Ty, Legal);
181  setOperationAction(ISD::SUB, Ty, Legal);
182  setOperationAction(ISD::UDIV, Ty, Legal);
183  setOperationAction(ISD::UREM, Ty, Legal);
184  setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
185  setOperationAction(ISD::VSELECT, Ty, Legal);
186  setOperationAction(ISD::XOR, Ty, Legal);
187
188  if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
189    setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
190    setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
191    setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
192    setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
193  }
194
195  setOperationAction(ISD::SETCC, Ty, Legal);
196  setCondCodeAction(ISD::SETNE, Ty, Expand);
197  setCondCodeAction(ISD::SETGE, Ty, Expand);
198  setCondCodeAction(ISD::SETGT, Ty, Expand);
199  setCondCodeAction(ISD::SETUGE, Ty, Expand);
200  setCondCodeAction(ISD::SETUGT, Ty, Expand);
201}
202
203// Enable MSA support for the given floating-point type and Register class.
204void MipsSETargetLowering::
205addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
206  addRegisterClass(Ty, RC);
207
208  // Expand all builtin opcodes.
209  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
210    setOperationAction(Opc, Ty, Expand);
211
212  setOperationAction(ISD::LOAD, Ty, Legal);
213  setOperationAction(ISD::STORE, Ty, Legal);
214  setOperationAction(ISD::BITCAST, Ty, Legal);
215  setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
216  setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
217  setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
218
219  if (Ty != MVT::v8f16) {
220    setOperationAction(ISD::FABS,  Ty, Legal);
221    setOperationAction(ISD::FADD,  Ty, Legal);
222    setOperationAction(ISD::FDIV,  Ty, Legal);
223    setOperationAction(ISD::FEXP2, Ty, Legal);
224    setOperationAction(ISD::FLOG2, Ty, Legal);
225    setOperationAction(ISD::FMA,   Ty, Legal);
226    setOperationAction(ISD::FMUL,  Ty, Legal);
227    setOperationAction(ISD::FRINT, Ty, Legal);
228    setOperationAction(ISD::FSQRT, Ty, Legal);
229    setOperationAction(ISD::FSUB,  Ty, Legal);
230    setOperationAction(ISD::VSELECT, Ty, Legal);
231
232    setOperationAction(ISD::SETCC, Ty, Legal);
233    setCondCodeAction(ISD::SETOGE, Ty, Expand);
234    setCondCodeAction(ISD::SETOGT, Ty, Expand);
235    setCondCodeAction(ISD::SETUGE, Ty, Expand);
236    setCondCodeAction(ISD::SETUGT, Ty, Expand);
237    setCondCodeAction(ISD::SETGE,  Ty, Expand);
238    setCondCodeAction(ISD::SETGT,  Ty, Expand);
239  }
240}
241
242bool
243MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
244  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
245
246  switch (SVT) {
247  case MVT::i64:
248  case MVT::i32:
249    if (Fast)
250      *Fast = true;
251    return true;
252  default:
253    return false;
254  }
255}
256
257SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
258                                             SelectionDAG &DAG) const {
259  switch(Op.getOpcode()) {
260  case ISD::LOAD:  return lowerLOAD(Op, DAG);
261  case ISD::STORE: return lowerSTORE(Op, DAG);
262  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
263  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
264  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
265  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
266  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
267  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
268  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
269                                          DAG);
270  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
271  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
272  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
273  case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
274  case ISD::BUILD_VECTOR:       return lowerBUILD_VECTOR(Op, DAG);
275  case ISD::VECTOR_SHUFFLE:     return lowerVECTOR_SHUFFLE(Op, DAG);
276  }
277
278  return MipsTargetLowering::LowerOperation(Op, DAG);
279}
280
281// selectMADD -
282// Transforms a subgraph in CurDAG if the following pattern is found:
283//  (addc multLo, Lo0), (adde multHi, Hi0),
284// where,
285//  multHi/Lo: product of multiplication
286//  Lo0: initial value of Lo register
287//  Hi0: initial value of Hi register
288// Return true if pattern matching was successful.
289static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
290  // ADDENode's second operand must be a flag output of an ADDC node in order
291  // for the matching to be successful.
292  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
293
294  if (ADDCNode->getOpcode() != ISD::ADDC)
295    return false;
296
297  SDValue MultHi = ADDENode->getOperand(0);
298  SDValue MultLo = ADDCNode->getOperand(0);
299  SDNode *MultNode = MultHi.getNode();
300  unsigned MultOpc = MultHi.getOpcode();
301
302  // MultHi and MultLo must be generated by the same node,
303  if (MultLo.getNode() != MultNode)
304    return false;
305
306  // and it must be a multiplication.
307  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
308    return false;
309
310  // MultLo amd MultHi must be the first and second output of MultNode
311  // respectively.
312  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
313    return false;
314
315  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
316  // of the values of MultNode, in which case MultNode will be removed in later
317  // phases.
318  // If there exist users other than ADDENode or ADDCNode, this function returns
319  // here, which will result in MultNode being mapped to a single MULT
320  // instruction node rather than a pair of MULT and MADD instructions being
321  // produced.
322  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
323    return false;
324
325  SDLoc DL(ADDENode);
326
327  // Initialize accumulator.
328  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
329                                  ADDCNode->getOperand(1),
330                                  ADDENode->getOperand(1));
331
332  // create MipsMAdd(u) node
333  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
334
335  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
336                                 MultNode->getOperand(0),// Factor 0
337                                 MultNode->getOperand(1),// Factor 1
338                                 ACCIn);
339
340  // replace uses of adde and addc here
341  if (!SDValue(ADDCNode, 0).use_empty()) {
342    SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
343    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
344  }
345  if (!SDValue(ADDENode, 0).use_empty()) {
346    SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
347    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
348  }
349
350  return true;
351}
352
353// selectMSUB -
354// Transforms a subgraph in CurDAG if the following pattern is found:
355//  (addc Lo0, multLo), (sube Hi0, multHi),
356// where,
357//  multHi/Lo: product of multiplication
358//  Lo0: initial value of Lo register
359//  Hi0: initial value of Hi register
360// Return true if pattern matching was successful.
361static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
362  // SUBENode's second operand must be a flag output of an SUBC node in order
363  // for the matching to be successful.
364  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
365
366  if (SUBCNode->getOpcode() != ISD::SUBC)
367    return false;
368
369  SDValue MultHi = SUBENode->getOperand(1);
370  SDValue MultLo = SUBCNode->getOperand(1);
371  SDNode *MultNode = MultHi.getNode();
372  unsigned MultOpc = MultHi.getOpcode();
373
374  // MultHi and MultLo must be generated by the same node,
375  if (MultLo.getNode() != MultNode)
376    return false;
377
378  // and it must be a multiplication.
379  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
380    return false;
381
382  // MultLo amd MultHi must be the first and second output of MultNode
383  // respectively.
384  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
385    return false;
386
387  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
388  // of the values of MultNode, in which case MultNode will be removed in later
389  // phases.
390  // If there exist users other than SUBENode or SUBCNode, this function returns
391  // here, which will result in MultNode being mapped to a single MULT
392  // instruction node rather than a pair of MULT and MSUB instructions being
393  // produced.
394  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
395    return false;
396
397  SDLoc DL(SUBENode);
398
399  // Initialize accumulator.
400  SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
401                                  SUBCNode->getOperand(0),
402                                  SUBENode->getOperand(0));
403
404  // create MipsSub(u) node
405  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
406
407  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
408                                 MultNode->getOperand(0),// Factor 0
409                                 MultNode->getOperand(1),// Factor 1
410                                 ACCIn);
411
412  // replace uses of sube and subc here
413  if (!SDValue(SUBCNode, 0).use_empty()) {
414    SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
415    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
416  }
417  if (!SDValue(SUBENode, 0).use_empty()) {
418    SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
419    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
420  }
421
422  return true;
423}
424
425static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
426                                  TargetLowering::DAGCombinerInfo &DCI,
427                                  const MipsSubtarget *Subtarget) {
428  if (DCI.isBeforeLegalize())
429    return SDValue();
430
431  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
432      selectMADD(N, &DAG))
433    return SDValue(N, 0);
434
435  return SDValue();
436}
437
438// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
439//
440// Performs the following transformations:
441// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
442//   sign/zero-extension is completely overwritten by the new one performed by
443//   the ISD::AND.
444// - Removes redundant zero extensions performed by an ISD::AND.
445static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
446                                 TargetLowering::DAGCombinerInfo &DCI,
447                                 const MipsSubtarget *Subtarget) {
448  if (!Subtarget->hasMSA())
449    return SDValue();
450
451  SDValue Op0 = N->getOperand(0);
452  SDValue Op1 = N->getOperand(1);
453  unsigned Op0Opcode = Op0->getOpcode();
454
455  // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
456  // where $d + 1 == 2^n and n == 32
457  // or    $d + 1 == 2^n and n <= 32 and ZExt
458  // -> (MipsVExtractZExt $a, $b, $c)
459  if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
460      Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
461    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
462
463    if (!Mask)
464      return SDValue();
465
466    int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
467
468    if (Log2IfPositive <= 0)
469      return SDValue(); // Mask+1 is not a power of 2
470
471    SDValue Op0Op2 = Op0->getOperand(2);
472    EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
473    unsigned ExtendTySize = ExtendTy.getSizeInBits();
474    unsigned Log2 = Log2IfPositive;
475
476    if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
477        Log2 == ExtendTySize) {
478      SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
479      DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
480                      Op0->getVTList(), Ops, Op0->getNumOperands());
481      return Op0;
482    }
483  }
484
485  return SDValue();
486}
487
488static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
489                                  TargetLowering::DAGCombinerInfo &DCI,
490                                  const MipsSubtarget *Subtarget) {
491  if (DCI.isBeforeLegalize())
492    return SDValue();
493
494  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
495      selectMSUB(N, &DAG))
496    return SDValue(N, 0);
497
498  return SDValue();
499}
500
501static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
502                            EVT ShiftTy, SelectionDAG &DAG) {
503  // Clear the upper (64 - VT.sizeInBits) bits.
504  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
505
506  // Return 0.
507  if (C == 0)
508    return DAG.getConstant(0, VT);
509
510  // Return x.
511  if (C == 1)
512    return X;
513
514  // If c is power of 2, return (shl x, log2(c)).
515  if (isPowerOf2_64(C))
516    return DAG.getNode(ISD::SHL, DL, VT, X,
517                       DAG.getConstant(Log2_64(C), ShiftTy));
518
519  unsigned Log2Ceil = Log2_64_Ceil(C);
520  uint64_t Floor = 1LL << Log2_64(C);
521  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
522
523  // If |c - floor_c| <= |c - ceil_c|,
524  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
525  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
526  if (C - Floor <= Ceil - C) {
527    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
528    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
529    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
530  }
531
532  // If |c - floor_c| > |c - ceil_c|,
533  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
534  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
535  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
536  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
537}
538
539static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
540                                 const TargetLowering::DAGCombinerInfo &DCI,
541                                 const MipsSETargetLowering *TL) {
542  EVT VT = N->getValueType(0);
543
544  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
545    if (!VT.isVector())
546      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
547                          VT, TL->getScalarShiftAmountTy(VT), DAG);
548
549  return SDValue(N, 0);
550}
551
552static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
553                                      SelectionDAG &DAG,
554                                      const MipsSubtarget *Subtarget) {
555  // See if this is a vector splat immediate node.
556  APInt SplatValue, SplatUndef;
557  unsigned SplatBitSize;
558  bool HasAnyUndefs;
559  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
560  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
561
562  if (!BV ||
563      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
564                           EltSize, !Subtarget->isLittle()) ||
565      (SplatBitSize != EltSize) ||
566      (SplatValue.getZExtValue() >= EltSize))
567    return SDValue();
568
569  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
570                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
571}
572
573static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
574                                 TargetLowering::DAGCombinerInfo &DCI,
575                                 const MipsSubtarget *Subtarget) {
576  EVT Ty = N->getValueType(0);
577
578  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
579    return SDValue();
580
581  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
582}
583
584// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
585// constant splats into MipsISD::SHRA_DSP for DSPr2.
586//
587// Performs the following transformations:
588// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
589//   sign/zero-extension is completely overwritten by the new one performed by
590//   the ISD::SRA and ISD::SHL nodes.
591// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
592//   sequence.
593//
594// See performDSPShiftCombine for more information about the transformation
595// used for DSPr2.
596static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
597                                 TargetLowering::DAGCombinerInfo &DCI,
598                                 const MipsSubtarget *Subtarget) {
599  EVT Ty = N->getValueType(0);
600
601  if (Subtarget->hasMSA()) {
602    SDValue Op0 = N->getOperand(0);
603    SDValue Op1 = N->getOperand(1);
604
605    // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
606    // where $d + sizeof($c) == 32
607    // or    $d + sizeof($c) <= 32 and SExt
608    // -> (MipsVExtractSExt $a, $b, $c)
609    if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
610      SDValue Op0Op0 = Op0->getOperand(0);
611      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
612
613      if (!ShAmount)
614        return SDValue();
615
616      if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
617          Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
618        return SDValue();
619
620      EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
621      unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
622
623      if (TotalBits == 32 ||
624          (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
625           TotalBits <= 32)) {
626        SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
627                          Op0Op0->getOperand(2) };
628        DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
629                        Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands());
630        return Op0Op0;
631      }
632    }
633  }
634
635  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
636    return SDValue();
637
638  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
639}
640
641
642static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
643                                 TargetLowering::DAGCombinerInfo &DCI,
644                                 const MipsSubtarget *Subtarget) {
645  EVT Ty = N->getValueType(0);
646
647  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
648    return SDValue();
649
650  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
651}
652
653static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
654  bool IsV216 = (Ty == MVT::v2i16);
655
656  switch (CC) {
657  case ISD::SETEQ:
658  case ISD::SETNE:  return true;
659  case ISD::SETLT:
660  case ISD::SETLE:
661  case ISD::SETGT:
662  case ISD::SETGE:  return IsV216;
663  case ISD::SETULT:
664  case ISD::SETULE:
665  case ISD::SETUGT:
666  case ISD::SETUGE: return !IsV216;
667  default:          return false;
668  }
669}
670
671static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
672  EVT Ty = N->getValueType(0);
673
674  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
675    return SDValue();
676
677  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
678    return SDValue();
679
680  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
681                     N->getOperand(1), N->getOperand(2));
682}
683
684static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
685  EVT Ty = N->getValueType(0);
686
687  if (Ty.is128BitVector() && Ty.isInteger()) {
688    // Try the following combines:
689    //   (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
690    //   (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
691    //   (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
692    //   (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
693    //   (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
694    //   (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
695    //   (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
696    //   (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
697    // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
698    // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
699    // legalizer.
700    SDValue Op0 = N->getOperand(0);
701
702    if (Op0->getOpcode() != ISD::SETCC)
703      return SDValue();
704
705    ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
706    bool Signed;
707
708    if (CondCode == ISD::SETLT  || CondCode == ISD::SETLE)
709      Signed = true;
710    else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
711      Signed = false;
712    else
713      return SDValue();
714
715    SDValue Op1 = N->getOperand(1);
716    SDValue Op2 = N->getOperand(2);
717    SDValue Op0Op0 = Op0->getOperand(0);
718    SDValue Op0Op1 = Op0->getOperand(1);
719
720    if (Op1 == Op0Op0 && Op2 == Op0Op1)
721      return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
722                         Ty, Op1, Op2);
723    else if (Op1 == Op0Op1 && Op2 == Op0Op0)
724      return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
725                         Ty, Op1, Op2);
726  } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
727    SDValue SetCC = N->getOperand(0);
728
729    if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
730      return SDValue();
731
732    return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
733                       SetCC.getOperand(0), SetCC.getOperand(1),
734                       N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
735  }
736
737  return SDValue();
738}
739
740static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
741                                 const MipsSubtarget *Subtarget) {
742  EVT Ty = N->getValueType(0);
743
744  if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
745    // Try the following combines:
746    //   (xor (or $a, $b), (build_vector allones))
747    //   (xor (or $a, $b), (bitcast (build_vector allones)))
748    SDValue Op0 = N->getOperand(0);
749    SDValue Op1 = N->getOperand(1);
750    SDValue NotOp;
751
752    if (ISD::isBuildVectorAllOnes(Op0.getNode()))
753      NotOp = Op1;
754    else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
755      NotOp = Op0;
756    else
757      return SDValue();
758
759    if (NotOp->getOpcode() == ISD::OR)
760      return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
761                         NotOp->getOperand(1));
762  }
763
764  return SDValue();
765}
766
767SDValue
768MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
769  SelectionDAG &DAG = DCI.DAG;
770  SDValue Val;
771
772  switch (N->getOpcode()) {
773  case ISD::ADDE:
774    return performADDECombine(N, DAG, DCI, Subtarget);
775  case ISD::AND:
776    Val = performANDCombine(N, DAG, DCI, Subtarget);
777    break;
778  case ISD::SUBE:
779    return performSUBECombine(N, DAG, DCI, Subtarget);
780  case ISD::MUL:
781    return performMULCombine(N, DAG, DCI, this);
782  case ISD::SHL:
783    return performSHLCombine(N, DAG, DCI, Subtarget);
784  case ISD::SRA:
785    return performSRACombine(N, DAG, DCI, Subtarget);
786  case ISD::SRL:
787    return performSRLCombine(N, DAG, DCI, Subtarget);
788  case ISD::VSELECT:
789    return performVSELECTCombine(N, DAG);
790  case ISD::XOR:
791    Val = performXORCombine(N, DAG, Subtarget);
792    break;
793  case ISD::SETCC:
794    Val = performSETCCCombine(N, DAG);
795    break;
796  }
797
798  if (Val.getNode())
799    return Val;
800
801  return MipsTargetLowering::PerformDAGCombine(N, DCI);
802}
803
804MachineBasicBlock *
805MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
806                                                  MachineBasicBlock *BB) const {
807  switch (MI->getOpcode()) {
808  default:
809    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
810  case Mips::BPOSGE32_PSEUDO:
811    return emitBPOSGE32(MI, BB);
812  case Mips::SNZ_B_PSEUDO:
813    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
814  case Mips::SNZ_H_PSEUDO:
815    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
816  case Mips::SNZ_W_PSEUDO:
817    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
818  case Mips::SNZ_D_PSEUDO:
819    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
820  case Mips::SNZ_V_PSEUDO:
821    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
822  case Mips::SZ_B_PSEUDO:
823    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
824  case Mips::SZ_H_PSEUDO:
825    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
826  case Mips::SZ_W_PSEUDO:
827    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
828  case Mips::SZ_D_PSEUDO:
829    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
830  case Mips::SZ_V_PSEUDO:
831    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
832  case Mips::COPY_FW_PSEUDO:
833    return emitCOPY_FW(MI, BB);
834  case Mips::COPY_FD_PSEUDO:
835    return emitCOPY_FD(MI, BB);
836  case Mips::INSERT_FW_PSEUDO:
837    return emitINSERT_FW(MI, BB);
838  case Mips::INSERT_FD_PSEUDO:
839    return emitINSERT_FD(MI, BB);
840  case Mips::FILL_FW_PSEUDO:
841    return emitFILL_FW(MI, BB);
842  case Mips::FILL_FD_PSEUDO:
843    return emitFILL_FD(MI, BB);
844  case Mips::FEXP2_W_1_PSEUDO:
845    return emitFEXP2_W_1(MI, BB);
846  case Mips::FEXP2_D_1_PSEUDO:
847    return emitFEXP2_D_1(MI, BB);
848  }
849}
850
851bool MipsSETargetLowering::
852isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
853                                  unsigned NextStackOffset,
854                                  const MipsFunctionInfo& FI) const {
855  if (!EnableMipsTailCalls)
856    return false;
857
858  // Return false if either the callee or caller has a byval argument.
859  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
860    return false;
861
862  // Return true if the callee's argument area is no larger than the
863  // caller's.
864  return NextStackOffset <= FI.getIncomingArgSize();
865}
866
867void MipsSETargetLowering::
868getOpndList(SmallVectorImpl<SDValue> &Ops,
869            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
870            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
871            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
872  // T9 should contain the address of the callee function if
873  // -reloction-model=pic or it is an indirect call.
874  if (IsPICCall || !GlobalOrExternal) {
875    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
876    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
877  } else
878    Ops.push_back(Callee);
879
880  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
881                                  InternalLinkage, CLI, Callee, Chain);
882}
883
884SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
885  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
886
887  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
888    return MipsTargetLowering::lowerLOAD(Op, DAG);
889
890  // Replace a double precision load with two i32 loads and a buildpair64.
891  SDLoc DL(Op);
892  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
893  EVT PtrVT = Ptr.getValueType();
894
895  // i32 load from lower address.
896  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
897                           MachinePointerInfo(), Nd.isVolatile(),
898                           Nd.isNonTemporal(), Nd.isInvariant(),
899                           Nd.getAlignment());
900
901  // i32 load from higher address.
902  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
903  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
904                           MachinePointerInfo(), Nd.isVolatile(),
905                           Nd.isNonTemporal(), Nd.isInvariant(),
906                           std::min(Nd.getAlignment(), 4U));
907
908  if (!Subtarget->isLittle())
909    std::swap(Lo, Hi);
910
911  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
912  SDValue Ops[2] = {BP, Hi.getValue(1)};
913  return DAG.getMergeValues(Ops, 2, DL);
914}
915
916SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
917  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
918
919  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
920    return MipsTargetLowering::lowerSTORE(Op, DAG);
921
922  // Replace a double precision store with two extractelement64s and i32 stores.
923  SDLoc DL(Op);
924  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
925  EVT PtrVT = Ptr.getValueType();
926  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
927                           Val, DAG.getConstant(0, MVT::i32));
928  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
929                           Val, DAG.getConstant(1, MVT::i32));
930
931  if (!Subtarget->isLittle())
932    std::swap(Lo, Hi);
933
934  // i32 store to lower address.
935  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
936                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
937                       Nd.getTBAAInfo());
938
939  // i32 store to higher address.
940  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
941  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
942                      Nd.isVolatile(), Nd.isNonTemporal(),
943                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
944}
945
946SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
947                                          bool HasLo, bool HasHi,
948                                          SelectionDAG &DAG) const {
949  EVT Ty = Op.getOperand(0).getValueType();
950  SDLoc DL(Op);
951  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
952                             Op.getOperand(0), Op.getOperand(1));
953  SDValue Lo, Hi;
954
955  if (HasLo)
956    Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
957  if (HasHi)
958    Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
959
960  if (!HasLo || !HasHi)
961    return HasLo ? Lo : Hi;
962
963  SDValue Vals[] = { Lo, Hi };
964  return DAG.getMergeValues(Vals, 2, DL);
965}
966
967
968static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
969  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
970                             DAG.getConstant(0, MVT::i32));
971  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
972                             DAG.getConstant(1, MVT::i32));
973  return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
974}
975
976static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
977  SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
978  SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
979  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
980}
981
982// This function expands mips intrinsic nodes which have 64-bit input operands
983// or output values.
984//
985// out64 = intrinsic-node in64
986// =>
987// lo = copy (extract-element (in64, 0))
988// hi = copy (extract-element (in64, 1))
989// mips-specific-node
990// v0 = copy lo
991// v1 = copy hi
992// out64 = merge-values (v0, v1)
993//
994static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
995  SDLoc DL(Op);
996  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
997  SmallVector<SDValue, 3> Ops;
998  unsigned OpNo = 0;
999
1000  // See if Op has a chain input.
1001  if (HasChainIn)
1002    Ops.push_back(Op->getOperand(OpNo++));
1003
1004  // The next operand is the intrinsic opcode.
1005  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1006
1007  // See if the next operand has type i64.
1008  SDValue Opnd = Op->getOperand(++OpNo), In64;
1009
1010  if (Opnd.getValueType() == MVT::i64)
1011    In64 = initAccumulator(Opnd, DL, DAG);
1012  else
1013    Ops.push_back(Opnd);
1014
1015  // Push the remaining operands.
1016  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1017    Ops.push_back(Op->getOperand(OpNo));
1018
1019  // Add In64 to the end of the list.
1020  if (In64.getNode())
1021    Ops.push_back(In64);
1022
1023  // Scan output.
1024  SmallVector<EVT, 2> ResTys;
1025
1026  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1027       I != E; ++I)
1028    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1029
1030  // Create node.
1031  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
1032  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1033
1034  if (!HasChainIn)
1035    return Out;
1036
1037  assert(Val->getValueType(1) == MVT::Other);
1038  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
1039  return DAG.getMergeValues(Vals, 2, DL);
1040}
1041
1042// Lower an MSA copy intrinsic into the specified SelectionDAG node
1043static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1044  SDLoc DL(Op);
1045  SDValue Vec = Op->getOperand(1);
1046  SDValue Idx = Op->getOperand(2);
1047  EVT ResTy = Op->getValueType(0);
1048  EVT EltTy = Vec->getValueType(0).getVectorElementType();
1049
1050  SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1051                               DAG.getValueType(EltTy));
1052
1053  return Result;
1054}
1055
1056static SDValue
1057lowerMSASplatImm(SDLoc DL, EVT ResTy, SDValue ImmOp, SelectionDAG &DAG) {
1058  EVT ViaVecTy = ResTy;
1059  SmallVector<SDValue, 16> Ops;
1060  SDValue ImmHiOp;
1061
1062  if (ViaVecTy == MVT::v2i64) {
1063    ImmHiOp = DAG.getNode(ISD::SRA, DL, MVT::i32, ImmOp,
1064                          DAG.getConstant(31, MVT::i32));
1065    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i) {
1066      Ops.push_back(ImmHiOp);
1067      Ops.push_back(ImmOp);
1068    }
1069    ViaVecTy = MVT::v4i32;
1070  } else {
1071    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1072      Ops.push_back(ImmOp);
1073  }
1074
1075  SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, &Ops[0],
1076                               Ops.size());
1077
1078  if (ResTy != ViaVecTy)
1079    Result = DAG.getNode(ISD::BITCAST, DL, ResTy, Result);
1080
1081  return Result;
1082}
1083
1084static SDValue
1085lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
1086  return lowerMSASplatImm(SDLoc(Op), Op->getValueType(0),
1087                          Op->getOperand(ImmOp), DAG);
1088}
1089
1090SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1091                                                      SelectionDAG &DAG) const {
1092  SDLoc DL(Op);
1093
1094  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1095  default:
1096    return SDValue();
1097  case Intrinsic::mips_shilo:
1098    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1099  case Intrinsic::mips_dpau_h_qbl:
1100    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1101  case Intrinsic::mips_dpau_h_qbr:
1102    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1103  case Intrinsic::mips_dpsu_h_qbl:
1104    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1105  case Intrinsic::mips_dpsu_h_qbr:
1106    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1107  case Intrinsic::mips_dpa_w_ph:
1108    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1109  case Intrinsic::mips_dps_w_ph:
1110    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1111  case Intrinsic::mips_dpax_w_ph:
1112    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1113  case Intrinsic::mips_dpsx_w_ph:
1114    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1115  case Intrinsic::mips_mulsa_w_ph:
1116    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1117  case Intrinsic::mips_mult:
1118    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1119  case Intrinsic::mips_multu:
1120    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1121  case Intrinsic::mips_madd:
1122    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1123  case Intrinsic::mips_maddu:
1124    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1125  case Intrinsic::mips_msub:
1126    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1127  case Intrinsic::mips_msubu:
1128    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
1129  case Intrinsic::mips_addv_b:
1130  case Intrinsic::mips_addv_h:
1131  case Intrinsic::mips_addv_w:
1132  case Intrinsic::mips_addv_d:
1133    return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1134                       Op->getOperand(2));
1135  case Intrinsic::mips_addvi_b:
1136  case Intrinsic::mips_addvi_h:
1137  case Intrinsic::mips_addvi_w:
1138  case Intrinsic::mips_addvi_d:
1139    return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1140                       lowerMSASplatImm(Op, 2, DAG));
1141  case Intrinsic::mips_and_v:
1142    return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1143                       Op->getOperand(2));
1144  case Intrinsic::mips_andi_b:
1145    return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1146                       lowerMSASplatImm(Op, 2, DAG));
1147  case Intrinsic::mips_bnz_b:
1148  case Intrinsic::mips_bnz_h:
1149  case Intrinsic::mips_bnz_w:
1150  case Intrinsic::mips_bnz_d:
1151    return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1152                       Op->getOperand(1));
1153  case Intrinsic::mips_bnz_v:
1154    return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1155                       Op->getOperand(1));
1156  case Intrinsic::mips_bsel_v:
1157    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1158                       Op->getOperand(1), Op->getOperand(2),
1159                       Op->getOperand(3));
1160  case Intrinsic::mips_bseli_b:
1161    return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1162                       Op->getOperand(1), Op->getOperand(2),
1163                       lowerMSASplatImm(Op, 3, DAG));
1164  case Intrinsic::mips_bz_b:
1165  case Intrinsic::mips_bz_h:
1166  case Intrinsic::mips_bz_w:
1167  case Intrinsic::mips_bz_d:
1168    return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1169                       Op->getOperand(1));
1170  case Intrinsic::mips_bz_v:
1171    return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1172                       Op->getOperand(1));
1173  case Intrinsic::mips_ceq_b:
1174  case Intrinsic::mips_ceq_h:
1175  case Intrinsic::mips_ceq_w:
1176  case Intrinsic::mips_ceq_d:
1177    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1178                        Op->getOperand(2), ISD::SETEQ);
1179  case Intrinsic::mips_ceqi_b:
1180  case Intrinsic::mips_ceqi_h:
1181  case Intrinsic::mips_ceqi_w:
1182  case Intrinsic::mips_ceqi_d:
1183    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1184                        lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1185  case Intrinsic::mips_cle_s_b:
1186  case Intrinsic::mips_cle_s_h:
1187  case Intrinsic::mips_cle_s_w:
1188  case Intrinsic::mips_cle_s_d:
1189    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1190                        Op->getOperand(2), ISD::SETLE);
1191  case Intrinsic::mips_clei_s_b:
1192  case Intrinsic::mips_clei_s_h:
1193  case Intrinsic::mips_clei_s_w:
1194  case Intrinsic::mips_clei_s_d:
1195    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1196                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1197  case Intrinsic::mips_cle_u_b:
1198  case Intrinsic::mips_cle_u_h:
1199  case Intrinsic::mips_cle_u_w:
1200  case Intrinsic::mips_cle_u_d:
1201    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1202                        Op->getOperand(2), ISD::SETULE);
1203  case Intrinsic::mips_clei_u_b:
1204  case Intrinsic::mips_clei_u_h:
1205  case Intrinsic::mips_clei_u_w:
1206  case Intrinsic::mips_clei_u_d:
1207    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1208                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1209  case Intrinsic::mips_clt_s_b:
1210  case Intrinsic::mips_clt_s_h:
1211  case Intrinsic::mips_clt_s_w:
1212  case Intrinsic::mips_clt_s_d:
1213    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1214                        Op->getOperand(2), ISD::SETLT);
1215  case Intrinsic::mips_clti_s_b:
1216  case Intrinsic::mips_clti_s_h:
1217  case Intrinsic::mips_clti_s_w:
1218  case Intrinsic::mips_clti_s_d:
1219    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1220                        lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1221  case Intrinsic::mips_clt_u_b:
1222  case Intrinsic::mips_clt_u_h:
1223  case Intrinsic::mips_clt_u_w:
1224  case Intrinsic::mips_clt_u_d:
1225    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1226                        Op->getOperand(2), ISD::SETULT);
1227  case Intrinsic::mips_clti_u_b:
1228  case Intrinsic::mips_clti_u_h:
1229  case Intrinsic::mips_clti_u_w:
1230  case Intrinsic::mips_clti_u_d:
1231    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1232                        lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
1233  case Intrinsic::mips_copy_s_b:
1234  case Intrinsic::mips_copy_s_h:
1235  case Intrinsic::mips_copy_s_w:
1236    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1237  case Intrinsic::mips_copy_s_d:
1238    // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal.
1239    // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1240    // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1241    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1242                       Op->getOperand(1), Op->getOperand(2));
1243  case Intrinsic::mips_copy_u_b:
1244  case Intrinsic::mips_copy_u_h:
1245  case Intrinsic::mips_copy_u_w:
1246    return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1247  case Intrinsic::mips_copy_u_d:
1248    // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal.
1249    // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type
1250    // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1251    //
1252    // Note: When i64 is illegal, this results in copy_s.w instructions instead
1253    // of copy_u.w instructions. This makes no difference to the behaviour
1254    // since i64 is only illegal when the register file is 32-bit.
1255    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1256                       Op->getOperand(1), Op->getOperand(2));
1257  case Intrinsic::mips_div_s_b:
1258  case Intrinsic::mips_div_s_h:
1259  case Intrinsic::mips_div_s_w:
1260  case Intrinsic::mips_div_s_d:
1261    return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1262                       Op->getOperand(2));
1263  case Intrinsic::mips_div_u_b:
1264  case Intrinsic::mips_div_u_h:
1265  case Intrinsic::mips_div_u_w:
1266  case Intrinsic::mips_div_u_d:
1267    return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1268                       Op->getOperand(2));
1269  case Intrinsic::mips_fadd_w:
1270  case Intrinsic::mips_fadd_d:
1271    return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1272                       Op->getOperand(2));
1273  // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1274  case Intrinsic::mips_fceq_w:
1275  case Intrinsic::mips_fceq_d:
1276    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1277                        Op->getOperand(2), ISD::SETOEQ);
1278  case Intrinsic::mips_fcle_w:
1279  case Intrinsic::mips_fcle_d:
1280    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1281                        Op->getOperand(2), ISD::SETOLE);
1282  case Intrinsic::mips_fclt_w:
1283  case Intrinsic::mips_fclt_d:
1284    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1285                        Op->getOperand(2), ISD::SETOLT);
1286  case Intrinsic::mips_fcne_w:
1287  case Intrinsic::mips_fcne_d:
1288    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1289                        Op->getOperand(2), ISD::SETONE);
1290  case Intrinsic::mips_fcor_w:
1291  case Intrinsic::mips_fcor_d:
1292    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1293                        Op->getOperand(2), ISD::SETO);
1294  case Intrinsic::mips_fcueq_w:
1295  case Intrinsic::mips_fcueq_d:
1296    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1297                        Op->getOperand(2), ISD::SETUEQ);
1298  case Intrinsic::mips_fcule_w:
1299  case Intrinsic::mips_fcule_d:
1300    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1301                        Op->getOperand(2), ISD::SETULE);
1302  case Intrinsic::mips_fcult_w:
1303  case Intrinsic::mips_fcult_d:
1304    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1305                        Op->getOperand(2), ISD::SETULT);
1306  case Intrinsic::mips_fcun_w:
1307  case Intrinsic::mips_fcun_d:
1308    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1309                        Op->getOperand(2), ISD::SETUO);
1310  case Intrinsic::mips_fcune_w:
1311  case Intrinsic::mips_fcune_d:
1312    return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
1313                        Op->getOperand(2), ISD::SETUNE);
1314  case Intrinsic::mips_fdiv_w:
1315  case Intrinsic::mips_fdiv_d:
1316    return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1317                       Op->getOperand(2));
1318  case Intrinsic::mips_ffint_u_w:
1319  case Intrinsic::mips_ffint_u_d:
1320    return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1321                       Op->getOperand(1));
1322  case Intrinsic::mips_ffint_s_w:
1323  case Intrinsic::mips_ffint_s_d:
1324    return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1325                       Op->getOperand(1));
1326  case Intrinsic::mips_fill_b:
1327  case Intrinsic::mips_fill_h:
1328  case Intrinsic::mips_fill_w:
1329  case Intrinsic::mips_fill_d: {
1330    SmallVector<SDValue, 16> Ops;
1331    EVT ResTy = Op->getValueType(0);
1332
1333    for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
1334      Ops.push_back(Op->getOperand(1));
1335
1336    // If ResTy is v2i64 then the type legalizer will break this node down into
1337    // an equivalent v4i32.
1338    return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
1339  }
1340  case Intrinsic::mips_fexp2_w:
1341  case Intrinsic::mips_fexp2_d: {
1342    EVT ResTy = Op->getValueType(0);
1343    return DAG.getNode(
1344        ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1345        DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1346  }
1347  case Intrinsic::mips_flog2_w:
1348  case Intrinsic::mips_flog2_d:
1349    return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
1350  case Intrinsic::mips_fmadd_w:
1351  case Intrinsic::mips_fmadd_d:
1352    return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1353                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1354  case Intrinsic::mips_fmul_w:
1355  case Intrinsic::mips_fmul_d:
1356    return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1357                       Op->getOperand(2));
1358  case Intrinsic::mips_fmsub_w:
1359  case Intrinsic::mips_fmsub_d: {
1360    EVT ResTy = Op->getValueType(0);
1361    return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1362                       DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1363                                   Op->getOperand(2), Op->getOperand(3)));
1364  }
1365  case Intrinsic::mips_frint_w:
1366  case Intrinsic::mips_frint_d:
1367    return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
1368  case Intrinsic::mips_fsqrt_w:
1369  case Intrinsic::mips_fsqrt_d:
1370    return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
1371  case Intrinsic::mips_fsub_w:
1372  case Intrinsic::mips_fsub_d:
1373    return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1374                       Op->getOperand(2));
1375  case Intrinsic::mips_ftrunc_u_w:
1376  case Intrinsic::mips_ftrunc_u_d:
1377    return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1378                       Op->getOperand(1));
1379  case Intrinsic::mips_ftrunc_s_w:
1380  case Intrinsic::mips_ftrunc_s_d:
1381    return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1382                       Op->getOperand(1));
1383  case Intrinsic::mips_ilvev_b:
1384  case Intrinsic::mips_ilvev_h:
1385  case Intrinsic::mips_ilvev_w:
1386  case Intrinsic::mips_ilvev_d:
1387    return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
1388                       Op->getOperand(1), Op->getOperand(2));
1389  case Intrinsic::mips_ilvl_b:
1390  case Intrinsic::mips_ilvl_h:
1391  case Intrinsic::mips_ilvl_w:
1392  case Intrinsic::mips_ilvl_d:
1393    return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
1394                       Op->getOperand(1), Op->getOperand(2));
1395  case Intrinsic::mips_ilvod_b:
1396  case Intrinsic::mips_ilvod_h:
1397  case Intrinsic::mips_ilvod_w:
1398  case Intrinsic::mips_ilvod_d:
1399    return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
1400                       Op->getOperand(1), Op->getOperand(2));
1401  case Intrinsic::mips_ilvr_b:
1402  case Intrinsic::mips_ilvr_h:
1403  case Intrinsic::mips_ilvr_w:
1404  case Intrinsic::mips_ilvr_d:
1405    return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
1406                       Op->getOperand(1), Op->getOperand(2));
1407  case Intrinsic::mips_insert_b:
1408  case Intrinsic::mips_insert_h:
1409  case Intrinsic::mips_insert_w:
1410  case Intrinsic::mips_insert_d:
1411    return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1412                       Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
1413  case Intrinsic::mips_ldi_b:
1414  case Intrinsic::mips_ldi_h:
1415  case Intrinsic::mips_ldi_w:
1416  case Intrinsic::mips_ldi_d:
1417    return lowerMSASplatImm(Op, 1, DAG);
1418  case Intrinsic::mips_lsa: {
1419    EVT ResTy = Op->getValueType(0);
1420    return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1421                       DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1422                                   Op->getOperand(2), Op->getOperand(3)));
1423  }
1424  case Intrinsic::mips_maddv_b:
1425  case Intrinsic::mips_maddv_h:
1426  case Intrinsic::mips_maddv_w:
1427  case Intrinsic::mips_maddv_d: {
1428    EVT ResTy = Op->getValueType(0);
1429    return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1430                       DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1431                                   Op->getOperand(2), Op->getOperand(3)));
1432  }
1433  case Intrinsic::mips_max_s_b:
1434  case Intrinsic::mips_max_s_h:
1435  case Intrinsic::mips_max_s_w:
1436  case Intrinsic::mips_max_s_d:
1437    return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1438                       Op->getOperand(1), Op->getOperand(2));
1439  case Intrinsic::mips_max_u_b:
1440  case Intrinsic::mips_max_u_h:
1441  case Intrinsic::mips_max_u_w:
1442  case Intrinsic::mips_max_u_d:
1443    return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1444                       Op->getOperand(1), Op->getOperand(2));
1445  case Intrinsic::mips_maxi_s_b:
1446  case Intrinsic::mips_maxi_s_h:
1447  case Intrinsic::mips_maxi_s_w:
1448  case Intrinsic::mips_maxi_s_d:
1449    return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1450                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1451  case Intrinsic::mips_maxi_u_b:
1452  case Intrinsic::mips_maxi_u_h:
1453  case Intrinsic::mips_maxi_u_w:
1454  case Intrinsic::mips_maxi_u_d:
1455    return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1456                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1457  case Intrinsic::mips_min_s_b:
1458  case Intrinsic::mips_min_s_h:
1459  case Intrinsic::mips_min_s_w:
1460  case Intrinsic::mips_min_s_d:
1461    return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1462                       Op->getOperand(1), Op->getOperand(2));
1463  case Intrinsic::mips_min_u_b:
1464  case Intrinsic::mips_min_u_h:
1465  case Intrinsic::mips_min_u_w:
1466  case Intrinsic::mips_min_u_d:
1467    return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1468                       Op->getOperand(1), Op->getOperand(2));
1469  case Intrinsic::mips_mini_s_b:
1470  case Intrinsic::mips_mini_s_h:
1471  case Intrinsic::mips_mini_s_w:
1472  case Intrinsic::mips_mini_s_d:
1473    return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
1474                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1475  case Intrinsic::mips_mini_u_b:
1476  case Intrinsic::mips_mini_u_h:
1477  case Intrinsic::mips_mini_u_w:
1478  case Intrinsic::mips_mini_u_d:
1479    return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
1480                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1481  case Intrinsic::mips_mod_s_b:
1482  case Intrinsic::mips_mod_s_h:
1483  case Intrinsic::mips_mod_s_w:
1484  case Intrinsic::mips_mod_s_d:
1485    return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
1486                       Op->getOperand(2));
1487  case Intrinsic::mips_mod_u_b:
1488  case Intrinsic::mips_mod_u_h:
1489  case Intrinsic::mips_mod_u_w:
1490  case Intrinsic::mips_mod_u_d:
1491    return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
1492                       Op->getOperand(2));
1493  case Intrinsic::mips_mulv_b:
1494  case Intrinsic::mips_mulv_h:
1495  case Intrinsic::mips_mulv_w:
1496  case Intrinsic::mips_mulv_d:
1497    return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
1498                       Op->getOperand(2));
1499  case Intrinsic::mips_msubv_b:
1500  case Intrinsic::mips_msubv_h:
1501  case Intrinsic::mips_msubv_w:
1502  case Intrinsic::mips_msubv_d: {
1503    EVT ResTy = Op->getValueType(0);
1504    return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
1505                       DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1506                                   Op->getOperand(2), Op->getOperand(3)));
1507  }
1508  case Intrinsic::mips_nlzc_b:
1509  case Intrinsic::mips_nlzc_h:
1510  case Intrinsic::mips_nlzc_w:
1511  case Intrinsic::mips_nlzc_d:
1512    return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
1513  case Intrinsic::mips_nor_v: {
1514    SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1515                              Op->getOperand(1), Op->getOperand(2));
1516    return DAG.getNOT(DL, Res, Res->getValueType(0));
1517  }
1518  case Intrinsic::mips_nori_b: {
1519    SDValue Res =  DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1520                               Op->getOperand(1),
1521                               lowerMSASplatImm(Op, 2, DAG));
1522    return DAG.getNOT(DL, Res, Res->getValueType(0));
1523  }
1524  case Intrinsic::mips_or_v:
1525    return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
1526                       Op->getOperand(2));
1527  case Intrinsic::mips_ori_b:
1528    return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
1529                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1530  case Intrinsic::mips_pckev_b:
1531  case Intrinsic::mips_pckev_h:
1532  case Intrinsic::mips_pckev_w:
1533  case Intrinsic::mips_pckev_d:
1534    return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
1535                       Op->getOperand(1), Op->getOperand(2));
1536  case Intrinsic::mips_pckod_b:
1537  case Intrinsic::mips_pckod_h:
1538  case Intrinsic::mips_pckod_w:
1539  case Intrinsic::mips_pckod_d:
1540    return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
1541                       Op->getOperand(1), Op->getOperand(2));
1542  case Intrinsic::mips_pcnt_b:
1543  case Intrinsic::mips_pcnt_h:
1544  case Intrinsic::mips_pcnt_w:
1545  case Intrinsic::mips_pcnt_d:
1546    return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
1547  case Intrinsic::mips_shf_b:
1548  case Intrinsic::mips_shf_h:
1549  case Intrinsic::mips_shf_w:
1550    return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
1551                       Op->getOperand(2), Op->getOperand(1));
1552  case Intrinsic::mips_sll_b:
1553  case Intrinsic::mips_sll_h:
1554  case Intrinsic::mips_sll_w:
1555  case Intrinsic::mips_sll_d:
1556    return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
1557                       Op->getOperand(2));
1558  case Intrinsic::mips_slli_b:
1559  case Intrinsic::mips_slli_h:
1560  case Intrinsic::mips_slli_w:
1561  case Intrinsic::mips_slli_d:
1562    return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
1563                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1564  case Intrinsic::mips_splat_b:
1565  case Intrinsic::mips_splat_h:
1566  case Intrinsic::mips_splat_w:
1567  case Intrinsic::mips_splat_d:
1568    // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
1569    // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
1570    // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
1571    // Instead we lower to MipsISD::VSHF and match from there.
1572    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1573                       lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1574                       Op->getOperand(1));
1575  case Intrinsic::mips_splati_b:
1576  case Intrinsic::mips_splati_h:
1577  case Intrinsic::mips_splati_w:
1578  case Intrinsic::mips_splati_d:
1579    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1580                       lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
1581                       Op->getOperand(1));
1582  case Intrinsic::mips_sra_b:
1583  case Intrinsic::mips_sra_h:
1584  case Intrinsic::mips_sra_w:
1585  case Intrinsic::mips_sra_d:
1586    return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
1587                       Op->getOperand(2));
1588  case Intrinsic::mips_srai_b:
1589  case Intrinsic::mips_srai_h:
1590  case Intrinsic::mips_srai_w:
1591  case Intrinsic::mips_srai_d:
1592    return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
1593                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1594  case Intrinsic::mips_srl_b:
1595  case Intrinsic::mips_srl_h:
1596  case Intrinsic::mips_srl_w:
1597  case Intrinsic::mips_srl_d:
1598    return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
1599                       Op->getOperand(2));
1600  case Intrinsic::mips_srli_b:
1601  case Intrinsic::mips_srli_h:
1602  case Intrinsic::mips_srli_w:
1603  case Intrinsic::mips_srli_d:
1604    return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
1605                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1606  case Intrinsic::mips_subv_b:
1607  case Intrinsic::mips_subv_h:
1608  case Intrinsic::mips_subv_w:
1609  case Intrinsic::mips_subv_d:
1610    return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
1611                       Op->getOperand(2));
1612  case Intrinsic::mips_subvi_b:
1613  case Intrinsic::mips_subvi_h:
1614  case Intrinsic::mips_subvi_w:
1615  case Intrinsic::mips_subvi_d:
1616    return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
1617                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1618  case Intrinsic::mips_vshf_b:
1619  case Intrinsic::mips_vshf_h:
1620  case Intrinsic::mips_vshf_w:
1621  case Intrinsic::mips_vshf_d:
1622    return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
1623                       Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
1624  case Intrinsic::mips_xor_v:
1625    return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
1626                       Op->getOperand(2));
1627  case Intrinsic::mips_xori_b:
1628    return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
1629                       Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
1630  }
1631}
1632
1633static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1634  SDLoc DL(Op);
1635  SDValue ChainIn = Op->getOperand(0);
1636  SDValue Address = Op->getOperand(2);
1637  SDValue Offset  = Op->getOperand(3);
1638  EVT ResTy = Op->getValueType(0);
1639  EVT PtrTy = Address->getValueType(0);
1640
1641  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1642
1643  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
1644                     false, false, 16);
1645}
1646
1647SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
1648                                                     SelectionDAG &DAG) const {
1649  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1650  switch (Intr) {
1651  default:
1652    return SDValue();
1653  case Intrinsic::mips_extp:
1654    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
1655  case Intrinsic::mips_extpdp:
1656    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
1657  case Intrinsic::mips_extr_w:
1658    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
1659  case Intrinsic::mips_extr_r_w:
1660    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
1661  case Intrinsic::mips_extr_rs_w:
1662    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
1663  case Intrinsic::mips_extr_s_h:
1664    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
1665  case Intrinsic::mips_mthlip:
1666    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
1667  case Intrinsic::mips_mulsaq_s_w_ph:
1668    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
1669  case Intrinsic::mips_maq_s_w_phl:
1670    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
1671  case Intrinsic::mips_maq_s_w_phr:
1672    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
1673  case Intrinsic::mips_maq_sa_w_phl:
1674    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
1675  case Intrinsic::mips_maq_sa_w_phr:
1676    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
1677  case Intrinsic::mips_dpaq_s_w_ph:
1678    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
1679  case Intrinsic::mips_dpsq_s_w_ph:
1680    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
1681  case Intrinsic::mips_dpaq_sa_l_w:
1682    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
1683  case Intrinsic::mips_dpsq_sa_l_w:
1684    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
1685  case Intrinsic::mips_dpaqx_s_w_ph:
1686    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
1687  case Intrinsic::mips_dpaqx_sa_w_ph:
1688    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
1689  case Intrinsic::mips_dpsqx_s_w_ph:
1690    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
1691  case Intrinsic::mips_dpsqx_sa_w_ph:
1692    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
1693  case Intrinsic::mips_ld_b:
1694  case Intrinsic::mips_ld_h:
1695  case Intrinsic::mips_ld_w:
1696  case Intrinsic::mips_ld_d:
1697   return lowerMSALoadIntr(Op, DAG, Intr);
1698  }
1699}
1700
1701static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
1702  SDLoc DL(Op);
1703  SDValue ChainIn = Op->getOperand(0);
1704  SDValue Value   = Op->getOperand(2);
1705  SDValue Address = Op->getOperand(3);
1706  SDValue Offset  = Op->getOperand(4);
1707  EVT PtrTy = Address->getValueType(0);
1708
1709  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
1710
1711  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
1712                      false, 16);
1713}
1714
1715SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
1716                                                  SelectionDAG &DAG) const {
1717  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1718  switch (Intr) {
1719  default:
1720    return SDValue();
1721  case Intrinsic::mips_st_b:
1722  case Intrinsic::mips_st_h:
1723  case Intrinsic::mips_st_w:
1724  case Intrinsic::mips_st_d:
1725    return lowerMSAStoreIntr(Op, DAG, Intr);
1726  }
1727}
1728
1729/// \brief Check if the given BuildVectorSDNode is a splat.
1730/// This method currently relies on DAG nodes being reused when equivalent,
1731/// so it's possible for this to return false even when isConstantSplat returns
1732/// true.
1733static bool isSplatVector(const BuildVectorSDNode *N) {
1734  unsigned int nOps = N->getNumOperands();
1735  assert(nOps > 1 && "isSplat has 0 or 1 sized build vector");
1736
1737  SDValue Operand0 = N->getOperand(0);
1738
1739  for (unsigned int i = 1; i < nOps; ++i) {
1740    if (N->getOperand(i) != Operand0)
1741      return false;
1742  }
1743
1744  return true;
1745}
1746
1747// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
1748//
1749// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
1750// choose to sign-extend but we could have equally chosen zero-extend. The
1751// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
1752// result into this node later (possibly changing it to a zero-extend in the
1753// process).
1754SDValue MipsSETargetLowering::
1755lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
1756  SDLoc DL(Op);
1757  EVT ResTy = Op->getValueType(0);
1758  SDValue Op0 = Op->getOperand(0);
1759  EVT VecTy = Op0->getValueType(0);
1760
1761  if (!VecTy.is128BitVector())
1762    return SDValue();
1763
1764  if (ResTy.isInteger()) {
1765    SDValue Op1 = Op->getOperand(1);
1766    EVT EltTy = VecTy.getVectorElementType();
1767    return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
1768                       DAG.getValueType(EltTy));
1769  }
1770
1771  return Op;
1772}
1773
1774static bool isConstantOrUndef(const SDValue Op) {
1775  if (Op->getOpcode() == ISD::UNDEF)
1776    return true;
1777  if (dyn_cast<ConstantSDNode>(Op))
1778    return true;
1779  if (dyn_cast<ConstantFPSDNode>(Op))
1780    return true;
1781  return false;
1782}
1783
1784static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
1785  for (unsigned i = 0; i < Op->getNumOperands(); ++i)
1786    if (isConstantOrUndef(Op->getOperand(i)))
1787      return true;
1788  return false;
1789}
1790
1791// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
1792// backend.
1793//
1794// Lowers according to the following rules:
1795// - Constant splats are legal as-is as long as the SplatBitSize is a power of
1796//   2 less than or equal to 64 and the value fits into a signed 10-bit
1797//   immediate
1798// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
1799//   is a power of 2 less than or equal to 64 and the value does not fit into a
1800//   signed 10-bit immediate
1801// - Non-constant splats are legal as-is.
1802// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
1803// - All others are illegal and must be expanded.
1804SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
1805                                                SelectionDAG &DAG) const {
1806  BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
1807  EVT ResTy = Op->getValueType(0);
1808  SDLoc DL(Op);
1809  APInt SplatValue, SplatUndef;
1810  unsigned SplatBitSize;
1811  bool HasAnyUndefs;
1812
1813  if (!Subtarget->hasMSA() || !ResTy.is128BitVector())
1814    return SDValue();
1815
1816  if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1817                            HasAnyUndefs, 8,
1818                            !Subtarget->isLittle()) && SplatBitSize <= 64) {
1819    // We can only cope with 8, 16, 32, or 64-bit elements
1820    if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
1821        SplatBitSize != 64)
1822      return SDValue();
1823
1824    // If the value fits into a simm10 then we can use ldi.[bhwd]
1825    if (SplatValue.isSignedIntN(10))
1826      return Op;
1827
1828    EVT ViaVecTy;
1829
1830    switch (SplatBitSize) {
1831    default:
1832      return SDValue();
1833    case 8:
1834      ViaVecTy = MVT::v16i8;
1835      break;
1836    case 16:
1837      ViaVecTy = MVT::v8i16;
1838      break;
1839    case 32:
1840      ViaVecTy = MVT::v4i32;
1841      break;
1842    case 64:
1843      // There's no fill.d to fall back on for 64-bit values
1844      return SDValue();
1845    }
1846
1847    SmallVector<SDValue, 16> Ops;
1848    SDValue Constant = DAG.getConstant(SplatValue.sextOrSelf(32), MVT::i32);
1849
1850    for (unsigned i = 0; i < ViaVecTy.getVectorNumElements(); ++i)
1851      Ops.push_back(Constant);
1852
1853    SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Node), ViaVecTy,
1854                                 &Ops[0], Ops.size());
1855
1856    if (ViaVecTy != ResTy)
1857      Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
1858
1859    return Result;
1860  } else if (isSplatVector(Node))
1861    return Op;
1862  else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
1863    // Use INSERT_VECTOR_ELT operations rather than expand to stores.
1864    // The resulting code is the same length as the expansion, but it doesn't
1865    // use memory operations
1866    EVT ResTy = Node->getValueType(0);
1867
1868    assert(ResTy.isVector());
1869
1870    unsigned NumElts = ResTy.getVectorNumElements();
1871    SDValue Vector = DAG.getUNDEF(ResTy);
1872    for (unsigned i = 0; i < NumElts; ++i) {
1873      Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
1874                           Node->getOperand(i),
1875                           DAG.getConstant(i, MVT::i32));
1876    }
1877    return Vector;
1878  }
1879
1880  return SDValue();
1881}
1882
1883// Lower VECTOR_SHUFFLE into SHF (if possible).
1884//
1885// SHF splits the vector into blocks of four elements, then shuffles these
1886// elements according to a <4 x i2> constant (encoded as an integer immediate).
1887//
1888// It is therefore possible to lower into SHF when the mask takes the form:
1889//   <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
1890// When undef's appear they are treated as if they were whatever value is
1891// necessary in order to fit the above form.
1892//
1893// For example:
1894//   %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
1895//                      <8 x i32> <i32 3, i32 2, i32 1, i32 0,
1896//                                 i32 7, i32 6, i32 5, i32 4>
1897// is lowered to:
1898//   (SHF_H $w0, $w1, 27)
1899// where the 27 comes from:
1900//   3 + (2 << 2) + (1 << 4) + (0 << 6)
1901static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
1902                                       SmallVector<int, 16> Indices,
1903                                       SelectionDAG &DAG) {
1904  int SHFIndices[4] = { -1, -1, -1, -1 };
1905
1906  if (Indices.size() < 4)
1907    return SDValue();
1908
1909  for (unsigned i = 0; i < 4; ++i) {
1910    for (unsigned j = i; j < Indices.size(); j += 4) {
1911      int Idx = Indices[j];
1912
1913      // Convert from vector index to 4-element subvector index
1914      // If an index refers to an element outside of the subvector then give up
1915      if (Idx != -1) {
1916        Idx -= 4 * (j / 4);
1917        if (Idx < 0 || Idx >= 4)
1918          return SDValue();
1919      }
1920
1921      // If the mask has an undef, replace it with the current index.
1922      // Note that it might still be undef if the current index is also undef
1923      if (SHFIndices[i] == -1)
1924        SHFIndices[i] = Idx;
1925
1926      // Check that non-undef values are the same as in the mask. If they
1927      // aren't then give up
1928      if (!(Idx == -1 || Idx == SHFIndices[i]))
1929        return SDValue();
1930    }
1931  }
1932
1933  // Calculate the immediate. Replace any remaining undefs with zero
1934  APInt Imm(32, 0);
1935  for (int i = 3; i >= 0; --i) {
1936    int Idx = SHFIndices[i];
1937
1938    if (Idx == -1)
1939      Idx = 0;
1940
1941    Imm <<= 2;
1942    Imm |= Idx & 0x3;
1943  }
1944
1945  return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy,
1946                     DAG.getConstant(Imm, MVT::i32), Op->getOperand(0));
1947}
1948
1949// Lower VECTOR_SHUFFLE into ILVEV (if possible).
1950//
1951// ILVEV interleaves the even elements from each vector.
1952//
1953// It is possible to lower into ILVEV when the mask takes the form:
1954//   <0, n, 2, n+2, 4, n+4, ...>
1955// where n is the number of elements in the vector.
1956//
1957// When undef's appear in the mask they are treated as if they were whatever
1958// value is necessary in order to fit the above form.
1959static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
1960                                         SmallVector<int, 16> Indices,
1961                                         SelectionDAG &DAG) {
1962  assert ((Indices.size() % 2) == 0);
1963  int WsIdx = 0;
1964  int WtIdx = ResTy.getVectorNumElements();
1965
1966  for (unsigned i = 0; i < Indices.size(); i += 2) {
1967    if (Indices[i] != -1 && Indices[i] != WsIdx)
1968      return SDValue();
1969    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
1970      return SDValue();
1971    WsIdx += 2;
1972    WtIdx += 2;
1973  }
1974
1975  return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0),
1976                     Op->getOperand(1));
1977}
1978
1979// Lower VECTOR_SHUFFLE into ILVOD (if possible).
1980//
1981// ILVOD interleaves the odd elements from each vector.
1982//
1983// It is possible to lower into ILVOD when the mask takes the form:
1984//   <1, n+1, 3, n+3, 5, n+5, ...>
1985// where n is the number of elements in the vector.
1986//
1987// When undef's appear in the mask they are treated as if they were whatever
1988// value is necessary in order to fit the above form.
1989static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
1990                                         SmallVector<int, 16> Indices,
1991                                         SelectionDAG &DAG) {
1992  assert ((Indices.size() % 2) == 0);
1993  int WsIdx = 1;
1994  int WtIdx = ResTy.getVectorNumElements() + 1;
1995
1996  for (unsigned i = 0; i < Indices.size(); i += 2) {
1997    if (Indices[i] != -1 && Indices[i] != WsIdx)
1998      return SDValue();
1999    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2000      return SDValue();
2001    WsIdx += 2;
2002    WtIdx += 2;
2003  }
2004
2005  return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0),
2006                     Op->getOperand(1));
2007}
2008
2009// Lower VECTOR_SHUFFLE into ILVL (if possible).
2010//
2011// ILVL interleaves consecutive elements from the left half of each vector.
2012//
2013// It is possible to lower into ILVL when the mask takes the form:
2014//   <0, n, 1, n+1, 2, n+2, ...>
2015// where n is the number of elements in the vector.
2016//
2017// When undef's appear in the mask they are treated as if they were whatever
2018// value is necessary in order to fit the above form.
2019static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2020                                        SmallVector<int, 16> Indices,
2021                                        SelectionDAG &DAG) {
2022  assert ((Indices.size() % 2) == 0);
2023  int WsIdx = 0;
2024  int WtIdx = ResTy.getVectorNumElements();
2025
2026  for (unsigned i = 0; i < Indices.size(); i += 2) {
2027    if (Indices[i] != -1 && Indices[i] != WsIdx)
2028      return SDValue();
2029    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2030      return SDValue();
2031    WsIdx ++;
2032    WtIdx ++;
2033  }
2034
2035  return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0),
2036                     Op->getOperand(1));
2037}
2038
2039// Lower VECTOR_SHUFFLE into ILVR (if possible).
2040//
2041// ILVR interleaves consecutive elements from the right half of each vector.
2042//
2043// It is possible to lower into ILVR when the mask takes the form:
2044//   <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2045// where n is the number of elements in the vector and x is half n.
2046//
2047// When undef's appear in the mask they are treated as if they were whatever
2048// value is necessary in order to fit the above form.
2049static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2050                                        SmallVector<int, 16> Indices,
2051                                        SelectionDAG &DAG) {
2052  assert ((Indices.size() % 2) == 0);
2053  unsigned NumElts = ResTy.getVectorNumElements();
2054  int WsIdx = NumElts / 2;
2055  int WtIdx = NumElts + NumElts / 2;
2056
2057  for (unsigned i = 0; i < Indices.size(); i += 2) {
2058    if (Indices[i] != -1 && Indices[i] != WsIdx)
2059      return SDValue();
2060    if (Indices[i+1] != -1 && Indices[i+1] != WtIdx)
2061      return SDValue();
2062    WsIdx ++;
2063    WtIdx ++;
2064  }
2065
2066  return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0),
2067                     Op->getOperand(1));
2068}
2069
2070// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2071//
2072// PCKEV copies the even elements of each vector into the result vector.
2073//
2074// It is possible to lower into PCKEV when the mask takes the form:
2075//   <0, 2, 4, ..., n, n+2, n+4, ...>
2076// where n is the number of elements in the vector.
2077//
2078// When undef's appear in the mask they are treated as if they were whatever
2079// value is necessary in order to fit the above form.
2080static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2081                                         SmallVector<int, 16> Indices,
2082                                         SelectionDAG &DAG) {
2083  assert ((Indices.size() % 2) == 0);
2084  int Idx = 0;
2085
2086  for (unsigned i = 0; i < Indices.size(); ++i) {
2087    if (Indices[i] != -1 && Indices[i] != Idx)
2088      return SDValue();
2089    Idx += 2;
2090  }
2091
2092  return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0),
2093                     Op->getOperand(1));
2094}
2095
2096// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2097//
2098// PCKOD copies the odd elements of each vector into the result vector.
2099//
2100// It is possible to lower into PCKOD when the mask takes the form:
2101//   <1, 3, 5, ..., n+1, n+3, n+5, ...>
2102// where n is the number of elements in the vector.
2103//
2104// When undef's appear in the mask they are treated as if they were whatever
2105// value is necessary in order to fit the above form.
2106static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2107                                         SmallVector<int, 16> Indices,
2108                                         SelectionDAG &DAG) {
2109  assert ((Indices.size() % 2) == 0);
2110  int Idx = 1;
2111
2112  for (unsigned i = 0; i < Indices.size(); ++i) {
2113    if (Indices[i] != -1 && Indices[i] != Idx)
2114      return SDValue();
2115    Idx += 2;
2116  }
2117
2118  return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0),
2119                     Op->getOperand(1));
2120}
2121
2122// Lower VECTOR_SHUFFLE into VSHF.
2123//
2124// This mostly consists of converting the shuffle indices in Indices into a
2125// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2126// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2127// if the type is v8i16 and all the indices are less than 8 then the second
2128// operand is unused and can be replaced with anything. We choose to replace it
2129// with the used operand since this reduces the number of instructions overall.
2130static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2131                                        SmallVector<int, 16> Indices,
2132                                        SelectionDAG &DAG) {
2133  SmallVector<SDValue, 16> Ops;
2134  SDValue Op0;
2135  SDValue Op1;
2136  EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2137  EVT MaskEltTy = MaskVecTy.getVectorElementType();
2138  bool Using1stVec = false;
2139  bool Using2ndVec = false;
2140  SDLoc DL(Op);
2141  int ResTyNumElts = ResTy.getVectorNumElements();
2142
2143  for (int i = 0; i < ResTyNumElts; ++i) {
2144    // Idx == -1 means UNDEF
2145    int Idx = Indices[i];
2146
2147    if (0 <= Idx && Idx < ResTyNumElts)
2148      Using1stVec = true;
2149    if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2150      Using2ndVec = true;
2151  }
2152
2153  for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2154       ++I)
2155    Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy));
2156
2157  SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0],
2158                                Ops.size());
2159
2160  if (Using1stVec && Using2ndVec) {
2161    Op0 = Op->getOperand(0);
2162    Op1 = Op->getOperand(1);
2163  } else if (Using1stVec)
2164    Op0 = Op1 = Op->getOperand(0);
2165  else if (Using2ndVec)
2166    Op0 = Op1 = Op->getOperand(1);
2167  else
2168    llvm_unreachable("shuffle vector mask references neither vector operand?");
2169
2170  return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1);
2171}
2172
2173// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2174// indices in the shuffle.
2175SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2176                                                  SelectionDAG &DAG) const {
2177  ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2178  EVT ResTy = Op->getValueType(0);
2179
2180  if (!ResTy.is128BitVector())
2181    return SDValue();
2182
2183  int ResTyNumElts = ResTy.getVectorNumElements();
2184  SmallVector<int, 16> Indices;
2185
2186  for (int i = 0; i < ResTyNumElts; ++i)
2187    Indices.push_back(Node->getMaskElt(i));
2188
2189  SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG);
2190  if (Result.getNode())
2191    return Result;
2192  Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG);
2193  if (Result.getNode())
2194    return Result;
2195  Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG);
2196  if (Result.getNode())
2197    return Result;
2198  Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG);
2199  if (Result.getNode())
2200    return Result;
2201  Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG);
2202  if (Result.getNode())
2203    return Result;
2204  Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG);
2205  if (Result.getNode())
2206    return Result;
2207  Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG);
2208  if (Result.getNode())
2209    return Result;
2210  return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2211}
2212
2213MachineBasicBlock * MipsSETargetLowering::
2214emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2215  // $bb:
2216  //  bposge32_pseudo $vr0
2217  //  =>
2218  // $bb:
2219  //  bposge32 $tbb
2220  // $fbb:
2221  //  li $vr2, 0
2222  //  b $sink
2223  // $tbb:
2224  //  li $vr1, 1
2225  // $sink:
2226  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2227
2228  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2229  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2230  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2231  DebugLoc DL = MI->getDebugLoc();
2232  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2233  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2234  MachineFunction *F = BB->getParent();
2235  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2236  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2237  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2238  F->insert(It, FBB);
2239  F->insert(It, TBB);
2240  F->insert(It, Sink);
2241
2242  // Transfer the remainder of BB and its successor edges to Sink.
2243  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2244               BB->end());
2245  Sink->transferSuccessorsAndUpdatePHIs(BB);
2246
2247  // Add successors.
2248  BB->addSuccessor(FBB);
2249  BB->addSuccessor(TBB);
2250  FBB->addSuccessor(Sink);
2251  TBB->addSuccessor(Sink);
2252
2253  // Insert the real bposge32 instruction to $BB.
2254  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
2255
2256  // Fill $FBB.
2257  unsigned VR2 = RegInfo.createVirtualRegister(RC);
2258  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2259    .addReg(Mips::ZERO).addImm(0);
2260  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2261
2262  // Fill $TBB.
2263  unsigned VR1 = RegInfo.createVirtualRegister(RC);
2264  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2265    .addReg(Mips::ZERO).addImm(1);
2266
2267  // Insert phi function to $Sink.
2268  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2269          MI->getOperand(0).getReg())
2270    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2271
2272  MI->eraseFromParent();   // The pseudo instruction is gone now.
2273  return Sink;
2274}
2275
2276MachineBasicBlock * MipsSETargetLowering::
2277emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2278                     unsigned BranchOp) const{
2279  // $bb:
2280  //  vany_nonzero $rd, $ws
2281  //  =>
2282  // $bb:
2283  //  bnz.b $ws, $tbb
2284  //  b $fbb
2285  // $fbb:
2286  //  li $rd1, 0
2287  //  b $sink
2288  // $tbb:
2289  //  li $rd2, 1
2290  // $sink:
2291  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
2292
2293  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2294  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2295  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2296  DebugLoc DL = MI->getDebugLoc();
2297  const BasicBlock *LLVM_BB = BB->getBasicBlock();
2298  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
2299  MachineFunction *F = BB->getParent();
2300  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2301  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2302  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
2303  F->insert(It, FBB);
2304  F->insert(It, TBB);
2305  F->insert(It, Sink);
2306
2307  // Transfer the remainder of BB and its successor edges to Sink.
2308  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
2309               BB->end());
2310  Sink->transferSuccessorsAndUpdatePHIs(BB);
2311
2312  // Add successors.
2313  BB->addSuccessor(FBB);
2314  BB->addSuccessor(TBB);
2315  FBB->addSuccessor(Sink);
2316  TBB->addSuccessor(Sink);
2317
2318  // Insert the real bnz.b instruction to $BB.
2319  BuildMI(BB, DL, TII->get(BranchOp))
2320    .addReg(MI->getOperand(1).getReg())
2321    .addMBB(TBB);
2322
2323  // Fill $FBB.
2324  unsigned RD1 = RegInfo.createVirtualRegister(RC);
2325  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
2326    .addReg(Mips::ZERO).addImm(0);
2327  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2328
2329  // Fill $TBB.
2330  unsigned RD2 = RegInfo.createVirtualRegister(RC);
2331  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
2332    .addReg(Mips::ZERO).addImm(1);
2333
2334  // Insert phi function to $Sink.
2335  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2336          MI->getOperand(0).getReg())
2337    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
2338
2339  MI->eraseFromParent();   // The pseudo instruction is gone now.
2340  return Sink;
2341}
2342
2343// Emit the COPY_FW pseudo instruction.
2344//
2345// copy_fw_pseudo $fd, $ws, n
2346// =>
2347// copy_u_w $rt, $ws, $n
2348// mtc1     $rt, $fd
2349//
2350// When n is zero, the equivalent operation can be performed with (potentially)
2351// zero instructions due to register overlaps. This optimization is never valid
2352// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
2353MachineBasicBlock * MipsSETargetLowering::
2354emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
2355  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2356  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2357  DebugLoc DL = MI->getDebugLoc();
2358  unsigned Fd = MI->getOperand(0).getReg();
2359  unsigned Ws = MI->getOperand(1).getReg();
2360  unsigned Lane = MI->getOperand(2).getImm();
2361
2362  if (Lane == 0)
2363    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2364  else {
2365    unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2366
2367    BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
2368    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2369  }
2370
2371  MI->eraseFromParent();   // The pseudo instruction is gone now.
2372  return BB;
2373}
2374
2375// Emit the COPY_FD pseudo instruction.
2376//
2377// copy_fd_pseudo $fd, $ws, n
2378// =>
2379// splati.d $wt, $ws, $n
2380// copy $fd, $wt:sub_64
2381//
2382// When n is zero, the equivalent operation can be performed with (potentially)
2383// zero instructions due to register overlaps. This optimization is always
2384// valid because FR=1 mode which is the only supported mode in MSA.
2385MachineBasicBlock * MipsSETargetLowering::
2386emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
2387  assert(Subtarget->isFP64bit());
2388
2389  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2390  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2391  unsigned Fd  = MI->getOperand(0).getReg();
2392  unsigned Ws  = MI->getOperand(1).getReg();
2393  unsigned Lane = MI->getOperand(2).getImm() * 2;
2394  DebugLoc DL = MI->getDebugLoc();
2395
2396  if (Lane == 0)
2397    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
2398  else {
2399    unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2400
2401    BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
2402    BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
2403  }
2404
2405  MI->eraseFromParent();   // The pseudo instruction is gone now.
2406  return BB;
2407}
2408
2409// Emit the INSERT_FW pseudo instruction.
2410//
2411// insert_fw_pseudo $wd, $wd_in, $n, $fs
2412// =>
2413// subreg_to_reg $wt:sub_lo, $fs
2414// insve_w $wd[$n], $wd_in, $wt[0]
2415MachineBasicBlock *
2416MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
2417                                    MachineBasicBlock *BB) const {
2418  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2419  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2420  DebugLoc DL = MI->getDebugLoc();
2421  unsigned Wd = MI->getOperand(0).getReg();
2422  unsigned Wd_in = MI->getOperand(1).getReg();
2423  unsigned Lane = MI->getOperand(2).getImm();
2424  unsigned Fs = MI->getOperand(3).getReg();
2425  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2426
2427  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2428      .addImm(0)
2429      .addReg(Fs)
2430      .addImm(Mips::sub_lo);
2431  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
2432      .addReg(Wd_in)
2433      .addImm(Lane)
2434      .addReg(Wt);
2435
2436  MI->eraseFromParent(); // The pseudo instruction is gone now.
2437  return BB;
2438}
2439
2440// Emit the INSERT_FD pseudo instruction.
2441//
2442// insert_fd_pseudo $wd, $fs, n
2443// =>
2444// subreg_to_reg $wt:sub_64, $fs
2445// insve_d $wd[$n], $wd_in, $wt[0]
2446MachineBasicBlock *
2447MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
2448                                    MachineBasicBlock *BB) const {
2449  assert(Subtarget->isFP64bit());
2450
2451  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2452  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2453  DebugLoc DL = MI->getDebugLoc();
2454  unsigned Wd = MI->getOperand(0).getReg();
2455  unsigned Wd_in = MI->getOperand(1).getReg();
2456  unsigned Lane = MI->getOperand(2).getImm();
2457  unsigned Fs = MI->getOperand(3).getReg();
2458  unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2459
2460  BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
2461      .addImm(0)
2462      .addReg(Fs)
2463      .addImm(Mips::sub_64);
2464  BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
2465      .addReg(Wd_in)
2466      .addImm(Lane)
2467      .addReg(Wt);
2468
2469  MI->eraseFromParent(); // The pseudo instruction is gone now.
2470  return BB;
2471}
2472
2473// Emit the FILL_FW pseudo instruction.
2474//
2475// fill_fw_pseudo $wd, $fs
2476// =>
2477// implicit_def $wt1
2478// insert_subreg $wt2:subreg_lo, $wt1, $fs
2479// splati.w $wd, $wt2[0]
2480MachineBasicBlock *
2481MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
2482                                  MachineBasicBlock *BB) const {
2483  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2484  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2485  DebugLoc DL = MI->getDebugLoc();
2486  unsigned Wd = MI->getOperand(0).getReg();
2487  unsigned Fs = MI->getOperand(1).getReg();
2488  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2489  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2490
2491  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2492  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2493      .addReg(Wt1)
2494      .addReg(Fs)
2495      .addImm(Mips::sub_lo);
2496  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
2497
2498  MI->eraseFromParent(); // The pseudo instruction is gone now.
2499  return BB;
2500}
2501
2502// Emit the FILL_FD pseudo instruction.
2503//
2504// fill_fd_pseudo $wd, $fs
2505// =>
2506// implicit_def $wt1
2507// insert_subreg $wt2:subreg_64, $wt1, $fs
2508// splati.d $wd, $wt2[0]
2509MachineBasicBlock *
2510MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
2511                                  MachineBasicBlock *BB) const {
2512  assert(Subtarget->isFP64bit());
2513
2514  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2515  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2516  DebugLoc DL = MI->getDebugLoc();
2517  unsigned Wd = MI->getOperand(0).getReg();
2518  unsigned Fs = MI->getOperand(1).getReg();
2519  unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2520  unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
2521
2522  BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
2523  BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
2524      .addReg(Wt1)
2525      .addReg(Fs)
2526      .addImm(Mips::sub_64);
2527  BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
2528
2529  MI->eraseFromParent();   // The pseudo instruction is gone now.
2530  return BB;
2531}
2532
2533// Emit the FEXP2_W_1 pseudo instructions.
2534//
2535// fexp2_w_1_pseudo $wd, $wt
2536// =>
2537// ldi.w $ws, 1
2538// fexp2.w $wd, $ws, $wt
2539MachineBasicBlock *
2540MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
2541                                    MachineBasicBlock *BB) const {
2542  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2543  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2544  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
2545  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2546  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2547  DebugLoc DL = MI->getDebugLoc();
2548
2549  // Splat 1.0 into a vector
2550  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
2551  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
2552
2553  // Emit 1.0 * fexp2(Wt)
2554  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
2555      .addReg(Ws2)
2556      .addReg(MI->getOperand(1).getReg());
2557
2558  MI->eraseFromParent(); // The pseudo instruction is gone now.
2559  return BB;
2560}
2561
2562// Emit the FEXP2_D_1 pseudo instructions.
2563//
2564// fexp2_d_1_pseudo $wd, $wt
2565// =>
2566// ldi.d $ws, 1
2567// fexp2.d $wd, $ws, $wt
2568MachineBasicBlock *
2569MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
2570                                    MachineBasicBlock *BB) const {
2571  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2572  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
2573  const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
2574  unsigned Ws1 = RegInfo.createVirtualRegister(RC);
2575  unsigned Ws2 = RegInfo.createVirtualRegister(RC);
2576  DebugLoc DL = MI->getDebugLoc();
2577
2578  // Splat 1.0 into a vector
2579  BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
2580  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
2581
2582  // Emit 1.0 * fexp2(Wt)
2583  BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
2584      .addReg(Ws2)
2585      .addReg(MI->getOperand(1).getReg());
2586
2587  MI->eraseFromParent(); // The pseudo instruction is gone now.
2588  return BB;
2589}
2590