MipsSEISelLowering.cpp revision ddfbd5805478cf108156bb0159b7495d2b236f7e 
1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
14#include "MipsRegisterInfo.h"
15#include "MipsTargetMachine.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22using namespace llvm;
23
24static cl::opt<bool>
25EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26                    cl::desc("MIPS: Enable tail calls."), cl::init(false));
27
28static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
29                                   cl::desc("Expand double precision loads and "
30                                            "stores to their single precision "
31                                            "counterparts"));
32
33MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
34  : MipsTargetLowering(TM) {
35  // Set up the register classes
36
37  clearRegisterClasses();
38
39  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
40
41  if (HasMips64)
42    addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43
44  if (Subtarget->hasDSP()) {
45    MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
46
47    for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
48      addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
49
50      // Expand all builtin opcodes.
51      for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
52        setOperationAction(Opc, VecTys[i], Expand);
53
54      setOperationAction(ISD::ADD, VecTys[i], Legal);
55      setOperationAction(ISD::SUB, VecTys[i], Legal);
56      setOperationAction(ISD::LOAD, VecTys[i], Legal);
57      setOperationAction(ISD::STORE, VecTys[i], Legal);
58      setOperationAction(ISD::BITCAST, VecTys[i], Legal);
59    }
60
61    // Expand all truncating stores and extending loads.
62    unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
63    unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
64
65    for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) {
66      for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1)
67        setTruncStoreAction((MVT::SimpleValueType)VT0,
68                            (MVT::SimpleValueType)VT1, Expand);
69
70      setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
71      setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
72      setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
73    }
74
75    setTargetDAGCombine(ISD::SHL);
76    setTargetDAGCombine(ISD::SRA);
77    setTargetDAGCombine(ISD::SRL);
78    setTargetDAGCombine(ISD::SETCC);
79    setTargetDAGCombine(ISD::VSELECT);
80  }
81
82  if (Subtarget->hasDSPR2())
83    setOperationAction(ISD::MUL, MVT::v2i16, Legal);
84
85  if (Subtarget->hasMSA()) {
86    addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
87    addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
88    addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
89    addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
90    addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
91    addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
92    addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
93  }
94
95  if (!Subtarget->mipsSEUsesSoftFloat()) {
96    addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
97
98    // When dealing with single precision only, use libcalls
99    if (!Subtarget->isSingleFloat()) {
100      if (Subtarget->isFP64bit())
101        addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
102      else
103        addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
104    }
105  }
106
107  setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
108  setOperationAction(ISD::UMUL_LOHI,          MVT::i32, Custom);
109  setOperationAction(ISD::MULHS,              MVT::i32, Custom);
110  setOperationAction(ISD::MULHU,              MVT::i32, Custom);
111
112  if (HasMips64) {
113    setOperationAction(ISD::MULHS,            MVT::i64, Custom);
114    setOperationAction(ISD::MULHU,            MVT::i64, Custom);
115    setOperationAction(ISD::MUL,              MVT::i64, Custom);
116  }
117
118  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
119  setOperationAction(ISD::INTRINSIC_W_CHAIN,  MVT::i64, Custom);
120
121  setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
122  setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
123  setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
124  setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
125  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Custom);
126  setOperationAction(ISD::LOAD,               MVT::i32, Custom);
127  setOperationAction(ISD::STORE,              MVT::i32, Custom);
128
129  setTargetDAGCombine(ISD::ADDE);
130  setTargetDAGCombine(ISD::SUBE);
131  setTargetDAGCombine(ISD::MUL);
132
133  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
135  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
136
137  if (NoDPLoadStore) {
138    setOperationAction(ISD::LOAD, MVT::f64, Custom);
139    setOperationAction(ISD::STORE, MVT::f64, Custom);
140  }
141
142  computeRegisterProperties();
143}
144
145const MipsTargetLowering *
146llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
147  return new MipsSETargetLowering(TM);
148}
149
150void MipsSETargetLowering::
151addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
152  addRegisterClass(Ty, RC);
153
154  // Expand all builtin opcodes.
155  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
156    setOperationAction(Opc, Ty, Expand);
157
158  setOperationAction(ISD::BITCAST, Ty, Legal);
159  setOperationAction(ISD::LOAD, Ty, Legal);
160  setOperationAction(ISD::STORE, Ty, Legal);
161
162}
163
164void MipsSETargetLowering::
165addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
166  addRegisterClass(Ty, RC);
167
168  // Expand all builtin opcodes.
169  for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
170    setOperationAction(Opc, Ty, Expand);
171
172  setOperationAction(ISD::LOAD, Ty, Legal);
173  setOperationAction(ISD::STORE, Ty, Legal);
174  setOperationAction(ISD::BITCAST, Ty, Legal);
175}
176
177bool
178MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
179  MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
180
181  switch (SVT) {
182  case MVT::i64:
183  case MVT::i32:
184    if (Fast)
185      *Fast = true;
186    return true;
187  default:
188    return false;
189  }
190}
191
192SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
193                                             SelectionDAG &DAG) const {
194  switch(Op.getOpcode()) {
195  case ISD::LOAD:  return lowerLOAD(Op, DAG);
196  case ISD::STORE: return lowerSTORE(Op, DAG);
197  case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
198  case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
199  case ISD::MULHS:     return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
200  case ISD::MULHU:     return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
201  case ISD::MUL:       return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
202  case ISD::SDIVREM:   return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
203  case ISD::UDIVREM:   return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
204                                          DAG);
205  case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
206  case ISD::INTRINSIC_W_CHAIN:  return lowerINTRINSIC_W_CHAIN(Op, DAG);
207  case ISD::INTRINSIC_VOID:     return lowerINTRINSIC_VOID(Op, DAG);
208  }
209
210  return MipsTargetLowering::LowerOperation(Op, DAG);
211}
212
213// selectMADD -
214// Transforms a subgraph in CurDAG if the following pattern is found:
215//  (addc multLo, Lo0), (adde multHi, Hi0),
216// where,
217//  multHi/Lo: product of multiplication
218//  Lo0: initial value of Lo register
219//  Hi0: initial value of Hi register
220// Return true if pattern matching was successful.
221static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
222  // ADDENode's second operand must be a flag output of an ADDC node in order
223  // for the matching to be successful.
224  SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
225
226  if (ADDCNode->getOpcode() != ISD::ADDC)
227    return false;
228
229  SDValue MultHi = ADDENode->getOperand(0);
230  SDValue MultLo = ADDCNode->getOperand(0);
231  SDNode *MultNode = MultHi.getNode();
232  unsigned MultOpc = MultHi.getOpcode();
233
234  // MultHi and MultLo must be generated by the same node,
235  if (MultLo.getNode() != MultNode)
236    return false;
237
238  // and it must be a multiplication.
239  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
240    return false;
241
242  // MultLo amd MultHi must be the first and second output of MultNode
243  // respectively.
244  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
245    return false;
246
247  // Transform this to a MADD only if ADDENode and ADDCNode are the only users
248  // of the values of MultNode, in which case MultNode will be removed in later
249  // phases.
250  // If there exist users other than ADDENode or ADDCNode, this function returns
251  // here, which will result in MultNode being mapped to a single MULT
252  // instruction node rather than a pair of MULT and MADD instructions being
253  // produced.
254  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
255    return false;
256
257  SDLoc DL(ADDENode);
258
259  // Initialize accumulator.
260  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
261                                  ADDCNode->getOperand(1),
262                                  ADDENode->getOperand(1));
263
264  // create MipsMAdd(u) node
265  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
266
267  SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
268                                 MultNode->getOperand(0),// Factor 0
269                                 MultNode->getOperand(1),// Factor 1
270                                 ACCIn);
271
272  // replace uses of adde and addc here
273  if (!SDValue(ADDCNode, 0).use_empty()) {
274    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
275    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
276                                    LoIdx);
277    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
278  }
279  if (!SDValue(ADDENode, 0).use_empty()) {
280    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
281    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
282                                    HiIdx);
283    CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
284  }
285
286  return true;
287}
288
289// selectMSUB -
290// Transforms a subgraph in CurDAG if the following pattern is found:
291//  (addc Lo0, multLo), (sube Hi0, multHi),
292// where,
293//  multHi/Lo: product of multiplication
294//  Lo0: initial value of Lo register
295//  Hi0: initial value of Hi register
296// Return true if pattern matching was successful.
297static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
298  // SUBENode's second operand must be a flag output of an SUBC node in order
299  // for the matching to be successful.
300  SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
301
302  if (SUBCNode->getOpcode() != ISD::SUBC)
303    return false;
304
305  SDValue MultHi = SUBENode->getOperand(1);
306  SDValue MultLo = SUBCNode->getOperand(1);
307  SDNode *MultNode = MultHi.getNode();
308  unsigned MultOpc = MultHi.getOpcode();
309
310  // MultHi and MultLo must be generated by the same node,
311  if (MultLo.getNode() != MultNode)
312    return false;
313
314  // and it must be a multiplication.
315  if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
316    return false;
317
318  // MultLo amd MultHi must be the first and second output of MultNode
319  // respectively.
320  if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
321    return false;
322
323  // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
324  // of the values of MultNode, in which case MultNode will be removed in later
325  // phases.
326  // If there exist users other than SUBENode or SUBCNode, this function returns
327  // here, which will result in MultNode being mapped to a single MULT
328  // instruction node rather than a pair of MULT and MSUB instructions being
329  // produced.
330  if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
331    return false;
332
333  SDLoc DL(SUBENode);
334
335  // Initialize accumulator.
336  SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
337                                  SUBCNode->getOperand(0),
338                                  SUBENode->getOperand(0));
339
340  // create MipsSub(u) node
341  MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
342
343  SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
344                                 MultNode->getOperand(0),// Factor 0
345                                 MultNode->getOperand(1),// Factor 1
346                                 ACCIn);
347
348  // replace uses of sube and subc here
349  if (!SDValue(SUBCNode, 0).use_empty()) {
350    SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
351    SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
352                                    LoIdx);
353    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
354  }
355  if (!SDValue(SUBENode, 0).use_empty()) {
356    SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
357    SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
358                                    HiIdx);
359    CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
360  }
361
362  return true;
363}
364
365static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
366                                  TargetLowering::DAGCombinerInfo &DCI,
367                                  const MipsSubtarget *Subtarget) {
368  if (DCI.isBeforeLegalize())
369    return SDValue();
370
371  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
372      selectMADD(N, &DAG))
373    return SDValue(N, 0);
374
375  return SDValue();
376}
377
378static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
379                                  TargetLowering::DAGCombinerInfo &DCI,
380                                  const MipsSubtarget *Subtarget) {
381  if (DCI.isBeforeLegalize())
382    return SDValue();
383
384  if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
385      selectMSUB(N, &DAG))
386    return SDValue(N, 0);
387
388  return SDValue();
389}
390
391static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
392                            EVT ShiftTy, SelectionDAG &DAG) {
393  // Clear the upper (64 - VT.sizeInBits) bits.
394  C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
395
396  // Return 0.
397  if (C == 0)
398    return DAG.getConstant(0, VT);
399
400  // Return x.
401  if (C == 1)
402    return X;
403
404  // If c is power of 2, return (shl x, log2(c)).
405  if (isPowerOf2_64(C))
406    return DAG.getNode(ISD::SHL, DL, VT, X,
407                       DAG.getConstant(Log2_64(C), ShiftTy));
408
409  unsigned Log2Ceil = Log2_64_Ceil(C);
410  uint64_t Floor = 1LL << Log2_64(C);
411  uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
412
413  // If |c - floor_c| <= |c - ceil_c|,
414  // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
415  // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
416  if (C - Floor <= Ceil - C) {
417    SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
418    SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
419    return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
420  }
421
422  // If |c - floor_c| > |c - ceil_c|,
423  // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
424  SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
425  SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
426  return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
427}
428
429static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
430                                 const TargetLowering::DAGCombinerInfo &DCI,
431                                 const MipsSETargetLowering *TL) {
432  EVT VT = N->getValueType(0);
433
434  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
435    if (!VT.isVector())
436      return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N),
437                          VT, TL->getScalarShiftAmountTy(VT), DAG);
438
439  return SDValue(N, 0);
440}
441
442static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
443                                      SelectionDAG &DAG,
444                                      const MipsSubtarget *Subtarget) {
445  // See if this is a vector splat immediate node.
446  APInt SplatValue, SplatUndef;
447  unsigned SplatBitSize;
448  bool HasAnyUndefs;
449  unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
450  BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
451
452  if (!BV ||
453      !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
454                           EltSize, !Subtarget->isLittle()) ||
455      (SplatBitSize != EltSize) ||
456      (SplatValue.getZExtValue() >= EltSize))
457    return SDValue();
458
459  return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0),
460                     DAG.getConstant(SplatValue.getZExtValue(), MVT::i32));
461}
462
463static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
464                                 TargetLowering::DAGCombinerInfo &DCI,
465                                 const MipsSubtarget *Subtarget) {
466  EVT Ty = N->getValueType(0);
467
468  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
469    return SDValue();
470
471  return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
472}
473
474static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
475                                 TargetLowering::DAGCombinerInfo &DCI,
476                                 const MipsSubtarget *Subtarget) {
477  EVT Ty = N->getValueType(0);
478
479  if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2()))
480    return SDValue();
481
482  return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
483}
484
485
486static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
487                                 TargetLowering::DAGCombinerInfo &DCI,
488                                 const MipsSubtarget *Subtarget) {
489  EVT Ty = N->getValueType(0);
490
491  if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8))
492    return SDValue();
493
494  return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
495}
496
497static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
498  bool IsV216 = (Ty == MVT::v2i16);
499
500  switch (CC) {
501  case ISD::SETEQ:
502  case ISD::SETNE:  return true;
503  case ISD::SETLT:
504  case ISD::SETLE:
505  case ISD::SETGT:
506  case ISD::SETGE:  return IsV216;
507  case ISD::SETULT:
508  case ISD::SETULE:
509  case ISD::SETUGT:
510  case ISD::SETUGE: return !IsV216;
511  default:          return false;
512  }
513}
514
515static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
516  EVT Ty = N->getValueType(0);
517
518  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
519    return SDValue();
520
521  if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
522    return SDValue();
523
524  return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
525                     N->getOperand(1), N->getOperand(2));
526}
527
528static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
529  EVT Ty = N->getValueType(0);
530
531  if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
532    return SDValue();
533
534  SDValue SetCC = N->getOperand(0);
535
536  if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
537    return SDValue();
538
539  return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
540                     SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
541                     N->getOperand(2), SetCC.getOperand(2));
542}
543
544SDValue
545MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
546  SelectionDAG &DAG = DCI.DAG;
547  SDValue Val;
548
549  switch (N->getOpcode()) {
550  case ISD::ADDE:
551    return performADDECombine(N, DAG, DCI, Subtarget);
552  case ISD::SUBE:
553    return performSUBECombine(N, DAG, DCI, Subtarget);
554  case ISD::MUL:
555    return performMULCombine(N, DAG, DCI, this);
556  case ISD::SHL:
557    return performSHLCombine(N, DAG, DCI, Subtarget);
558  case ISD::SRA:
559    return performSRACombine(N, DAG, DCI, Subtarget);
560  case ISD::SRL:
561    return performSRLCombine(N, DAG, DCI, Subtarget);
562  case ISD::VSELECT:
563    return performVSELECTCombine(N, DAG);
564  case ISD::SETCC: {
565    Val = performSETCCCombine(N, DAG);
566    break;
567  }
568  }
569
570  if (Val.getNode())
571    return Val;
572
573  return MipsTargetLowering::PerformDAGCombine(N, DCI);
574}
575
576MachineBasicBlock *
577MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
578                                                  MachineBasicBlock *BB) const {
579  switch (MI->getOpcode()) {
580  default:
581    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
582  case Mips::BPOSGE32_PSEUDO:
583    return emitBPOSGE32(MI, BB);
584  case Mips::SNZ_B_PSEUDO:
585    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
586  case Mips::SNZ_H_PSEUDO:
587    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
588  case Mips::SNZ_W_PSEUDO:
589    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
590  case Mips::SNZ_D_PSEUDO:
591    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
592  case Mips::SNZ_V_PSEUDO:
593    return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
594  case Mips::SZ_B_PSEUDO:
595    return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
596  case Mips::SZ_H_PSEUDO:
597    return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
598  case Mips::SZ_W_PSEUDO:
599    return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
600  case Mips::SZ_D_PSEUDO:
601    return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
602  case Mips::SZ_V_PSEUDO:
603    return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
604  }
605}
606
607bool MipsSETargetLowering::
608isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
609                                  unsigned NextStackOffset,
610                                  const MipsFunctionInfo& FI) const {
611  if (!EnableMipsTailCalls)
612    return false;
613
614  // Return false if either the callee or caller has a byval argument.
615  if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
616    return false;
617
618  // Return true if the callee's argument area is no larger than the
619  // caller's.
620  return NextStackOffset <= FI.getIncomingArgSize();
621}
622
623void MipsSETargetLowering::
624getOpndList(SmallVectorImpl<SDValue> &Ops,
625            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
626            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
627            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
628  // T9 should contain the address of the callee function if
629  // -reloction-model=pic or it is an indirect call.
630  if (IsPICCall || !GlobalOrExternal) {
631    unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
632    RegsToPass.push_front(std::make_pair(T9Reg, Callee));
633  } else
634    Ops.push_back(Callee);
635
636  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
637                                  InternalLinkage, CLI, Callee, Chain);
638}
639
640SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
641  LoadSDNode &Nd = *cast<LoadSDNode>(Op);
642
643  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
644    return MipsTargetLowering::lowerLOAD(Op, DAG);
645
646  // Replace a double precision load with two i32 loads and a buildpair64.
647  SDLoc DL(Op);
648  SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
649  EVT PtrVT = Ptr.getValueType();
650
651  // i32 load from lower address.
652  SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
653                           MachinePointerInfo(), Nd.isVolatile(),
654                           Nd.isNonTemporal(), Nd.isInvariant(),
655                           Nd.getAlignment());
656
657  // i32 load from higher address.
658  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
659  SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
660                           MachinePointerInfo(), Nd.isVolatile(),
661                           Nd.isNonTemporal(), Nd.isInvariant(),
662                           std::min(Nd.getAlignment(), 4U));
663
664  if (!Subtarget->isLittle())
665    std::swap(Lo, Hi);
666
667  SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
668  SDValue Ops[2] = {BP, Hi.getValue(1)};
669  return DAG.getMergeValues(Ops, 2, DL);
670}
671
672SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
673  StoreSDNode &Nd = *cast<StoreSDNode>(Op);
674
675  if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
676    return MipsTargetLowering::lowerSTORE(Op, DAG);
677
678  // Replace a double precision store with two extractelement64s and i32 stores.
679  SDLoc DL(Op);
680  SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
681  EVT PtrVT = Ptr.getValueType();
682  SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
683                           Val, DAG.getConstant(0, MVT::i32));
684  SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
685                           Val, DAG.getConstant(1, MVT::i32));
686
687  if (!Subtarget->isLittle())
688    std::swap(Lo, Hi);
689
690  // i32 store to lower address.
691  Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
692                       Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
693                       Nd.getTBAAInfo());
694
695  // i32 store to higher address.
696  Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT));
697  return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
698                      Nd.isVolatile(), Nd.isNonTemporal(),
699                      std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo());
700}
701
702SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
703                                          bool HasLo, bool HasHi,
704                                          SelectionDAG &DAG) const {
705  EVT Ty = Op.getOperand(0).getValueType();
706  SDLoc DL(Op);
707  SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
708                             Op.getOperand(0), Op.getOperand(1));
709  SDValue Lo, Hi;
710
711  if (HasLo)
712    Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
713                     DAG.getConstant(Mips::sub_lo, MVT::i32));
714  if (HasHi)
715    Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
716                     DAG.getConstant(Mips::sub_hi, MVT::i32));
717
718  if (!HasLo || !HasHi)
719    return HasLo ? Lo : Hi;
720
721  SDValue Vals[] = { Lo, Hi };
722  return DAG.getMergeValues(Vals, 2, DL);
723}
724
725
726static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
727  SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
728                             DAG.getConstant(0, MVT::i32));
729  SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
730                             DAG.getConstant(1, MVT::i32));
731  return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
732}
733
734static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
735  SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
736                           DAG.getConstant(Mips::sub_lo, MVT::i32));
737  SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
738                           DAG.getConstant(Mips::sub_hi, MVT::i32));
739  return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
740}
741
742// This function expands mips intrinsic nodes which have 64-bit input operands
743// or output values.
744//
745// out64 = intrinsic-node in64
746// =>
747// lo = copy (extract-element (in64, 0))
748// hi = copy (extract-element (in64, 1))
749// mips-specific-node
750// v0 = copy lo
751// v1 = copy hi
752// out64 = merge-values (v0, v1)
753//
754static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
755  SDLoc DL(Op);
756  bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
757  SmallVector<SDValue, 3> Ops;
758  unsigned OpNo = 0;
759
760  // See if Op has a chain input.
761  if (HasChainIn)
762    Ops.push_back(Op->getOperand(OpNo++));
763
764  // The next operand is the intrinsic opcode.
765  assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
766
767  // See if the next operand has type i64.
768  SDValue Opnd = Op->getOperand(++OpNo), In64;
769
770  if (Opnd.getValueType() == MVT::i64)
771    In64 = initAccumulator(Opnd, DL, DAG);
772  else
773    Ops.push_back(Opnd);
774
775  // Push the remaining operands.
776  for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
777    Ops.push_back(Op->getOperand(OpNo));
778
779  // Add In64 to the end of the list.
780  if (In64.getNode())
781    Ops.push_back(In64);
782
783  // Scan output.
784  SmallVector<EVT, 2> ResTys;
785
786  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
787       I != E; ++I)
788    ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
789
790  // Create node.
791  SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
792  SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
793
794  if (!HasChainIn)
795    return Out;
796
797  assert(Val->getValueType(1) == MVT::Other);
798  SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
799  return DAG.getMergeValues(Vals, 2, DL);
800}
801
802static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
803  SDLoc DL(Op);
804  SDValue Value = Op->getOperand(1);
805  EVT ResTy = Op->getValueType(0);
806
807  SDValue Result = DAG.getNode(Opc, DL, ResTy, Value);
808
809  return Result;
810}
811
812SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
813                                                      SelectionDAG &DAG) const {
814  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
815  default:
816    return SDValue();
817  case Intrinsic::mips_shilo:
818    return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
819  case Intrinsic::mips_dpau_h_qbl:
820    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
821  case Intrinsic::mips_dpau_h_qbr:
822    return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
823  case Intrinsic::mips_dpsu_h_qbl:
824    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
825  case Intrinsic::mips_dpsu_h_qbr:
826    return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
827  case Intrinsic::mips_dpa_w_ph:
828    return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
829  case Intrinsic::mips_dps_w_ph:
830    return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
831  case Intrinsic::mips_dpax_w_ph:
832    return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
833  case Intrinsic::mips_dpsx_w_ph:
834    return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
835  case Intrinsic::mips_mulsa_w_ph:
836    return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
837  case Intrinsic::mips_mult:
838    return lowerDSPIntr(Op, DAG, MipsISD::Mult);
839  case Intrinsic::mips_multu:
840    return lowerDSPIntr(Op, DAG, MipsISD::Multu);
841  case Intrinsic::mips_madd:
842    return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
843  case Intrinsic::mips_maddu:
844    return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
845  case Intrinsic::mips_msub:
846    return lowerDSPIntr(Op, DAG, MipsISD::MSub);
847  case Intrinsic::mips_msubu:
848    return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
849  case Intrinsic::mips_bnz_b:
850  case Intrinsic::mips_bnz_h:
851  case Intrinsic::mips_bnz_w:
852  case Intrinsic::mips_bnz_d:
853    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_NONZERO);
854  case Intrinsic::mips_bnz_v:
855    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_NONZERO);
856  case Intrinsic::mips_bz_b:
857  case Intrinsic::mips_bz_h:
858  case Intrinsic::mips_bz_w:
859  case Intrinsic::mips_bz_d:
860    return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
861  case Intrinsic::mips_bz_v:
862    return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
863  }
864}
865
866static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
867  SDLoc DL(Op);
868  SDValue ChainIn = Op->getOperand(0);
869  SDValue Address = Op->getOperand(2);
870  SDValue Offset  = Op->getOperand(3);
871  EVT ResTy = Op->getValueType(0);
872  EVT PtrTy = Address->getValueType(0);
873
874  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
875
876  return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
877                     false, false, 16);
878}
879
880SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
881                                                     SelectionDAG &DAG) const {
882  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
883  switch (Intr) {
884  default:
885    return SDValue();
886  case Intrinsic::mips_extp:
887    return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
888  case Intrinsic::mips_extpdp:
889    return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
890  case Intrinsic::mips_extr_w:
891    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
892  case Intrinsic::mips_extr_r_w:
893    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
894  case Intrinsic::mips_extr_rs_w:
895    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
896  case Intrinsic::mips_extr_s_h:
897    return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
898  case Intrinsic::mips_mthlip:
899    return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
900  case Intrinsic::mips_mulsaq_s_w_ph:
901    return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
902  case Intrinsic::mips_maq_s_w_phl:
903    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
904  case Intrinsic::mips_maq_s_w_phr:
905    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
906  case Intrinsic::mips_maq_sa_w_phl:
907    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
908  case Intrinsic::mips_maq_sa_w_phr:
909    return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
910  case Intrinsic::mips_dpaq_s_w_ph:
911    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
912  case Intrinsic::mips_dpsq_s_w_ph:
913    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
914  case Intrinsic::mips_dpaq_sa_l_w:
915    return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
916  case Intrinsic::mips_dpsq_sa_l_w:
917    return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
918  case Intrinsic::mips_dpaqx_s_w_ph:
919    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
920  case Intrinsic::mips_dpaqx_sa_w_ph:
921    return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
922  case Intrinsic::mips_dpsqx_s_w_ph:
923    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
924  case Intrinsic::mips_dpsqx_sa_w_ph:
925    return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
926  case Intrinsic::mips_ld_b:
927  case Intrinsic::mips_ld_h:
928  case Intrinsic::mips_ld_w:
929  case Intrinsic::mips_ld_d:
930  case Intrinsic::mips_ldx_b:
931  case Intrinsic::mips_ldx_h:
932  case Intrinsic::mips_ldx_w:
933  case Intrinsic::mips_ldx_d:
934   return lowerMSALoadIntr(Op, DAG, Intr);
935  }
936}
937
938static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
939  SDLoc DL(Op);
940  SDValue ChainIn = Op->getOperand(0);
941  SDValue Value   = Op->getOperand(2);
942  SDValue Address = Op->getOperand(3);
943  SDValue Offset  = Op->getOperand(4);
944  EVT PtrTy = Address->getValueType(0);
945
946  Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
947
948  return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
949                      false, 16);
950}
951
952SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
953                                                  SelectionDAG &DAG) const {
954  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
955  switch (Intr) {
956  default:
957    return SDValue();
958  case Intrinsic::mips_st_b:
959  case Intrinsic::mips_st_h:
960  case Intrinsic::mips_st_w:
961  case Intrinsic::mips_st_d:
962  case Intrinsic::mips_stx_b:
963  case Intrinsic::mips_stx_h:
964  case Intrinsic::mips_stx_w:
965  case Intrinsic::mips_stx_d:
966    return lowerMSAStoreIntr(Op, DAG, Intr);
967  }
968}
969
970MachineBasicBlock * MipsSETargetLowering::
971emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
972  // $bb:
973  //  bposge32_pseudo $vr0
974  //  =>
975  // $bb:
976  //  bposge32 $tbb
977  // $fbb:
978  //  li $vr2, 0
979  //  b $sink
980  // $tbb:
981  //  li $vr1, 1
982  // $sink:
983  //  $vr0 = phi($vr2, $fbb, $vr1, $tbb)
984
985  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
986  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
987  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
988  DebugLoc DL = MI->getDebugLoc();
989  const BasicBlock *LLVM_BB = BB->getBasicBlock();
990  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
991  MachineFunction *F = BB->getParent();
992  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
993  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
994  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
995  F->insert(It, FBB);
996  F->insert(It, TBB);
997  F->insert(It, Sink);
998
999  // Transfer the remainder of BB and its successor edges to Sink.
1000  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1001               BB->end());
1002  Sink->transferSuccessorsAndUpdatePHIs(BB);
1003
1004  // Add successors.
1005  BB->addSuccessor(FBB);
1006  BB->addSuccessor(TBB);
1007  FBB->addSuccessor(Sink);
1008  TBB->addSuccessor(Sink);
1009
1010  // Insert the real bposge32 instruction to $BB.
1011  BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1012
1013  // Fill $FBB.
1014  unsigned VR2 = RegInfo.createVirtualRegister(RC);
1015  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1016    .addReg(Mips::ZERO).addImm(0);
1017  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1018
1019  // Fill $TBB.
1020  unsigned VR1 = RegInfo.createVirtualRegister(RC);
1021  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1022    .addReg(Mips::ZERO).addImm(1);
1023
1024  // Insert phi function to $Sink.
1025  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1026          MI->getOperand(0).getReg())
1027    .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1028
1029  MI->eraseFromParent();   // The pseudo instruction is gone now.
1030  return Sink;
1031}
1032
1033MachineBasicBlock * MipsSETargetLowering::
1034emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
1035                     unsigned BranchOp) const{
1036  // $bb:
1037  //  vany_nonzero $rd, $ws
1038  //  =>
1039  // $bb:
1040  //  bnz.b $ws, $tbb
1041  //  b $fbb
1042  // $fbb:
1043  //  li $rd1, 0
1044  //  b $sink
1045  // $tbb:
1046  //  li $rd2, 1
1047  // $sink:
1048  //  $rd = phi($rd1, $fbb, $rd2, $tbb)
1049
1050  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1051  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1052  const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1053  DebugLoc DL = MI->getDebugLoc();
1054  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1055  MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1056  MachineFunction *F = BB->getParent();
1057  MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1058  MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1059  MachineBasicBlock *Sink  = F->CreateMachineBasicBlock(LLVM_BB);
1060  F->insert(It, FBB);
1061  F->insert(It, TBB);
1062  F->insert(It, Sink);
1063
1064  // Transfer the remainder of BB and its successor edges to Sink.
1065  Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1066               BB->end());
1067  Sink->transferSuccessorsAndUpdatePHIs(BB);
1068
1069  // Add successors.
1070  BB->addSuccessor(FBB);
1071  BB->addSuccessor(TBB);
1072  FBB->addSuccessor(Sink);
1073  TBB->addSuccessor(Sink);
1074
1075  // Insert the real bnz.b instruction to $BB.
1076  BuildMI(BB, DL, TII->get(BranchOp))
1077    .addReg(MI->getOperand(1).getReg())
1078    .addMBB(TBB);
1079
1080  // Fill $FBB.
1081  unsigned RD1 = RegInfo.createVirtualRegister(RC);
1082  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
1083    .addReg(Mips::ZERO).addImm(0);
1084  BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1085
1086  // Fill $TBB.
1087  unsigned RD2 = RegInfo.createVirtualRegister(RC);
1088  BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
1089    .addReg(Mips::ZERO).addImm(1);
1090
1091  // Insert phi function to $Sink.
1092  BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1093          MI->getOperand(0).getReg())
1094    .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
1095
1096  MI->eraseFromParent();   // The pseudo instruction is gone now.
1097  return Sink;
1098}
1099